JPH02284251A - Data transfer control system for hard disk - Google Patents

Abstract

PURPOSE:To realize efficient and high-speed data transfer by dividing a buffer memory into, at least, three blocks, and executing the data transfer between a host computer and a hard disk drive while shifting these blocks. CONSTITUTION:The buffer memories 4A, 4B, 4C, a DMA control circuit 5, updown counters 6A, 6B, 6C and a data transfer control circuit 7 are provided, and in the case where data is transferred through the buffer memory 4 from the host computer 1 to the hard disk drive 2 (hard disk controller 3) or in a direction opposite to this, the data transfer is executed while shifting three buffer memory blocks. Thus, the efficient data transfer can be realized.

Description

Detailed Description of the Invention Technical Field The present invention is a hard disk data transfer control method that transfers data from a host computer to a hard disk drive or vice versa via a buffer memory. There are a single buffering method and a double buffering method.

When transferring data from the host computer to the node disk drive, in the single buffering method, data is transferred from the host computer to the buffer memory, and after the data transfer is completed, data is transferred from the buffer memory to the node disk drive. - Data transfer is performed to the hard disk drive.

In the double buffering method, the buffer memory is separated into two independent blocks (buffer memories A and B), and the buffer memory A1 is connected to the host computer.
Data is transferred from buffer memory B to the hard disk drive independently, and when buffer memory A becomes full and buffer memory B becomes empty, the buffer memory is switched and the host computer transfers data from buffer memory B1 to buffer memory A. Start transferring data to the hard disk drive. This operation is executed repeatedly.

In the conventional single buffering method described above, unless one data transfer is completed, the other data transfer cannot be performed.

In addition, in the double buffering method, even if transfer is more efficient than in the single buffering method, unless one data transfer is completed and the other data transfer is not completed (in other words, both data transfers are (unless the process is completed), data transfer cannot be continued by switching the buffer memory.

OBJECTS OF THE INVENTION Accordingly, an object of the present invention is to provide a hard disk data transfer control system that allows efficient data transfer.

According to the present invention, a buffer memory connected to a computer system is provided, and when data transfer between a host computer and a hard disk drive is performed by a direct memory access method via the buffer memory, at least A hard disk data transfer control method is obtained, which is characterized in that the data transfer is performed by dividing the data into three blocks and shifting the at least three buffer memory blocks.

Embodiment Next, please refer to the drawings showing an embodiment of the present invention! Dashi,
The present invention will be described in detail.

FIG. 1 is a block diagram of a data transfer system according to an embodiment of the present invention. In this embodiment, data is transferred from the host computer 1 to the hard disk drive 2 (hard disk controller 3) or vice versa via the buffer memory 4, but for the sake of simplicity, the following In the description, a write operation from the host computer 1 to the hard disk drive 2 (hard disk controller 3) will be described.

A direct memory access (hereinafter referred to as DMA) request signal a from the host computer 1 is sent to the DMA IQ.
8 circuit 5, and data transfer from host computer 1 to buffer memory 4A is started.

The number of data transferred from the host computer 1 to the buffer memory 4A is counted by the up signal input from the DMA control circuit 5 to the up/down counter 6A. When the count value of the counter 6A reaches a value indicating that the buffer memory 4A is full, the data transfer control unit 3 sends a message to the three buffer memories 4 (4A, 4B, 4C).
Control signal C is output.

The control signal C includes a write enable signal that connects the buffer memory 4 to the host computer 1 and a read enable signal that connects the buffer memory 4 to the hard disk controller 3. By this control signal C, the three buffer memories 4
is shifted, the host computer 1 transfers data to the empty buffer memory 4B or 4C (in this case, buffer memory 4B), and the full buffer memory 4A transfers data to the hard disk controller 3. Perform the transfer. Prior to data transfer from the buffer memory 4A to the hard disk controller 3, the hard disk controller 3 outputs a DMA request signal d.

When there is a difference between the transfer capacity of the host computer 1 and the transfer capacity of the hard disk controller 3, if the data transfer from the host computer 1 to the buffer memory 4B ends earlier (that is, the buffer memory 4B becomes full). (if it is earlier), the control signal C is input to the three buffer memories 4, and the host computer 1 executes data transfer to the empty buffer memory 4C. Data transfer from the buffer memory 4A to the hard disk controller 3 continues as is.

When the transfer is completed (the buffer memory 4A becomes empty), the control signal C is manually applied to the three buffer memories 4, and data transfer from the full buffer memory 4B to the hard disk controller 3 is executed. .

Even if the data transfer from the host computer 1 to the buffer memory 4C is completed, if the data transfer from the buffer memory 4A to the hard disk controller 3 is not yet completed, a write mask is sent from the data transfer control unit 7 to the host computer 1. It outputs the signal e to stop writing to the buffer memory, and waits for the data transfer from the buffer memory 4A to the hard disk controller 3 to be completed.

When the data transfer is completed, the write mask signal e is cleared.

Next, if the data transfer from the buffer memory 4A to the hard disk controller 3 is completed earlier, the data transfer control unit 7 outputs a read mask signal f to the node disk controller 3 to transfer data from the buffer memory 4B. The reading is stopped and waits for the data transfer from the host computer 1 to the buffer memory 4B to be completed.

When the data transfer is completed, the read mask signal f is cleared. At the same time, the control signal C is input to the three buffer memories 4, and the host computer 1 inputs the control signal C to the three buffer memories 4.
C and data transfer from the buffer memory 4B to the hard disk controller 3, respectively.

When transferring data from the host computer 1 to the buffer memory 4, if the last data ends before the buffer memory reaches a full state, the host computer 1
Using the transfer count end signal g from the data transfer controller 7, the control signal C is inputted to the three buffer memories 4, and data transfer from the last buffer memory 4 to the hard disk controller 3 is executed.

Furthermore, when the transfer direction is a read operation from the hard disk controller 3, the logical conditions described above are simply contradictory.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, the buffer memory provided between the host computer and the hard disk drive is divided into at least three blocks, and while these blocks are shifted, the buffer memory provided between the host computer and the hard disk drive is divided into at least three blocks. By performing data transfer between
Efficient high-speed data transfer can be achieved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention. Explanation of symbols of main parts 1...Host computer 2...Hard disk drive 3...
Hard disk controller 4 (4A, 4B, 4C) ... Data storage buffer memory 5 ...D
MA control circuit applicant: NEC Corporation (1 other person)

Claims (1)

[Claims] (1) When having a buffer memory connected to a computer system and performing data transfer between a host computer and a hard disk drive using the direct memory access method via the buffer memory, the buffer memory is divided into at least three blocks. , while shifting the at least three buffer memory blocks;
A data transfer control method for a hard disk, characterized in that the data transfer is performed as described above.