JPH03189755A - Inter-memory transfer device - Google Patents

Abstract

PURPOSE:To increase the inter-memory transfer speed by using one of two memories as an I/O. CONSTITUTION:A transferer memory 1 is handled as an I/O. When a transfer request signal (i) is outputted from a command control circuit 7 via a DMA channel, a DMA controller 3 acquires a bus and receives a grant signal (c) sent back. A selector 6 is switched by the signal (c), and the initial value of a counter 4 containing a loading function is outputted to a local address (f) of the memory 1. When the signal (c) is invalidated, a transferee memory 2 counts up the counter 4 by one at the edge of the signal (c). Then the signal (i) is outputted from the circuit 7 and the second transfer is started. Thus the inter-memory transfer speed is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention is used in computers, word processors, and the like. DMA (Direct Memory Access)
ss) relates to an inter-memory data transfer device using a channel.

(Prior Art) In recent years, data transfer in floppy disk drives, hard disk drives, etc. inside computers, word processors, etc. is generally performed by a CPU (Central Processing Unit).
The MA controller is used because it allows high-speed data transfer without using the MA controller. The DMA controller enables high-speed data transfer between an input/output port (hereinafter referred to as Ilo) and memory, or between memory. □Once the transfer destination memory address is initialized, the rest is automatically performed. The address is incremented, data can be transferred a set number of times, and it has a function to notify you when it is finished, making it useful for high-speed transfer. Note that in the above transfer between memories, it is necessary to also specify the address of the transfer source memory.

(Problem to be Solved by the Invention) However, since high-speed transfer is possible, the MA controller can also perform memory-to-memory transfer as shown in FIG. 3, as shown in FIG. Compared to the normal l/O-memory transfer,
It is unreasonable to require two channels of DMA controller, and since it is necessary to output both the transfer source memory address and the transfer destination memory address to a common bus, the transfer cycle becomes two, and therefore There was a drawback that the transfer time was doubled.

The present invention eliminates the problems of the conventional memory-to-memory transfer described above, and
An object of the present invention is to provide a memory-to-memory transfer device using one channel of a DMA controller.

(Means for Solving the Problems) The present invention has achieved the above object by providing a counter with a load function that can set an arbitrary address as an initial value by the CPU to either the memory to be transferred or the memory to be transferred. This is achieved by an inter-memory transfer device equipped with a selector that outputs either the counter output or the system address as a local address.

(Function) According to the present invention, by regarding one memory as Ilo, transfer between memories can be performed as an I/O-memory transfer, and therefore efficient memory transfer between memories can be performed. This can be done extremely quickly.

(Example) Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, where 1 is a transfer source memory in which data a sent from another device is written, and 2 is a transfer source memory connected to a data bus b. 3 is a DMA controller; 4 is a counter with a load function; an arbitrary address initial value can be set by the CPU 5;

It is counted by the permission signal C. A selector 6 switches between two types of inputs, the address bus d of the system and the counter output e of the counter 4 with a load function, in response to a permission signal C from the DMA controller 3, and outputs a local address f. 7 is a command control circuit,
I/O command g output from DMA controller 3
is converted into a local command h of the transfer source memory 1, and outputs a transfer request signal i to the DMA controller 3.

The present invention has the above configuration, and its data transfer operation will be explained below using an example of transfer from the transfer source memory 1 to the transfer destination memory 2.

Generally, data input from the outside, for example from an input device such as a scanner, is typically stored in a small scale memory such as a line memory. When transferring the memory data to the system memory, if the former small-scale memory is used as the transfer source memory 1 and the latter system memory is used as the transfer destination memory 2, the start address of the transfer memory to be read is set in the counter 4 with a load function. Set as an initial value from the CPU 5.

The designation of the l/O-memory transfer mode and the transfer destination address are set in the DMA controller 3 from the same <CPU 5. At this time, the transfer source memory 1 is treated as Ilo,
When the command control circuit 7 outputs the transfer request signal i using one DMA channel, the DMA controller 3 acquires the bus and the permission signal C is returned.

The selector 6 is switched by the signal C, and the transfer source memory 1
The initial value of the counter 4 with load function is output to the local address f. A transfer destination address is output from the DMA controller 3 to the address bus d. Also, D
The I/O command g output from the MA controller 3 is output by the command control circuit 7 to the source memory 1 as a local command h such as read, write, output control, etc. for the destination memory 2, and the data is transferred to the source memory 1. It is output to bus b.

On the other hand, the transfer destination memory 2 takes in data through normal DMA operation, and when the first transfer cycle is completed and the permission signal C is invalidated, the counter 4 with a load function is incremented by one count at the edge of the signal. , the counter output e is a value obtained by adding 1 to the above-mentioned counter value. Transfer request signal i
is output from the command control circuit 7 and the second transfer is started. In the same procedure as the first transfer, an address obtained by adding 1 to the transfer start address is set to the local address f and the address bus d is has DMA controller 3
The address incremented by +1 is output, and the second transfer cycle is performed.

Thereafter, in the same way, along with the transfer cycle, the address bus d
, the local address bus f is raised, and the data transfer between the target memories is completed.

(Effects of the Invention) As is clear from the above explanation, the present invention enables the DMA controller to transfer data between memories in half the time compared to the conventional method, and the DMA controller uses only one channel. This has the effect of improving the throughput of the entire system.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the configuration of the present invention, Figure 2 is a DM
FIG. 3 is a timing diagram of data transfer between memories of the A controller. FIG. 3 is a timing diagram of data transfer between I/O and memories of the DMA controller. 1...Transfer source memory, 2...Transfer destination memory,
3... DMA controller, 4... Counter with load function, 5... CPU, 6... Selector, 7... Command control circuit.

Claims (1)

[Claims] An arbitrary initial value is set by a transfer source memory and a transfer destination memory connected to the same data bus, a DMA controller that transfers data using a DMA channel, and a central processing unit, and counting is performed by a permission signal from the DMA controller. A counter with a load function to be uploaded, a selector that outputs either the counter output or the address bus of the system by switching the output according to a permission signal from the DMA controller, and an I/O command of the DMA controller to the transfer source. An inter-memory transfer device comprising a command control circuit that outputs a local command to a memory and sends a data transfer request signal to the DMA controller.