JPH02252024A - Microprogram loading system - Google Patents

Abstract

PURPOSE:To attain plural processing more than the capacity of a memory without dropping a processing speed by connecting plural banks to be independently accessed to control a control memory, and loading a microprogram to another bank during the execution of the microprogram. CONSTITUTION:The microprogram controlled by a general microprocessor and loaded to a bank WCS1 in control memory 13 to be a RAM based upon a sequencer 11 is read out to execute the program. On the other hand, an WCS selection control circuit 17 uses a bank WCS2 capable of independently accessing the bank WCS1 by address information from the sequencer 11 as the succeeding loading bank to load the microprogram to the WCS2. When the execution of the program is advanced, the bank WCS1 is loaded by the circuit 17, the WCS2 is switched to the executing bank. The repeat of such operations makes more than the capacity of the memory 13 without dropping the processing capacity execution of complex microprogram possible.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a microprogram loading method in a microprogram-controlled data processing device, and particularly to the specification of a microprogram control equipped with a writable control memory having a limited capacity. Microprogram loading method suitable for application-specific integrated circuits [Conventional technology] Advances in LSI technology have led to the development of integrated circuits suitable for various applications.

In particular, microprogram controlled integrated circuits (microprogram controlled LSIs) have the advantage of ease of circuit design and flexibility in responding to functional changes and additions. This microprogram-controlled integrated circuit may have a control memory (C8) that stores the microprogram externally, or it may be built into the integrated circuit, but it is generally built in from the standpoint of processing speed and number of pins. Furthermore, in order to flexibly respond to changes and additions of functions, it is usually configured with a writable RAM.

An example of the conventional configuration of this type of microphone program control LSI is shown in FIG. 3. In FIG.
At startup, such as when the power is turned on, a microprogram is loaded into the WC 833 from an external memory or the like via the data switching circuit 34. At this time, the load address of WCS33 is
From the load address generation circuit 3G to the address switching circuit 32
given through. This load address generation time ``j6
36 is initialized prior to loading by a control signal from a general-purpose microprocessor or the like, and is incremented every time one microinstruction is written to the WC833. During normal operation, the next microinstruction address from the sequencer 31 that controls the execution order of microprograms is given to the WC833 via the address switching circuit 32.
The micro-instruction read from the micro-instruction register 35 is transferred to the micro-instruction register 35 via the data switching circuit 34, and as soon as the micro-instruction is executed, the next address control field of the micro-instruction being executed in the micro-instruction register 25 is stored. is taken into the sequencer 31, and the sequencer 31 generates the next microinstruction address.

(ii!!) In the conventional technology, the microprogram is simply loaded from an external memory to the WC8 at startup, such as when the power is turned on. Microprogram controlled LS with built-in WC8 cannot be executed without deterioration.
In I, the built-in WC8 capacity was limited due to chip area constraints, which hindered the realization of complex processing functions.

The object of the invention is to provide a microprogram controlled integrated circuit with a WC8 of limited capacity.

To be able to execute a microprogram with a capacity of WC8 or more without reducing processing speed.

The object of the present invention is to provide a microprogram loading method that enables complex processing with this type of microprogram controlled LSI.

[Means to solve the problem]

In order to achieve the above object, the present invention comprises a control memory that stores microprograms as a writable memory consisting of multiple banks that can be accessed independently, and that while a microprogram stored in one bank is being executed, other It is characterized by loading a microprogram into a bank.

[For production]

A microprogram of approximately 1200 steps is required to realize a certain processing function, and a dedicated LSI is required for that purpose.
It is assumed that the device can only have a built-in memory of 5J, or 2 steps (microphone colloquial language) at most. In this case, the configuration is 2 banks of WC8 each with 256 steps, and the microprogram is 256 steps each.
Multiple independent steps within 6 steps. For example, 240, 200, 230, 2], 0
, 150, 170), by repeating the operation of loading a microprogram module into another bank while a microprogram module in one bank is being executed, the processing speed can be increased by executing microprograms that exceed the WaS capacity. This can be achieved without any deterioration. In the case of the above example, there is a constraint to an independent sequential execution module within 256 steps, but in a microprogram, even if the function requires a large capacity as a whole, the individual processing steps to realize it may not be that large. There is no problem, so it is not a problem.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. In this embodiment, there are two writable control memories (WCS) 13 that store microprograms, each of which can be accessed independently.
Punk WC8], ..., WC82. Micro instructions! Nogistor 15 holds the microinstruction being executed. Sequencer 11 is microinstruction register 1
WC8I- or WC52, which holds the next microinstruction to be executed by inputting the next address control field of the microinstruction in 5 or a signal from the calculation unit (not shown).
Outputs the read address. The load address generation circuit 16 generates a write address for the wcsi or WC82 when loading a microprogram from an external memory. The WCS selection circuit 12.14 selects the WC8I or WC that holds the microprogram being executed.
82 and the same W that loads the microprogram from the outside.
This circuit inputs and outputs addresses and microinstructions by selecting C8I or WO82. WCS selection control circuit 17
is based on the address information from the sequencer 11.
This is a circuit that controls the C8 selection circuits 12 and 14. In addition,
From the perspective of the sequencer 11, that is, the microprogram,
WO81 and WO82 are placed in the same consecutive address space, and using the most significant bit of this address, WC8I,
Suppose that selection 2 is made. The WCS identification signal indicates the WO2 currently being executed.

Figure 2 shows an example of the overall system configuration.
SI21. General-purpose microprocessor 2 that controls the entire system
2. Memory 23 that holds programs and data of the microprocessor 22, WC from the LSI 21 for specific applications
an interrupt generating section 24 that generates an interrupt request signal to the microprocessor 22 from the .8 identification signal; and data bus 25
゜It consists of an address bus 26. The microprogram loaded into the LSI 21 is held in the memory 23 as data of the microprocessor 22, and the 1-interrupt generation unit 24 is loaded into the WC8I or WO52 of the LSI 21 as appropriate under the control of the microprocessor 22.
An interrupt request signal indicating switching of WO2 is generated from the WCSg separate signal from the SI 21, and in response to this interrupt request, the microprocessor 22 reads a necessary microprogram from the memory 23 and transfers it to the LSI 21.

Next, the operation shown in FIG. 1 will be explained. Here, microprograms are loaded into pi, p2, P3, etc. based on the capacity that can be loaded into WO2 per bank and the execution order. P4. P5
．． The specific processing functions required are PL, P2, P3. P4. P5. It is assumed that this is realized by repeatedly executing the microprogram in the order of P6.

First, under the control of the general-purpose microprocessor 22, W
WC5I of the control memory 13 by the CS selection control circuit 17
was designated as Road WC8.

Load address generation circuit 16 is initialized. after that,
21 portions of the microprogram are read from memory 23 by general-purpose microprocessor 22 and written to wcsi via WCS selection circuit 14. wcsi at this time
The address is given from the load address generation circuit 16 via the WC8 selection circuit 12, and is automatically incremented every time one microinstruction is written. A write signal to the WO 51 is given in synchronization with the transfer of load data.

When the microprogram 5421 part is loaded into the WC5I, the general-purpose microprocessor 22 reads and writes it.
Based on the sequencer 11, execution of part 21 of the microprogram loaded into the W(:Sl) is started. On the other hand, the WCS selection control circuit 17 selects WO82 as the next load WC8 based on the address information from the sequencer 11. As a result, the 22 portions of the microprogram to be read next from the memory 23 are loaded into the WO 82 of the control memory 13.

As the microprogram progresses and moves to part 22,
WC8I is loaded WCS by WC8 selection control circuit 17
Then, WO82 is selected as the execution WCS, and the interrupt generation unit 24 is notified of the switching of WO2 by the WC8 identification signal.The interrupt generation unit 24 generates an interrupt request signal indicating the switching of WO2. In response, the microprocessor 22 initializes the load address generation circuit 16 to the beginning of the WC5I, reads 23 portions of the microprogram from the memory 23, and loads them into the WC5I.

Similarly, the 24th part of the microprogram is written in WO52.
Then, the 25th part is loaded into the WC5I and the 26th part is loaded into the WO52 in parallel with execution.

〔Effect of the invention〕

As explained above, according to the present invention, in a microprogram-controlled LSI for specific applications, a microprogram larger than the capacity of the writable control memory built into the chip can be executed without reducing the processing speed. becomes possible. Therefore, it is possible to realize high-performance processing of complex processing that requires a fairly large microprogram.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the microprogram loading method of the present invention, FIG. 2 is a diagram showing an example of a system using the microprogram control LSI configured in FIG. 1, and FIG.
The figure is a diagram illustrating a conventional microprogram loading method. DESCRIPTION OF SYMBOLS 11... Sequencer, 12, 14... WCS selection circuit, 13... Control memory, ]-5... Micro instruction register, 16... Load address generation circuit, 17... WCS selection control circuit. Figure 3

Claims (1)

[Claims] (1) In a microprogram-controlled data processing device, the control memory that stores the microprogram is composed of a writable memory consisting of multiple banks that can be accessed independently, and while a microprogram stored in one bank is being executed, other A microprogram loading method characterized by loading a microprogram into a bank.