JPH02205032A - Gaas semiconductor device - Google Patents

Gaas semiconductor device

Info

Publication number
JPH02205032A
JPH02205032A JP1026018A JP2601889A JPH02205032A JP H02205032 A JPH02205032 A JP H02205032A JP 1026018 A JP1026018 A JP 1026018A JP 2601889 A JP2601889 A JP 2601889A JP H02205032 A JPH02205032 A JP H02205032A
Authority
JP
Japan
Prior art keywords
bonding pad
metal layer
pad
insulating film
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1026018A
Other languages
Japanese (ja)
Inventor
Kanichiro Ikeda
池田　乾一郎
Takuji Sonoda
琢二 園田
Iwao Hayase
早瀬　巌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1026018A priority Critical patent/JPH02205032A/en
Publication of JPH02205032A publication Critical patent/JPH02205032A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To enhance the adhering strength of a GaAs to an electrode by forming the part of a bonding pad of an insulating film having the same thickness as that of the pad, forming a metal layer on both the metal of the pad and the insulating film on the pad, and forming a metal layer for the pad on the metal layer. CONSTITUTION:After a recess 6 is formed by etching, the gate electrode 3 of a channel is formed at a predetermined position by a lifting OFF method. In this case, the part of a bonding pad is simultaneously formed. Then, a remaining bonding pad is formed of an insulating film 8. In this instance, the metal of the pad and the film 8 are so formed in the same thickness that the pad becomes flat. Thereafter, a metal layer 9 of Cr, Pt, Ti, etc., is formed on the pad, i.e., over the metal of the pad and the film 8, and a metal layer 7 for the pad is laminated on the layer 9.

Description

【発明の詳細な説明】 〔産業上の利用分針〕 この発明は、Ｇ　ａ　Ａ　□ｓ　Ｆ　Ｅ　Ｔ　（Ｆｉｅ
ｌｄ　ＥｆｆｅｃｔＴｒａｎｓｉ・ｓ’　ｔ　ｏ　ｒ　
：電界効果トランジスタ）素子における電極の付着力を
向上せしめた半導体装置に関するものである。[Detailed description of the invention] [Minute hand for industrial use]
ld EffectTransi・s' tor
The present invention relates to a semiconductor device in which the adhesion of electrodes in a field effect transistor (field effect transistor) element is improved.

〔従来の技術〕[Conventional technology]

第３図は従来のＧａＡｓ半導体装置の平面図であり、第
４図（ａＬ　（ｂ）は、第３図のＣ−Ｃ’線およびＤ−
Ｄ’・線による断面図である。FIG. 3 is a plan view of a conventional GaAs semiconductor device, and FIG. 4 (aL (b) shows lines CC' and D-
It is a sectional view taken along the line D'.

第３図、第４図において、１は半絶縁性ＧａＡｓ基板、
２はこの半絶縁性ＧａＡｓ基板１上に形成された活性層
、３および４はこの活性層２上に形成されたソース電極
およびドレイン電極、６は前記活性層２にエツチングに
て形成したリセス、５は乙のリセス６内にリフトオフ法
にて形成したゲート電極、５Ａはゲートフィンガー部、
７はソース、ドレイン、ゲート各電極３，４．５のボン
ディングパッド部に、Ｔｉ（チタン）、Ｍｏ（モリブデ
ン）、Ａｕ（金）等の金属でリフトオフ法にて形成され
たボンディングパッド用金属層である。In FIGS. 3 and 4, 1 is a semi-insulating GaAs substrate;
2 is an active layer formed on this semi-insulating GaAs substrate 1; 3 and 4 are source and drain electrodes formed on this active layer 2; 6 is a recess formed in the active layer 2 by etching; 5 is a gate electrode formed in the recess 6 of B by the lift-off method, 5A is a gate finger part,
Reference numeral 7 denotes a metal layer for bonding pads formed by a lift-off method using metals such as Ti (titanium), Mo (molybdenum), and Au (gold) on the bonding pad portions of the source, drain, and gate electrodes 3 and 4.5. It is.

このように構成されたＧａＡｓＦＥＴは、チップ分割さ
れ、グイボンド、およびワイヤボンドが施される。The GaAsFET configured in this manner is divided into chips, and subjected to wire bonding and wire bonding.

上記のように構成された従来のＧａＡｓＦＥＴ素子は、
ボンディングパッド部に、金線を用いてワイヤボンドを
行う場合、素子とワイヤ間の強度を上げるため、高温で
の作業、超音波の使用等の厳しい条件となり、このとき
素子のボンディングパッド部には、矢きなストレスがが
がる。したがって、ソース、ドレイン、ゲートの各電極
３，４゜５のボンディングパッド部の高い付着強度が要
求される。しかし、ＧａＡｓと合金化されて付着強度の
高いオーミック接合のソース、ドレイン電極３．４に比
べ、ショク１−キー接合のゲート電極５の付着力が弱い
ため、ボンディングパッド部の剥離が発生する。また、
ボンディングパッド部にストレスを与えない低温や超音
波を使用しないワイヤーボンド条件では、ボンディング
パッド部の剥離は低減できるが、ボンディングパッド部
とワイヤの強度が低下する。The conventional GaAsFET device configured as described above is
When wire bonding is performed using gold wire on the bonding pad, harsh conditions such as working at high temperatures and using ultrasonic waves are required to increase the strength between the element and the wire. , it relieves a lot of stress. Therefore, high adhesion strength is required for the bonding pad portions of the source, drain, and gate electrodes 3 and 4.5. However, since the adhesive force of the gate electrode 5 of the square-key junction is weaker than that of the source and drain electrodes 3.4 of the ohmic junction which are alloyed with GaAs and have a high adhesive strength, peeling of the bonding pad portion occurs. Also,
Under low temperature conditions that do not apply stress to the bonding pad section or wire bonding conditions that do not use ultrasonic waves, peeling of the bonding pad section can be reduced, but the strength of the bonding pad section and the wire is reduced.

このため、ボンディングパッド部の密着性を上げるため
、ｐｔ（白金）、Ｃｒ（クロム）を用いると、ショット
キ特性、リフトオフ特性が劣化し、また、ボンディング
パッド部をソース、ドレイン電極３，４と同様にオーミ
ック接合を用いると半絶縁性Ｇ　ａＡｓ基板１のリーク
電流をひろってしまう等の問題点があった。For this reason, if pt (platinum) or Cr (chromium) is used to improve the adhesion of the bonding pad, the Schottky characteristics and lift-off characteristics will deteriorate, and the bonding pad may be formed in the same manner as the source and drain electrodes 3 and 4. If an ohmic junction is used for this purpose, there are problems such as leakage current from the semi-insulating GaAs substrate 1 being increased.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

この発明は、上記の問題点を解消するためになされたも
ので、ＧａＡｓＦＥＴ素子のワイヤーボンドの条件２強
度を変えず、かつウニへプ四セスの工程も大きく変更す
ることなしに、ＧａＡｓＦＥＴ素子のＧ　ａ　Ａ　ｓと
電極の付着強度を高くしたＧａＡｓ半導体装置を得るこ
とを目的とする。This invention was made in order to solve the above-mentioned problems, and it is possible to form a GaAsFET device without changing the strength of the wire bond of the GaAsFET device and without significantly changing the unihep four process. The object of the present invention is to obtain a GaAs semiconductor device in which the adhesion strength between GaAs and an electrode is increased.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係るＧａＡｓ半導体装置は、ボンディングパ
ッド部の一部をこのボンディングパッド部と同じ厚さで
の絶縁膜モ形成し、ボンディングパッド部上にボンディ
ングパッド部の金属と絶縁膜の両者にまたがって金属層
を形成し、金属層上にボンディングパッド用金属層を形
成したものである。In the GaAs semiconductor device according to the present invention, an insulating film is formed on a part of the bonding pad part to have the same thickness as the bonding pad part, and an insulating film is formed on the bonding pad part, spanning both the metal and the insulating film of the bonding pad part. A metal layer is formed, and a bonding pad metal layer is formed on the metal layer.

〔作用〕[Effect]

この発明においては、ゲート電極のボンデイングパッド
部の一部分を絶縁膜で形成し、金属と絶縁膜とで形成さ
れているボンディングパッド部上に金属層を設け、この
金属層上にボンディングパッド用金属層を積層した乙と
から、ＧａＡｓとの付着力強化は絶縁膜が果し、絶縁膜
とボンディングパッド部上の金属層も付着力を高め、ゲ
ート電極の付着強度が高くなる。In this invention, a part of the bonding pad part of the gate electrode is formed of an insulating film, a metal layer is provided on the bonding pad part formed of metal and an insulating film, and a metal layer for bonding pad is formed on this metal layer. The insulating film strengthens the adhesion with GaAs, and the metal layer on the insulating film and the bonding pad also increases the adhesion, increasing the adhesion strength of the gate electrode.

〔実施例〕〔Example〕

以下、この発明の一実施例を図面について説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第１図はこの発明の一実施例を示す図で、例えばＧａＡ
ｓＦＥＴ素子に適用した場合の素□子の平面図であり、
第２図（ａ）Ｐ（ｂ）は、第１図のＧａＡｓＦＥＴ素子
のＡ−Ａ’線、Ｂ−Ｂ’ｌｌによる断面図である。これ
らの図において、第３図。FIG. 1 is a diagram showing an embodiment of the present invention, for example, GaA
It is a plan view of an element when applied to an sFET element,
2(a) and 2(b) are cross-sectional views taken along line AA' and line BB'll of the GaAsFET element in FIG. 1. In these figures, FIG.

第４図と同一符号は同一構成部分を示し、８は前記ゲー
ト電極５のボンディングパラ・ド部の一部分にこのボン
ディングパッド部を構成する金属に変えて形成した絶縁
膜で、その厚みはボンディングパッド部の厚みと同程度
に形成される。９ば前記金属と絶縁膜８とで形成された
ボンディングパッド部上に形成された金属層で、この上
にポジディングパッド用金属層７が形成゛される。The same reference numerals as in FIG. 4 indicate the same constituent parts, and 8 is an insulating film formed on a part of the bonding pad part of the gate electrode 5 instead of the metal constituting the bonding pad part, and its thickness is the same as that of the bonding pad part. The thickness is approximately the same as that of the other parts. 9 is a metal layer formed on the bonding pad portion formed of the metal and the insulating film 8, on which a positive pad metal layer 7 is formed.

次に乙のＧａＡｓ半導体半導体装造方法゛に□ついて説
明する。Next, the GaAs semiconductor device manufacturing method (□) will be explained.

半絶縁性ＧａＡｓ基板１上に活性層２を形成し、この活
性層２上の所定位置にソー′ス電極３ンドレ□イン電極
４をリフ小オフ法にて形成する。□次にリセス６をエツ
チングにて形成した後、チャネル部のゲート電極（ゲー
トフィンガー部５Ａ）５’を所定の位置にリフトオフ法
を用いて形成する。チャ′ネル部のゲート電極５はＧ　
ａ”Ａ、ｓ　Ｆ”Ｅ　Ｔ素子の特性上重要であ□るシ宴
ツトキ・−特性が優れでお□す、しかも約０．５μｍの
ゲー゛１・長・を容易に・□形成できるリフトオフ特性
が優れているＡ　Ｉ　、　”Ｔ　ｉ’、等を・用いる。An active layer 2 is formed on a semi-insulating GaAs substrate 1, and a source electrode 3 and a drain □in electrode 4 are formed at predetermined positions on the active layer 2 by a riff small-off method. □Next, after forming the recess 6 by etching, the gate electrode (gate finger part 5A) 5' of the channel part is formed at a predetermined position using a lift-off method. The gate electrode 5 in the channel part is G
a"A, s F"ET It has excellent performance characteristics, which are important for the characteristics of T elements, and can easily form a gate length of approximately 0.5 μm. A I, "T i', etc. which have excellent lift-off characteristics are used.

このゲート電極５のチャ□ネル部分は□、ワ″イヤボン
ディングのとき強いストレスがかからないため、ＧａＡ
ｓとの密着性より素子の特性壱重視した前記のような材
料を用いる。また、この時ボンディングパッド部の一部
も同時に形成してお（。The channel portion of the gate electrode 5 is not exposed to strong stress during wire bonding, so it is made of GaA.
The above-mentioned material is used in which the characteristics of the element are more important than the adhesion with the material. Also, at this time, a part of the bonding pad part is also formed at the same time.

次に残りのボンディングパッド部を絶縁膜８にて形成す
る。この時、ボンディングパッド部が平坦になるように
ボンディングパッド部の金属と絶縁膜８の厚みを等しく
する。次にボンディングパッド部上に、すなわちボンデ
ィングパッド部の金属と絶縁膜８にまたがってＣｒ、Ｐ
ｔ、Ｔｉ等の金属層９を形成し、この金属層９上にボン
ディングパッド用金属層７が積層される。Next, the remaining bonding pad portions are formed with an insulating film 8. At this time, the thickness of the metal of the bonding pad portion and the thickness of the insulating film 8 are made equal so that the bonding pad portion is flat. Next, on the bonding pad part, that is, over the metal of the bonding pad part and the insulating film 8,
A metal layer 9 of T, Ti, etc. is formed, and a bonding pad metal layer 7 is laminated on this metal layer 9.

このように形成されたゲート電極５のボンディングパッ
ド部では、ＧａＡｓとの付着力がやや弱いゲート電極金
属はボンディングパッド部の一部を構成し、他の部分を
より付着力のある絶縁膜８で形成するようにしたので、
ＧａＡｓがらの剥離が防止できる。また、ボンディング
パッド部に積層されたＣｒ、Ｐｔ、Ｔｉ等の金属層９は
下地となる金属および絶縁膜８との付着力において問題
なく、かつ素子性能を低下させることもない。そして、
金属層９とボンディングパッド用金属層７との間でも付
着力に問題がなくなることがら、ボンディングパッド部
の強度の高い優れた特性を有するＧ　ａ　Ａ　ｓ　Ｆ　
Ｅ　Ｔが得られる。In the bonding pad portion of the gate electrode 5 formed in this manner, the gate electrode metal, which has a somewhat weak adhesion to GaAs, constitutes a part of the bonding pad portion, and the other portion is covered with the insulating film 8, which has a stronger adhesion. I made it to form,
Peeling of GaAs particles can be prevented. Further, the metal layer 9 of Cr, Pt, Ti, etc. laminated on the bonding pad portion has no problem in adhesion with the underlying metal and the insulating film 8, and does not deteriorate device performance. and,
Since there is no problem with adhesion between the metal layer 9 and the bonding pad metal layer 7, GaAsF has excellent properties such as high strength in the bonding pad portion.
ET is obtained.

〔発明の効果〕〔Effect of the invention〕

以上説明したようにこの発明は、ボンディングパッド部
の一部をこのボンディングパッド部と同じ厚さでの絶縁
膜で形成し、ボンディングパッド部上にボンディングパ
ッド部の金属と絶縁膜の両者にまたがって金属層を形成
し、金属層上にボンディングパッド用金属層を形成した
ので、ＧａＡｓとの付着力が高くなり、また、ボンディ
ングパッド部下層に位置する金属および絶縁膜とその上
の金属層とで付着力が高まり、ボンディングパッド用金
属層との付着力に関しても問題がなくなる。その上、チ
ャネル部に形成されているゲート電極により得られる優
れたシンットキー特性等の素子性能は劣化させることが
ないので、ボンディングパッド強度の高い、優れた特性
を有するＧａＡｓＦＥＴが得られる。As explained above, in the present invention, a part of the bonding pad part is formed with an insulating film having the same thickness as the bonding pad part, and a part of the bonding pad part is formed with an insulating film that spans both the metal and the insulating film of the bonding pad part. Since a metal layer is formed and a metal layer for a bonding pad is formed on the metal layer, the adhesion force with GaAs is high, and the bonding force between the metal and insulating film located below the bonding pad and the metal layer above it increases. The adhesive strength is increased, and there is no problem with the adhesive strength with the bonding pad metal layer. Moreover, since the device performance such as the excellent synt-key characteristic obtained by the gate electrode formed in the channel portion is not deteriorated, a GaAsFET with high bonding pad strength and excellent characteristics can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの発明の一実施例を示すＧａＡｓ半導体装置
の平面図、第２図（ａ）、（ｂ）は、第１図のＡ−Ａ’
線およびＢ−Ｂ’線による断面図、第３図は従来のＧａ
Ａｓ半導体装置の平面図、第４図（ａ）？（ｂ）は、第
３図のｃ−ｃ’線およびＤ−Ｄ’線による断面図である
。 図において、１は半絶縁性ＧａＡｓ基板、２は活性Ｈ１
３はソース電極、４はドレイン電極、５はゲート電極、
７はボンディングパッド用金属層、８は絶縁膜、９は金
属層である。 なお、各図中の同一符号は同一または相当部分を示す。 代理人　大　岩　増　雄　　　（外２名）３、補正をす
る者 事件との関係 手 続 補FIG. 1 is a plan view of a GaAs semiconductor device showing an embodiment of the present invention, and FIGS. 2(a) and (b) are AA' in FIG.
3 is a cross-sectional view taken along the line and the line BB'.
Plan view of As semiconductor device, FIG. 4(a)? (b) is a sectional view taken along line cc' and line DD' in FIG. 3. In the figure, 1 is a semi-insulating GaAs substrate, 2 is an active H1
3 is a source electrode, 4 is a drain electrode, 5 is a gate electrode,
7 is a metal layer for bonding pads, 8 is an insulating film, and 9 is a metal layer. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) 3. Supplementary procedures related to the amendment case

Claims (1)

【特許請求の範囲】[Claims] 半絶縁性ＧａＡｓ基板上に形成された活性層上に配置さ
れたゲートフィンガー部と、前記活性層外の所定の位置
に配置されたボンディングパッド部とを有するゲート電
極を備えた半導体装置において、前記ボンディングパッ
ド部の一部をこのボンディングパッド部と同じ厚さでの
絶縁膜で形成し、前記ボンディングパッド部上に前記ボ
ンディングパッド部の金属と絶縁膜の両者にまたがって
金属層を形成し、前記金属層上にボンディングパッド用
金属層を形成したことを特徴とするＧａＡｓ半導体装置
。A semiconductor device comprising a gate electrode having a gate finger portion disposed on an active layer formed on a semi-insulating GaAs substrate and a bonding pad portion disposed at a predetermined position outside the active layer. A part of the bonding pad section is formed of an insulating film having the same thickness as the bonding pad section, a metal layer is formed on the bonding pad section spanning both the metal of the bonding pad section and the insulating film, and the A GaAs semiconductor device characterized in that a metal layer for bonding pads is formed on a metal layer.
JP1026018A 1989-02-02 1989-02-02 Gaas semiconductor device Pending JPH02205032A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1026018A JPH02205032A (en) 1989-02-02 1989-02-02 Gaas semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1026018A JPH02205032A (en) 1989-02-02 1989-02-02 Gaas semiconductor device

Publications (1)

Publication Number Publication Date
JPH02205032A true JPH02205032A (en) 1990-08-14

Family

ID=12181959

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1026018A Pending JPH02205032A (en) 1989-02-02 1989-02-02 Gaas semiconductor device

Country Status (1)

Country Link
JP (1) JPH02205032A (en)

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