JPH02186748A - Communication loop back test circuit - Google Patents

Communication loop back test circuit

Info

Publication number
JPH02186748A
JPH02186748A JP1004822A JP482289A JPH02186748A JP H02186748 A JPH02186748 A JP H02186748A JP 1004822 A JP1004822 A JP 1004822A JP 482289 A JP482289 A JP 482289A JP H02186748 A JPH02186748 A JP H02186748A
Authority
JP
Japan
Prior art keywords
line
test
control device
channel control
loop back
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1004822A
Other languages
Japanese (ja)
Inventor
Eiji Takano
高野 栄治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Ibaraki Ltd
Original Assignee
NEC Ibaraki Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Ibaraki Ltd filed Critical NEC Ibaraki Ltd
Priority to JP1004822A priority Critical patent/JPH02186748A/en
Publication of JPH02186748A publication Critical patent/JPH02186748A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent malfunction at the time of a test and to easily conduct a loop back test by putting a delay line between the connection of a transmission line and a reception line at the time of the communication loop back test by means of a loop back test device. CONSTITUTION:When a channel controller 10 transmits transmission data 70 to a device controller 20 through a transmission line 50 in a normal action, the controller 20 returns a response with respect to data 70 to the controller 10 through a reception line 60. At that time, the delay line 40 is detached. When a test signal 90 is inputted at the time of the communication loop back test, a selector operates and the line 50 and the line 60 on a common interface are shortly connected, whereby the delay line 40 is interposed between both lines 50 and 60. When the test is conducted in such a way, loop back data is given delay and it returns to a channel control circuit 100. Consequently, malfunction hardly occurs.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、チャネル制御′?装置とデバイス制御装置間
の通信折返し試験回路に関し、特に折返したデータにデ
ィレィを持たせる機能を有する通信折返し試験回路に関
する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to channel control'? The present invention relates to a communication return test circuit between a device and a device control device, and particularly to a communication return test circuit having a function of giving a delay to returned data.

[従来の技術] 一般に、チャネル制g9装置とデバイス制御装置との間
は、設置箇所が離れており、両者を接続しかつ通信を行
なわせる共通インターフェイスの距離が長くなる。この
ため、チャネル制u4装a及びデバイス制御装置は、そ
れぞれディレィタイムを考慮した装置設計、即ちデータ
の送受信の間に一定時間のディレィタイムがあることを
前提にした設計を施されている。
[Prior Art] Generally, a channel control G9 device and a device control device are installed at a distance, and the distance of a common interface that connects the two and allows them to communicate becomes long. For this reason, the channel system U4 device a and the device control device are each designed in consideration of delay time, that is, designed on the premise that there is a certain delay time between data transmission and reception.

通信折返し試験時には、チャネル制御装置の送受信ライ
ン間を短絡的に接続して送出データを受信ラインに送る
ようにするが、短いケーブル、例えばl O〜20 m
 m 、最大100mmの長さのケーブルで接続しただ
けでは、要求される遅延時間を満たすことはできないの
で誤動作を起こす。
During a communication return test, the transmitting and receiving lines of the channel control device are connected in a short circuit to send outgoing data to the receiving line, but a short cable, e.g.
If only a cable with a maximum length of 100 mm is used, the required delay time cannot be met, resulting in malfunction.

このため 従来は通信折返し試験時には、上述の誤動作
を防ぐため前述の一定時間のディレィを満たす長い折返
しケーブルで送受信ライン間を接続していた。
For this reason, conventionally, during communication loopback tests, in order to prevent the above-mentioned malfunctions, a long loopback cable that satisfies the above-mentioned fixed time delay was used to connect the transmitting and receiving lines.

[解決すべき課題] 上述したように従来の通信折返し試験では、チャネル制
御装置とデバイス制御装置のデータのディレィに相当す
る長いケーブルを用意しなければならないという問題が
あった。
[Problems to be Solved] As mentioned above, in the conventional communication loopback test, there was a problem in that a long cable corresponding to the data delay between the channel control device and the device control device had to be prepared.

本発明は上述した問題点にかんがみなされたもので、通
信折返し試験時に長いケーブルを必要とせずに済み、か
つ通常の通信時にはバイパス可能な通信折返し回路の提
供を目的とする。
The present invention has been made in view of the above-mentioned problems, and aims to provide a communication return circuit that does not require a long cable during a communication return test and can be bypassed during normal communication.

[課題の解決手段] 上記目的を達成するために本発明は、チャネル制御装置
のデータ送受信ライン間に接離自在に介在し1通信折返
し試験時に前記チャネル制御回路より前記デバイス制御
装置へ送出される送信データにディレィを与えてを前記
チャネル制御回路の受信ラインに接続する通信折返し試
験回路であって、通常動作中は前記チャネル制御回路と
前記デバイス制御装置を共通インターフェイスで接続し
、折返し試験時は前記チャネル制御装置内で前記デバイ
ス制御装置への送信データをディレィラインを介して自
己チャネル制御装置の受信ラインに接続して受Qデータ
とする構成としである。
[Means for Solving the Problems] In order to achieve the above object, the present invention provides a data transmitting/receiving line of a channel control device that is interposed between the data transmission and reception lines so as to be freely accessible and separable, and that data is sent from the channel control circuit to the device control device during one communication return test. A communication loopback test circuit that delays transmission data and connects it to the reception line of the channel control circuit, wherein the channel control circuit and the device control device are connected through a common interface during normal operation, and during loopback testing. In the channel control device, data to be transmitted to the device control device is connected to a reception line of the own channel control device via a delay line to receive Q data.

[実施例1 以下、本発明の一実施例について図面を参照して説明す
る。
[Embodiment 1] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.

図において、10はチャネル制御装置、20はデバイス
制御装置であり1両者の間は共通インターフェイスとな
る送信ライン50、受信ライン60等で接続されている
。また図中100はチャネル制御回路である。
In the figure, 10 is a channel control device, 20 is a device control device, and the two are connected by a transmission line 50, a reception line 60, etc., which serve as a common interface. Further, 100 in the figure is a channel control circuit.

折返し試験装置30は、チャネル制御装置10内に位置
し、試験信号90により送信ライン50と受信ライン6
0を装置内部で短絡的に接続可能にするセレクタ(図示
せず)を有すると共に、セレクタにより切替えられて接
続された送信ライン50と受信ライン60の間に介在す
るディレィライン40を備える。ディレィライン40に
よる遅延時間は、チャネル制御装置lOとデバイス制御
装置20との間で予め規定されているディレィが生じる
ような時間とする。
The loopback test device 30 is located within the channel control device 10 and is connected to the transmission line 50 and the reception line 6 using the test signal 90.
0 can be connected in a short-circuit manner inside the device, and also has a delay line 40 interposed between the transmission line 50 and the reception line 60 which are switched and connected by the selector. The delay time caused by the delay line 40 is set to a time such that a predefined delay occurs between the channel control device IO and the device control device 20.

次に、本実施例の動作を説明する。Next, the operation of this embodiment will be explained.

通常動作では、チャネル制御装置10が送信データ70
を送信ライン50を介してデバイス制御装置20に送出
すると、デバイス制御装置20は送信データ70に対す
る応答を受信ライン60を介してチャネル制御装置10
に返す、このとき、ディレィライン40は切離されてい
る。
In normal operation, the channel control device 10 transmits data 70
When the data is sent to the device control device 20 via the transmission line 50, the device control device 20 sends a response to the transmission data 70 to the channel control device 10 via the reception line 60.
At this time, the delay line 40 is disconnected.

通信折返し試験時に試験信号90が入力されると、セレ
クタが作動して共通インターフェイス上の送信ライン5
0と受信ライン60とが短絡的に接続され、両ライン5
0.60の間にディレィライン40が介在する。このよ
うにして試験を行なうと、折返しのデータはディレィを
与えられてチャネル制御回路100に戻るので誤動作を
起こすことがない。
When the test signal 90 is input during the communication return test, the selector is activated and the transmission line 5 on the common interface is
0 and the receiving line 60 are connected in a short circuit, and both lines 5
A delay line 40 is interposed between 0.60 and 0.60. If the test is performed in this manner, the return data is returned to the channel control circuit 100 with a delay, so that no malfunction occurs.

[発明の効果] 以上説明したように本発明は、折返し試験装置による通
信折返し試験時、送信ラインと受信ラインの接続間にデ
ィレィラインを入れることにより試験時の誤動作を防止
できる。また、長いケーブルを用意する必要がなくなり
、容易に折返し試験を行なえるようになるという効果が
ある。
[Effects of the Invention] As described above, the present invention can prevent malfunctions during a communication return test using a return test device by inserting a delay line between the connection of the transmission line and the reception line. Further, there is an effect that there is no need to prepare a long cable, and it becomes possible to perform a folding test easily.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例のブロック図である。 lO:チャネル制御装置 20:デバイス制御装置 30:折返し試験装置 40:ディレィライン 50:送信ライン 60:受信ライン 70:送信データ 80:受信データ 90:試験信金 100:チャネル制御回路 FIG. 1 is a block diagram of one embodiment of the present invention. lO: Channel control device 20: Device control device 30: Folding test device 40: Delay line 50: Transmission line 60: Reception line 70: Transmission data 80: Received data 90: Exam Shinkin Bank 100: Channel control circuit

Claims (1)

【特許請求の範囲】[Claims] チャネル制御装置のデータ送受信ライン間に接離自在に
介在し、通信折返し試験時に前記チャネル制御回路より
前記デバイス制御装置へ送出される送信データにディレ
イを与えて前記チャネル制御回路の受信ラインに接続す
る通信折返し試験回路であって、通常動作中は前記チャ
ネル制御回路と前記デバイス制御装置を共通インターフ
ェイスで接続し、折返し試験時は前記チャネル制御装置
内で前記デバイス制御装置への送信データをディレイラ
インを介して自己チャネル制御装置の受信ラインに接続
して受信データとすることを特徴とした通信折返し試験
回路。
Intervening between the data transmission and reception lines of the channel control device so as to be freely accessible and detachable, and connecting to the reception line of the channel control circuit by giving a delay to the transmission data sent from the channel control circuit to the device control device during a communication return test. The communication loopback test circuit connects the channel control circuit and the device control device through a common interface during normal operation, and transmits data to be transmitted to the device control device within the channel control device through a delay line during the loopback test. A communication loopback test circuit characterized in that the circuit is connected to a reception line of a self-channel control device via a communication line to receive data.
JP1004822A 1989-01-13 1989-01-13 Communication loop back test circuit Pending JPH02186748A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1004822A JPH02186748A (en) 1989-01-13 1989-01-13 Communication loop back test circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1004822A JPH02186748A (en) 1989-01-13 1989-01-13 Communication loop back test circuit

Publications (1)

Publication Number Publication Date
JPH02186748A true JPH02186748A (en) 1990-07-23

Family

ID=11594402

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1004822A Pending JPH02186748A (en) 1989-01-13 1989-01-13 Communication loop back test circuit

Country Status (1)

Country Link
JP (1) JPH02186748A (en)

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