JPH02159659A - Bus control system - Google Patents

Abstract

PURPOSE:To omit the transfer of a status in the case when the operation is a write operation to a register of a slave unit, to end the processing by a response, and to execute the bus release in an early stage by providing a status circuit for generating and discriminating the status on the unit. CONSTITUTION:This system is constituted so that a response line 200-3 is provided in a line 200, and a bus arbiter 300 and a unit 100-2 of a slave side monitor an error state, etc., of data which is being transferred so that the contents of a fault can be informed together with a fault notice to a unit 100-1 at the time of the fault, and a data transfer in which the fault is generated can be suspended. Also, a status circuit 13 is provided on the units 100-1, 2, and when a write operation to registers of the units 100-1, 2 is executed, it is omitted to send back the status. In such a way, at the time of a write operation to the register in the slave unit 100-2, the status transfer is omitted, and the use efficiency of a bus can be improved.

Description

[Detailed description of the invention] 〔overview〕 As multiple units are linked together on a line.

Equipped with a bus arbiter that issues bus usage rights.

The purpose of this invention is to improve bus usage efficiency by omitting status transfer when writing to a register in a slave unit in a second bus control method that performs bus control under a so-called split method.

Create a response line within the above line.

The bus arbiter and slave side units mentioned above.

The present invention is configured to monitor the error state of data being transferred, and when a failure occurs, to notify the unit of the failure as well as the details of the failure, and to cancel the data transfer in which the failure has occurred.

A status circuit is provided in the unit so that when a write operation is performed to the register of the unit, the return of the status is omitted.

C. Industrial Application] The present invention is directed to a bus control system, in particular, a bus control system in which a plurality of units are connected on a line, and a bus arbiter that issues bus usage rights is provided, and bus control is performed under the so-called sprint system. Regarding bus control method.

Regarding data transfer under the sprint method.

When the masked unit issues a command to the slave side, it temporarily releases the line, and when the slave unit completes the specified processing.

The slave side then acts as a mask and transfers the data to the other party. This improves bus usage efficiency.

[Conventional technology]

FIG. 6 shows a hash control system configuration which is the premise of the present invention and is not yet known, and FIG. 7 shows a time chart of a conventional example. In addition.

In the following description, for convenience, the structure shown in FIG. 6 will be considered as a conventional structure.

In FIG. 6, 100-1.100-2. . . . are units, 200 is a line, and 200-1 is a data unit.
bus, 200-2 is bus control (i% bus, 200
-3 represents a response line, and 300 represents a bus arbiter. Furthermore, 1 is a transfer control f11 circuit, 2 is a flip-flop for receiving a bus right issue request, and 3 is a bus right control circuit.

4 is a bus permission reception flip-flop; 5 is a transmission/reception register; 6 is a gate; 7 is a transmission/reception register; 8 is a response control circuit; 9 is a transfer end (bus complete) reception flip-flop; 10 is a bus monitoring circuit; Reference numeral 11 represents a bus use permission reception flip-flop, and reference numeral 12 represents a gate.

Needless to say (, each unit 100-1, 100
-2. . . . have substantially the same configuration and perform the same processing.

Now assume that unit 100-1 requests data transfer from unit 100-2. In this case, as will become clearer with reference to the time chart shown in FIG.
-Q), and the bus right control circuit 3 in the bus arbiter 300 receives the request (BREQ-0),
When granting the right to use the bus, a bus use permission (bus ground master BGRM-0) is returned. The relevant permission (B
GRM-O) turns on the gate 6 and is taken into the transfer control circuit 1. Needless to say, the bus right control circuit 3 issues the above-mentioned permission (BGRMO) after processing conflicts with bus right requests from other units.

In unit l-100-1, transfer control circuit l sends the information prepared on register 5 onto line 200.

Commands and addresses are provided on the data bus 200-1.

Information is sent out in the order of data, and the bus control signal bus 200-2 is sent out for 1τ in synchronization with the sending of commands.
Outputs bus start (BSTT) indicating the start of the sequence. The bus monitoring circuit 10.

After receiving the bus start (BSTT), 1τ later, a bus use permission (bus ground slave BGR 3-1) is sent to the slave unit 100-2, and the gate 12 is turned on. In the command, each unit 100 connected to the 0 line 200 is displayed with the ID (DID) of the unit 100-1 that is currently being masked and the unit 100-2 that is to become the slave.
-3 monitors the contents of bus 200-1 and bus 200-2, in this case unit 100-
2 detects its own ID.

Operates as a slave.

The unit 100-1 serving as a mask issues a transfer end (BCPT) in synchronization with the last transfer data to be transferred. Based on this, the bus arbiter 300 drops the grant (BGRM-0), and after 1 and 1τ, the bus arbiter 300 drops the grant (BGRM-0).
R3-1) and requests from other units (BREQ
) is accepted. During this time, the slave side unit 100-
2 and the bus monitoring circuit 10 monitor errors on the bus. and.

During the transfer from the Unisol l-100-1 to the unit 100-2, a response RC, RA, RD, etc. is sent via the response line 200-3 to determine whether an error or the like has occurred in the transferred data.・Return as . Although FIG. 7 shows a case where no error occurs, for example, if an error occurs during transmission of command C and the error is notified by response RC, the unit 100-1 serving as a mask 3τ
Afterwards, it issues a transfer end (BCPT) and bus arbiter 3
00 immediately drops permission (BGRM-0) and then drops permission (BGR8-1).

[Problem to be solved by the invention]

In the case of the conventional configuration described above, since a split method is adopted, when the unit 100-1 serving as a mask finishes transmitting the information to be transmitted by itself, the occupation of the line 200 is temporarily released. In addition, responses that are sent back sequentially are examined to release the occupation of the line 200 at an early stage. This prevents one line 200 from being occupied by one unit for an undesired long period of time.

However, problems still remain. That is, in the time chart shown in FIG. 7, even if the command transfer is completed normally, the status S will always be notified.
For this reason, the release of the line has to wait until the status S is notified. However, for operations performed using eight lines 200, the unit 100 is treated as a slave.
There are cases where memory within -2 is accessed and cases where registers are accessed. Unit 100 as a mask
During a write operation from 4, the former once receives data in the buffer (register) and returns a response based on the result, then actually writes to the memory, and notifies the result by status transfer. However, in the latter case, after writing the value to the register, there is no need to particularly notify the masked unit 100-1, and the status S is wasted. Access to this register is a frequent operation and 9 lines 20
The impact was large on the usage rate of 0. Note that when reading from the masked unit 100-1, data is transferred together with the status.

No unnecessary bus sequences are used.

An object of the present invention is to improve the bus utilization rate by omitting status transfer during a write operation to a register in a slave unit.

Means for Solving Problem C] FIG. 1 shows a diagram of the principle configuration of the present invention. Code 100 in the diagram
-1.100-2. ... are the respective units, 200 is the line 200-1 is the data bus, 200-2 is the bus control signal bus, and 200-3 is the response line (RLN).
), 3 is a bus right control circuit, 7 is a register [0 is a bus monitoring circuit, 12 is a gate, 13 is a status circuit, 14
15 represents a control circuit, and 15 represents a memory.

The control circuit 14 issues a bus use right issuance request (BREQ) and a transfer end (CMPT), and also sends a command, command, etc. on the two lines 200 after receiving a bus use permission for the mask (hass ground master BGRM). Send out information.

A response line 200-3 is provided in line 200, and bus supervisory circuit 10 performs a bus start (BST)
After receiving T), the slave unit l-
Issues bus use (bus ground slave BGR8) for permission slave to unit 100-2.
Turn on the gate 12 at 00-2 and turn on the unit 100
-2 response line 200-3
Allow it to be sent upwards.

The status circuit 13 prevents the transfer of status S when the operation using one line 200 is a write operation from the masked unit 100-1 to the register 7 of the unit 1'0O-2. .

[Effect]

Upon receiving the request (BREQ) from the control circuit 14, the bus right control circuit 3 issues a permission (BGRM). Upon receiving the permission (BGRM), the control circuit 14 sends information onto the data bus 200-1, and also sends a bus start signal (BSTT) onto the bus control signal bus 200-2. Send out.

As a result, the slave unit 100-2 receives the information on the bus 200-1. Bus monitoring circuit IO
When receiving the bus start (BSTT), it issues permission (BGR) to the slave unit 100-2.
5) to enable unit 100-2 to send a response to unit 100-1.

While receiving the information from the unit 100-1, the unit 100-2 performs an error check on each piece of information received, and sends a response line 200.
-3, the response is sent back.

The unit 100-1 serving as a mask continues to send out information while checking from the above response whether or not each piece of information that it is sending out has been correctly received. When all the information has been sent, a transfer end (CMPT) signal is issued.

While the unit 100-1 is transmitting its own information, if a response reports the occurrence of a failure and the details of the failure, the unit 100-1 issues a transfer end (CMPT) early so to speak.
Configured to release the line.

Unit 100- whose operation is a mask
1 to the register 7 of the unit 100-2 which is a slave, the unit 1002 returns a response and the status circuit 1 of the unit 100-2
3 does not return status S.

If the response is normal, the unit 100-1 (status cycle 113) ends the process at that point. On the other hand, when the operation is a read operation from the register 7 or an access to the memory 15 (write operation and read operation), the status circuit 13 returns the status S. Unit 100-1 (status circuit 13)
If the status S is normal, the process ends.

Note that even though an error occurred while the information from UNISO 100-1 was being transferred, the slave unit 100-2 itself responded that the error was due to a failure, for example. If it is not possible to send the error message, the bus monitoring circuit 1O, which monitors the status and contents of the first line 200, sends a response describing the error and its details on behalf of the unit 100-2. Send out.

〔Example〕

Figure 2 is an example configuration diagram, Figure 3 is a status generation circuit,
FIG. 4 shows a status determination circuit, and FIG. 5 shows a time chart of the present invention (during write operation to a register).

In FIG. 2, the symbols 100.200.300. 1 to 10 correspond to FIG. 1 or FIG. 6, respectively.

Hereinafter, with reference to FIGS. 3 to 5, the unit 10
The following description assumes that 0-1 transfers information to register 7 of unit 100-2.

Arbitration control circuit 17 requests (BREQ-0
), the bus right control circuit 3 issues permission (BGRM
-0) is issued. Unit 1001 has the permission (BG
RM-0), the transfer control circuit 16 turns on the gate 6, and at the same time, the transfer control circuit 16 turns on the register 5.
The information prepared in the above is sent out onto the line 200. Information is sent on the data bus 200-1 in the order of command, address, and data, and in synchronization with the sending of the command,
bus star indicating the start of the bus sequence during τ)
(BSTT) is issued.

Among the commands, unit 1, which is the bus master,
I between 00-1 and the unit 1002 that should become a slave
D is displayed, and unit 100-2 takes in the information on data bus 200-1, assuming that the information is addressed to itself.

bus ml 1111 (when the bus monitoring circuit 10 receives a bus start (BSTT) on the t bus 200-2).

A permission (BGR3-1) is issued to the slave unit 100-2.

The unit 100-2 receives the permission (BGR3-1), and the transfer control circuit 16 turns on the gate.

Then, the unit 100-2 that is the slave is 1
Every τ, the information on the data bus 200-1 is received in its register 7, and a response is sent out on the response line 200-3 to report the status at the time of receiving the information. RC, RA, RD, . . . shown in FIG. 5 are information IC, A on the data bus 200-1.

It represents the response as a result of receiving D, .

The unit 100-1 serving as a mask performs the transfer while confirming that each piece of information has been normally received by the above response every 1τ, and synchronizes with the last transfer to transfer the information to the fifth unit.
As shown in the figure, a transfer end (CMPT) is issued. In response, the bus arbiter 300 immediately grants (BG
RM-0) dropped.

■After τ, permission (BGR3-1) is also dropped.

The status generation circuit 13-1 of the unit 100-2 is
It is known from the command on data bus 200-1 that it is a write operation to register 7. Status generation circuit 1
A part of 3-1 is shown in Figure 3. Since this is a write operation to the register 7, register access is "1", read operation is "O", memory access is "0", and memory storage end is "O".

Therefore, the status return instruction becomes "O", and the status generation circuit 13-1 does not generate or return the status S.

Note that conventionally, a status return instruction has been formed based only on register access and memory storage completion notification.

On the other hand, the status determination circuit 13- of the unit 100-1
2 knows from the command sent onto the data bus 200-1 that it is a write operation to the register. The status determination circuit 13-2 is shown in FIG. unit 100
At the same time as the start of the operation, the unit 100-1 normally turns ``Busy'' to 7 and sets ``Busy'' to the unit 100-1 at the same time as the start of the operation.

It remains busy and waits for the status S to be returned.

However, in this case, the register access is "I" and the write operation is "l", so the response is normal (normal reception is "l") and the inspection (end) timing of the final response (RLN) is "1". ”, the Bus
It is configured such that y is dropped. That is, at this timing, the status determination circuit 13-2 determines that the operation has ended normally.

As a result, the operation is completed without returning the status S as shown in FIG.

Note that when the unit 100-1 reads information from the register 7 of the unit 100-2, the status generation circuit 13
-1, register access and read operations are both “1”
'', the status S is sent out. Also, the unit 100-1 is connected to the memory 1 of the unit 100-2.
5, the status S is sent by setting both the on-mory access and the memory storage (access) completion notification to "1". On the other hand, in the status generation circuit 13-2, the Bytel DI of register 5 is
The result of comparing D (destination ID) with its own ID using ENOR, the ByteO command/status determination bit “STS”, and the BSTT delay signal are A.
It is input to the ND gate and the timing at which the status S is returned is detected. Then, at this timing, it drops Busy and interrupts the processor. Also, the status S is analyzed at this timing, and if it is normal, the process ends at this point.

As a result of the above, the status S is returned as shown in FIG. 7, and the process ends after the predetermined process.

〔Effect of the invention〕

As explained above, according to the present invention, while the mask unit is sending out individual information, the slave unit or bus arbiter issues a response, and when a failure occurs, etc. Notification of the occurrence of a failure and the details of the failure can be notified using the corresponding response, and one bus can be released quickly. In addition, when the operation is a write operation to the register of a slave unit, the status can be transferred. Omitted.

By terminating the process with the response, the bus can be released early.

data bus, 200-2 bus control signal bus, 20
03 is a response line, 3 is a bus right control circuit,
5 and 7 are transmitting/receiving registers, 10 is a bus monitoring circuit, 1
3 is a status circuit, and 14 is a control circuit.

15 represents memory.

Claims (1)

[Claims] A plurality of units (100) are connected on a line (200) and are provided with a bus arbiter (300) that issues a bus usage right for occupying the line (200), When one of the units (100-1) requests the bus arbiter (300) to issue a bus usage right and obtains permission, it issues information on the line (200) and ) in a bus control system configured to temporarily release the occupancy of the bus. In the line (200), at least a data bus (2
00-1) and a bus control signal bus (200-2),
A response line (200-3) is provided, the unit (100) is provided with a status circuit (13) for generating and determining status, and the bus arbiter (300) is connected to the data bus (200-1). ) and the above bus control signal bus (200-2
) and the response line (200-3) to monitor the communication status between the units and to stop the communication when a failure occurs, and one of the units (100-1) ) performs a write operation to the register (7) of the other one (100-2) of the above unit, the other one (100-2) of the above unit
) status circuit (13) of one of the above units (1
1. A bus control method characterized by omitting the return of status to 00-1) and returning the status in other cases.