KR0146521B1 - Protocol controller and data transfer in multiprocessor system - Google Patents

Abstract

The present invention relates to a bus protocol controller in a multiprocessor system. More particularly, the present invention relates to a bus protocol controller and a data transmission method of a multiprocessor system for arbitrating an address bus and a data bus to improve bus efficiency. An internal bus connector connecting the control signal of the processor and each function block of the protocol controller in the processor board; An instruction generator for generating address information of the protocol; An arbiter that arbitrates the system bus in a priority manner; A protocol state transition to perform an address and read state transition or a write state transition; And a command status register for driving the protocol status transition or recording the status on a system bus. Therefore, as described above, the bus protocol controller of the present invention performs arbitration of the address bus and the data bus, respectively, so that data can be transmitted and received simultaneously with the command, thereby increasing the bus efficiency. In addition, it provides the function to perform the application test and performance test when using the system bus.

Description

Bus Protocol Controller and Data Transfer Method in Multiprocessor Systems

Figure 1a is a block diagram showing a sequential response method of the prior art

Figure 1b is a block diagram showing a non-sequential response method of the prior art

2 is a block diagram illustrating a bus protocol controller according to the present invention.

FIG. 3 is a block diagram of the internal bus connector shown in FIG.

4 is a block diagram of the arbiter shown in FIG.

5 is a block diagram of the RMC controller shown in FIG.

6 is a clock waveform diagram for the system bus communication shown in FIG.

7 is a system bus protocol diagram of a bus protocol controller according to the present invention.

8 is an address and read state transition diagram of a bus protocol controller according to the present invention.

9 is a write state transition diagram of a bus protocol controller according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus protocol controller in a multiprocessor system, and more particularly, to a bus protocol controller and a data transmission method of a multiprocessor system for arbitrating an address bus and a data bus for data transmission to increase bus efficiency.

Intel's patent, shown in US Pat. No. US005191649, relates to a multiprocessor system with data transfer and data buses separated into an ordered response and an out-ordered response.

Figure 1a is a block diagram showing a conventional sequential response method of the US patent number US005191649, the sequential response method until the master processor board to send data when the master processor board wants to read data from another processor board to send data If the communication link is maintained, the process is as follows.

In FIG. 1A, when the first processor board 10 wants to read data from the second processor board 12, the first processor board 10 first requests a bus for the address bus and acquires a bus by bus arbitration. After the read command is sent to the second processor board 12, the second processor board 12 transmits data to the first processor board 10. At this time, the first processor board 10 occupies the system bus and waits until the data reception is completed, and then performs another transfer command when the data reception is completed.

In this case, since the system bus is still occupied while the transfer command is being executed, the data transfer efficiency is inferior because other processors cannot use the system bus.

FIG. 1B illustrates a conventional non-sequential response method of US Patent No. US005191649. In the non-sequential response method, once the processor board to receive does not occupy the bus and releases the bus, the processor board to transmit When the send data is prepared, the sendable command, that is, the read response command, is used to connect the bus and transmit the data.

When first reading data of the second processor board 16 from the first processor board 14 of FIG. 1B, the first processor board 14 first requests a bus for the system bus and then the system bus through the bus arbitration. Acquire. Then, when a read command is sent to the second processor board 16 and the system bus is released, the second processor board 16 prepares data to be transmitted and then makes a bus request to the system bus. If obtained, a read response command is sent to the first processor board 14 and data is transmitted.

The problem of the prior art as described above is that in a multiprocessor system, since there is only one arbiter in each processor board, it is impossible to simultaneously transmit and receive commands and data, and data transmission efficiency is increased by transmitting unnecessary read response commands in a non-sequential response method. It is greatly reduced.

An object of the present invention for solving the above problems is a bus of a multiprocessor system that transmits data without a read response command when processing data in a nonsequential response method or when a necessary data transmission delay occurs in a multiprocessor system. In providing a protocol controller.

Another object of the present invention is to provide a data transmission method of a read cycle of a multiprocessor system that transmits data without a read response command when processing data in a non-sequential response method or when a necessary data transmission delay occurs in a multiprocessor system. It is.

Another object of the present invention is to provide a data transfer method of a write cycle of a multiprocessor system when data is processed in a nonsequential response method or a required data transfer delay occurs in a multiprocessor system.

A bus protocol controller in a multiprocessor system for achieving the above object includes an internal bus connector for interfacing control signals of a microprocessor (CPU) and respective function blocks in a protocol controller in a processor board;

A command generator for generating address information of a protocol according to a control signal introduced from the internal bus connector;

An arbiter for arbitrating a system bus by a priority method when an address bus request signal or a data transmission ready signal is received from the internal bus connector;

An RMC controller which reads data of a single address by a command introduced from the internal bus connector and subsequently controls a write operation of data of a single address;

A protocol state transition to perform read and write commands by a data transfer command when the arbitrator arbitrates and occupies a system bus; And

And a clock generator for generating a transmission and reception clock for data transmission and a clock for state transition to the arbiter, the RMC controller, the command generator, and the protocol transition.

The bus protocol controller in the multiprocessor system further includes an application having a system bus measurement function through address bus arbitration by notifying an error occurrence during the use of the system bus and counting a signal to occupy and retry an address during mediation. It is characterized by.

And a bus protocol controller in said multiprocessor system, said RMC controller comprising: a system address register for latching and storing an address at every system bus clock when an RMC instruction is already being executed;

A local address register that stores a corresponding address of an RMC operation already performed on the master processor board; And

And a RMCBUSY signal generator for comparing the system address register with the local address register and generating a signal (SRMCBSY signal) for inhibiting RMC operation of another master processor board if the same.

And in the bus protocol controller in the multiprocessor system, the protocol state transition

An address and read state transition in which the master processor board reads data of a single address and a plurality of addresses from the slave processor board; And

The master processor board is configured as a write state transition to write data of a single address and a plurality of addresses to the slave processor board.

And in the bus protocol controller in the multiprocessor system, the arbiter

An address bus arbiter for arbitrating the address bus; And

And a data bus arbiter for arbitrating the data bus.

In addition, the arbiter may arbitrate the address bus and the data bus arbitration separately from the address arbiter and the data bus arbiter to separate the transmission command and the data transmission and reception.

The bus protocol controller in the multiprocessor system may further include a command status register for driving the protocol state transition without software intervention or recording a state on the system bus.

And a bus protocol controller in the multiprocessor system, wherein the bus protocol controller

A single read that reads data at a single address;

Single write to write data of a single address;

Plural reads for reading the data of the address of the box;

Plural writes to write data of plural addresses; And

Read data of a single address and then transfer the data to the RMC cycle to write data of a single address.

On the other hand, a data transmission method of a non-sequential response type read cycle of a multiprocessor system for achieving the another object of the present invention is

Requesting use of the address bus at the master processor board and arbitrating the address bus request by priority;

Transmitting address information to a slave processor board when the address bus is occupied by the arbitration;

Responding to the master processor board whether there is an abnormal state after receiving the address information;

Requesting the use of the data bus when the read data is ready to be transmitted and mediating the occupation of the data bus according to priority;

Transmitting data information from a slave processor board to a master processor board at a receiving end when the data bus is occupied in the data bus arbitration step; And

The master processor board receiving the data from the slave processor board after receiving the data characterized in that it comprises the step of responding to the slave processor board status.

In the data transmission method of a non-sequential response type read cycle of the multiprocessor system, when a plurality of units of data are transmitted, the size of the transmission data included in the address information is counted inversely every time one unit of data is transferred. It is characterized in that the data is transmitted continuously until it is.

In the data transmission method of a non-sequential response type read cycle of the multiprocessor system, the address information

It includes information on the address, transmission type, transmission master processor board number, and transmission data size.

In the data transmission method of a non-sequential response type read cycle of the multiprocessor system, the status information in the step of responding to the abnormal status is characterized in that the normal, error, retransmission information.

In the data transmission method of a non-sequential response type read cycle of the multiprocessor system, the data information is a number of a master processor board that has transmitted a read command.

Meanwhile, a data transmission method of a non-sequential response type write cycle of a multiprocessor system for achieving another object of the present invention is

Requesting use of the address bus at the master processor board and arbitrating the address bus request by priority;

Transmitting address information to a slave processor board when the address bus is occupied by the arbitration;

A response step of transmitting a status of abnormality to a master processor board after receiving the address information;

Transmitting data from the master processor to the slave processor board; And

And transmitting a status of abnormality to the master processor board after receiving data from the slave processor board.

In the data transmission method of a non-sequential response type write cycle of the multiprocessor system, when a plurality of units of data are transmitted, the size of the transmission data included in the address information is counted inversely every time one unit of data is transferred. It is characterized in that the data is transmitted continuously until it is.

In the data transmission method of a non-sequential response type write cycle of the multiprocessor system, the status information in the step of responding to the abnormal status is characterized in that the normal, error, retransmission information.

In the data transmission method of a non-sequential response type write cycle of the multiprocessor system, the address information

It includes information on the address, transmission type, transmission master processor board number, and transmission data size.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. In the present invention, a multiprocessor system in which a plurality of processor boards each including a processor is connected to each other by a bus method, controls each processor board so that each processor board can use the system bus while satisfying the data transfer protocol of the system bus. The present invention relates to a bus protocol controller and a data transmission method.

2 is a block diagram showing the configuration of a bus protocol controller according to the present invention, wherein the bus protocol controller includes a CPU interface unit 200, an internal bus connector 210, an arbiter 220, an RMC controller 230, and a protocol. It is composed of a state shifter 240, an instruction status register 250, an instruction generator 260, a clock generator 270, and an application 280.

The internal bus connector 210 is a block acting as an interface, and includes the CPU interface 200, the RMC controller 230, the arbiter 220, the protocol state processor 240, and the command status register ( 250) and the command generator 260.

A block diagram for explaining the internal bus connector 210 in more detail is shown in FIG. 3, where the LMS signal is a master in which the processor board sends a command by reading or writing or according to the command of the master. This signal indicates whether the slave is transmitting or receiving data. When this signal is high, it means that the processor board is a master, and when it is low, it means that it is a slave, and is output from the CPU interface unit 200 of the master processor board.

The LRW signal is a signal for distinguishing read / write commands output from the CPU interface unit 200 of the master processor board. The LRW signal becomes high when a read command is executed and becomes low when a write command is performed. .

The LSTX * signal is a signal output from the CPU interface unit 200 of the master processor board. While the data transmission is an enable signal when transmitting data of one address at a time, the LBTX * signal is multiple at a time. This signal is enabled when transferring data of an address.

The LRMC * signal is enabled when the CPU interface unit 200 of the master processor board attempts to continuously write data after reading data at the corresponding address in data transmission at once.

The LCS * signal is a chip select control signal used by the CPU interface 200 of the master processor board to access the command status register 250 of the bus protocol controller.

LDATA [L: 0] is an internal data for use in reading and writing the value of the command status register 250.

The SRGO signal is an output signal of the internal bus connector 210. The SRGO signal is a transfer command enabled when the master processor board reads data of one address from the slave processor board, and the SWGO signal is data of one address of the master processor board. Is a transfer command that is enabled when writing to the slave processor board.

On the other hand, BRGO is a transfer command for the master processor board to read a plurality of addresses of data from the slave processor board, and BWGO is a transfer command for the master processor board to write a plurality of addresses of data to the slave processor board.

RMC signal is a kind of locking signal that reads and writes continuously and forms a transmission cycle. It is a transfer command generated when data is continuously written after reading data from the slave processor board.

The RQ signal is used when requesting a system bus, and is enabled when one of the SRGO, BRGO, BWGO, and RMC signals occurs.

The LSRDY * signal is a response signal of the slave processor board to read and write command signals output from the master processor board when the processor board operates as a slave.

The RDY signal is a signal output from the internal bus connector 210 by receiving the LSRDY * signal from the CPU interface unit 200, and the slave processor board returns to the master processor board in response to the read command from another master processor board. Used to indicate that data is ready to be sent.

The LOK * signal is generated when data transmission is normally completed. The LERR * signal is generated when an error occurs during transmission. The LRTY * signal is enabled when retransmission is required after transmitting data.

Meanwhile, the arbiter 220 is a block for arbitrating when a plurality of processor boards want to use a system bus. As shown in FIG. 4, the arbiter 220 may include an address bus arbiter 222 and a data bus arbiter 224. Is done.

The address bus arbiter 222 arbitrates the address bus when each process board intends to use the address bus of the system bus, and when one of the SRGO, BRGO, SWGO, BWGO and RMC signals of FIG. The RQ signal output from the internal bus connector 210 is input to the address bus arbiter 222 and performs arbitration according to a priority scheme. Each processor board has an RQ signal for requesting an address bus, and the SARQ [N: 0] signal is an address bus request signal that is assigned and output one by one for each processor board. The AWIN signal is a signal generated by the address arbiter 222 when the address bus arbitrates in accordance with the address request signal RQ and occupies the address bus, and is transmitted to the CPU interface unit 200. The ARTY signal is a signal generated to retry the address bus arbitration when the bus has not occupied the address bus as a result of the address bus arbitration and is transmitted to the CPU interface unit 200.

The data bus arbiter 224 is a block that arbitrates the right to use the data bus of the system bus when the processor board operates as a slave, and arbitration is performed as follows. First, when the slave processor board receives a read or write transfer command output from the master processor board and the corresponding data is ready, when the RDY signal output from the internal bus connector 210 is received, the data bus request signal SDRQ of another processor board is received. Take [M: 0] and compare it with its data bus request signal. At this time, if its own processor board has the highest priority, it outputs a DWIN signal to the CPU interface unit 200 that occupies the data bus and occupies the data bus.

Thus, the bus protocol arbiter according to the present invention provides both master and slave functions.

Meanwhile, when the RDY signal output from the internal bus connector 210 is introduced, the data bus arbiter 224 has its own processor board priority compared to the data bus request signal SDRQ [M: 0] output from another processor board. If is not the highest, output the DRTY signal to the CPU interface unit 200 to retry databus arbitration and retry databus arbitration.

Meanwhile, the RMC controller 230 is a block for controlling the master processor board according to a bus protocol when the master processor board intends to perform a read modified cycle (RMC) operation. The block diagram is illustrated in FIG. 5. Here, the system address register 238 latches and stores an address every system bus clock when an RMC command is already being executed, and the local address register 236 stores a corresponding address of an already performing RMC operation of the master processor board. In addition, the RMCBUSY signal generator 234 compares the system address register 238 with the local address register 236 and generates a signal SRMCBSY for inhibiting the RMC operation of another master processor board if they are the same. The RMC WIN register 232 is a register indicating whether the magnetic processor board is using the RMC.

Meanwhile, the operation of the RMC controller 230 is performed as follows. First, when the RMC signal output from the internal bus connector 210 to command the RMC is input to the RMC controller 230, the address of the slave to be accessed is input via the internal address bus LADR [P: 0] to the local address register. The same address is stored on the system bus SADR [R: 0].

At this time, if another master processor board is not performing RMC for the corresponding address, that is, if there is no enabled SRMCBSY signal, the RMC WIN register 232, which is a register indicating that the RMC is being used in the own processor board, is set. After performing the RMC, the RMC WIN register 232 is reset.

If another master processor board is already performing the RMC for the corresponding address, the other master processor board executing the RMC enables the SRMCBSY signal and thus cannot perform the RMC. If the RMC WIN register 232 is reset at this time, the RMCRTY signal, which is a signal for retrying RMC, is enabled and output to the CPU interface unit 200, and waits until the SRMCBSY signal is disabled. .

On the other hand, enabling the SRMCBSY signal can be done only by the master processor board performing RMC. The process is as follows. When the RMC is to be executed, the corresponding address is stored in its local address register 236, and then during the RMC, the address is latched in the system address register 238 at every system bus clock to store the address in the local address register 236. Compare with address. Thus, if it turns out to be the same address, it outputs the SRMCBSY signal through the RMCBUSY signal generator 234 to prevent other master processor boards from accessing that address.

The clock generator 270 is a block for supplying a clock required for the operation of the arbiter 220, the RMC controller 230, the protocol state shifter 240, the command generator 260, and the command state register 250. 6 shows a clock waveform diagram for system bus communication. The clock generated by the clock generator 270 is composed of three clocks: the TXCLK clock, the RXCLK clock, and the state transition clock. The data transmission on the system bus transmits address, data, and other information to the two reference clocks. It consists of a TXCLK clock for transmission and a RXCLK clock for receiving data. D is a time delay period for data transmitted in accordance with the TXCLK clock to be received in accordance with the RXCLK clock after the data is stabilized on the system bus. D is a constant clock phase delay in three or two quarters of the clock period. do. In addition, the state transition clock applied to the protocol state transition uses the inverted clock of the RXCLK clock for reception.

On the other hand, the instruction generator 260 is a block for generating data transmitted in the step of providing address information (AINFO step) when the master processor board accesses the slave processor board in the bus protocol, and includes an address, a transmission form, and a transmission master processor board. Generate information about the number and size of the transfer data. The above transmission type is composed of single read, single write, multiple read, multiple write and RMC cycles.

The send master processor board number is a step in which the master processor board sends a read command during a read transmission, and then sends data information for transmitting data to the master processor board to which the corresponding slave processor board sends the read command (DINFO step). .

The instruction status register 250 is composed of an instruction register and a status register. The instruction register is used for testing purposes such as running a protocol state transition without software intervention, or repeating only addressbus arbitration or databus arbitration. The status register in the command status register 250 records the normal, error, and retransmission status at the AACK or DACK signal stage of the bus protocol to be described later on the system bus so that the software can read the bus status. Waiting and retransmission status during the RMC cycle is also recorded. In the state register, the RQ, SRGO, SWGO, BWGO, RMC, and RDY states of the internal bus connector 210 are recorded.

The application 280 outputs an operation signal indicating that the system bus is operating and an ERR signal indicating an error when an error occurs through the internal utility bus.

In addition, AWIN, which is a signal occupying an address, and ARTY, which is a signal retrying to occupy an address, are counted and used for system bus measurement through address arbitration. The counted values are software readable.

The protocol state transition unit 240 is a control block that controls each stage of the bus protocol to perform read / write and RMC operations according to the system bus protocol, and includes two types of addresses, read state transitions, and write state transitions. It consists of.

Before describing the protocol state shifter 240, the protocol of the system bus that is the basis of the protocol state shifter 240 will be described with reference to FIG. 7 is a system bus protocol diagram of a bus protocol controller according to the present invention. Where M and S represent transmissions on the master and slave processor boards respectively. There are five communication protocols on the system bus: single read, single write, multi-read, multi-write and RMC cycles. First, detailed components of the five protocols will be described.

In the AINFO step, the master processor board transmits address information to the slave processor board. The address information includes a transmission address, a transmission type, a transmission master processor board number, and a transmission data size. The ARQ # step is an address bus request step for the master processor board to access data when reading or writing the slave processor board.

The AACK step is a response step in which the master receives the data received in the AINFO step of the slave processor boards without error. This step can also send messages of errors and retransmissions, where the SRMCBSY signal from the RMC controller is written to the status register.

The DRQ # step is an arbitration step that requires a data bus when a read command is received from the master processor board and data is prepared and transmitted from the slave processor board. The DACK step is a step in which the receiving side (master processor board or slave processor board) receives the data without error. In the DINFO step, the slave processor board stores the number of the master processor board to which the read command has been transmitted and transmits the data to the master processor board to receive the data when the data is ready to be transmitted.

Since the data size is transmitted in units of multiple reads and multiple writes, a counter by the data unit counter (not shown) operates simultaneously in the master processor and the slave processor. For the above operation, the data transfer size is transmitted to the slave processor board in the AINFO step. The reference clocks of the address and read state transitions and the write state transitions use a signal shifted RXCLK 180 degrees.

Based on the basic steps of constructing the above bus protocols, the protocols for the above five bus cycles will be described.

First, the protocol for a single read cycle is: When the master processor board requests an address bus in the ARQ # stage, the master bus board arbitrates in the address bus arbiter 222 to occupy the address bus, and transmits address information to the slave processor board to read data in the AINFO stage. do. In the AACK step, the corresponding slave processor board receiving the address information in the AINFO step transmits a response signal indicating that the address information has been received to the master processor board. The slave processor board goes through a waiting state until it is ready to access the data at the address it wants to read and send the data to the master processor board. When the data is ready to be transmitted, the data bus is requested in the DRQ # stage, the data bus arbiter 224 of the slave processor board arbitrates, and the data bus is occupied. The number of one master processor board is transmitted, and at the step D0, one unit of data is applied to the data bus and transmitted to the master processor board. DACK0 is a step of transmitting a response signal indicating that the master processor board has received data to the slave processor board.

The following describes the protocol for single write cycles. When the master processor board requests the address bus in the ARQ # stage, the master bus board arbitrates in the address bus arbiter 224 to occupy the address bus, and transmits address information to the slave processor board to write data in the AINFO stage. do. In the AACK step, the corresponding slave processor board receiving the address information in the AINFO step transmits a response signal indicating that the address information has been received to the corresponding master processor board performing the write command. In the D0 stage, the master processor board receives the response signal of the slave processor in the AACK stage, and transmits one unit of data to the data bus. The DACK0 step transmits a response signal indicating that the slave processor board has received data to the master processor board.

Meanwhile, the protocol for the multi-read cycle is as follows. When the master processor requests an address bus in the ARQ # stage, the master bus arbitrates in the address bus arbiter 222 of the master processor board, occupies the address bus, and transmits address information to the slave processor board to read data in the AINFO stage. . In the AACK step, the corresponding slave processor board receiving the address information in the AINFO step transmits a response signal indicating that the address information has been received to the master processor board. The slave processor board goes through the wait state until it is ready to access the data at the address it wants to read and send the data to the master processor board. When the data is ready to be transmitted, the data bus is requested in the DRQ # step and the data bus arbiter 224 of the slave processor board arbitrates to occupy the data bus. In the DINFO step, the slave processor board transmits data information, that is, the number of the master processor board which has read command, and in step D0, one unit of data is applied to the data bus and transmitted to the master processor board.

The DACK0 stage is a response signal indicating that the master processor board has received data of the D0 stage, and the D1 stage transmits data to the master processor board by applying a unit of data to the data bus. The DACK1 stage is a response signal indicating that the master processor board has received the data of the D1 stage. In the D2 stage, the slave processor board applies a unit of data to the data bus and transmits the data to the master processor board. According to the size of the data to be read included in the address information of the AINFO stage, the slave processor board applies the data of the last Dn to the data bus and transmits the data to the master processor board. Then, the master processor board receives the data of the D1 stage in the DACKn stage. Send the response signal to the slave processor board.

The protocol for the multiwrite cycle is as follows. When the master processor board requires an address bus in the ARQ # stage to write data, the master processor board arbitrates in the master bus board and occupies the address bus. In the AINFO step, address information is transmitted to the slave processor board to write data of the master processor. In the AACK step, the corresponding slave processor board receiving the address information in the AINFO step transmits a response signal indicating that the address information has been received to the master processor board.

In the D0 stage, the master processor board receives the response signal of the slave processor in the AACK stage, and transmits one unit of data to the data bus. The DACKO stage transmits a response signal indicating that the slave processor board has received data to the master processor board, and the D1 stage receives a response signal of the slave processor of the AACK stage received by the MR processor board and transmits one unit of data to the data bus. Authorize and send.

The DACK1 stage is a response signal indicating that the slave processor board has received data of the D1 stage, and the D2 stage transmits the master processor board to the slave processor board by applying a unit of data to the data bus. According to the size of the data to be written in the address information of the AINFO step, the master processor board applies the data of the last Dn to the data bus and transmits the data to the slave processor board. The slave processor board receives the data of the step Dn in the DACKn step. Send a response signal to the master processor board to complete the multi-write cycle.

Finally, the protocol for the RMC cycle is: When the master processor requests the address bus in the ARQ # stage, the master bus arbitrates in the address bus arbiter 222 of the master processor board, occupies the address bus, and transmits address information to the slave processor board to read data in the AINFO stage. In the AACK step, the corresponding slave processor board receiving the address information in the AINFO step transmits a response signal indicating that the address information has been received to the master processor board. The slave processor board goes through a waiting state until it is ready to send data to the master processor board.

When the data is ready to be transmitted, the data bus is requested in the DRQ # step and the data bus arbiter 224 of the slave processor board arbitrates to occupy the data bus.

In addition, in the DINFO stage, the master processor board number of the read command is transmitted. In the D0 stage, one unit of data is applied to the data bus and transmitted to the master processor board. DACK0 transmits a response signal indicating that the master processor board has received data read to the slave processor board.

After processing the data read from the master processor board, it goes through the waiting stage until the master processor is ready to write back to the read slave processor board.

In the ARQ # stage, when the master processor requests an address bus, the address bus arbiter 222 of the master processor board arbitrates to occupy the address bus and transmits address information to the slave processor board to write data in the AINFO stage. In the AACK step, the corresponding slave processor board receiving the address information in the AINFO step transmits a response signal indicating that the address information has been received to the corresponding master processor board performing the write command.

In the D0 stage, the master processor board receives the response signal of the slave processor in the AACK stage, transmits one unit of data to the data bus, and transmits the response signal indicating that the slave processor board receives the data in the DACK0 stage. Send.

When an address bus is requested from the master processor to be written in the ARQ # stage, the address bus arbiter 222 of the master processor board arbitrates to occupy the address bus and sends address information to the slave processor board to write data in the AINFO stage. Send. In the AACK step, the corresponding slave processor board receiving the address information in the AINFO step transmits a response signal indicating that the address information has been received to the corresponding master processor board performing the write command.

In the step D0, the master processor board applies one unit data to the data bus to the slave processor board. In the DACK0 step, the slave processor board transmits a response signal indicating that data has been received to the master processor board to complete the RMC cycle.

A bus protocol state transition diagram will be described based on the bus protocol described above. First, the address and read state transition diagram will be described. 8 illustrates an address and read state transition diagram of a bus protocol controller according to the present invention. The AIDLE step of reference numeral 800 is a state in which no transmission command is performed, and the address intermediate device 222 in the arbiter 220 receives the RQ signal, which is an address request signal transmitted from the internal bus connector 210 of the master processor board. When an address bus arbitration is performed to occupy the system address, the AWIN signal indicating that the address is occupied is output to the CPU interface 200, and the process proceeds to the AINFO step 810. In the AINFO step 810, the master processor board number to be transmitted, the transmission type and the data size are transmitted to the corresponding slave processor board to be accessed, and the slave processor board to change data to the WAIT0 820 step reads the data. Wait until the processor board is ready to send. In the AACK step 830, the slave processor board stores the normal, error, and retransmission states, which are the response of the slave processor to the address information received in the AINFO step 810, in the state register and transitions to the AIDLE 800 step in the error or retransmission. do. At this time, if a single write command SWGO or a multi-write command BWGO is output from the internal bus connector 210, the process transitions to the AIDLE 800 stage to prepare for writing.

On the other hand, if the response of the slave processor in the AACK (830) step is OK (OK), the transition to the WAIT1 (840) step and waits until the slave processor board is ready to transmit data to the receiving master processor board and RD0 (850) Transition to step). When the preparation for transmission is completed in the RD0 (850) step, the first data is transmitted from the slave processor board to the master processor board. After the SRGO command is output from the internal bus connector 210, the data received by the master processor board in the RDACK (860) step Sends normal, error and retransmission signals to the slave processor board via the system bus.

At this time, even if an error occurs, in order to simplify the implementation of the bus protocol, once the transfer is completed, the master processor board restarts the bus protocol.

On the other hand, if the BRGO command is output from the internal bus connector 210, the transition from the RD0 (850) to the MRD (870) step, the slave processor board is applied to the system bus by the data unit by unit to the master processor board.

In the MRDACK 880, whenever normal data received by the master processor board in the MRD 870 is transmitted, the normal, error, and retransmission signals of the data are transmitted to the system bus. In step WIDLE (800), the bus protocol is restarted.

The CNTSIZ representing the data unit size to be transmitted in the data unit counter of the protocol state shifter 240 is counted inversely for each data transmission, and if it is not 0, the state transmitted in the MRDACK 800 is stored in the state register and the MRD 930 step is performed. Transmit to and continue sending data to slave processor board. At this time, when the CNTSIZ indicating the completion of the transmission of the plurality of data becomes 0, the process proceeds to step AIDLE (800).

If the data transfer is normal, in the multi-read command, one unit of data included in the address information of the master processor board in the AINFO (810) step is counted inversely and transferred to the received data until it reaches zero. The MRDRCK 880 and the MRD 870 steps, which are data response states, are repeatedly performed. When the data transmission is completed or an error occurs in the MRDACK 880 step, the terminal transitions to the AIDLE 800 step.

Next, the write state transition diagram will be described. FIG. 9 is a write state transition diagram of a bus protocol controller according to the present invention. When the WIDLE step of the reference numeral 900 that does not perform a transfer command outputs a single read command SWGO from the internal bus connector 210, SWDO 910 In step), data is transmitted from the master processor board to the slave processor board. In the WDACK 920 step, the slave processor board transmits whether the received data state is normal or error (ERR), and the master processor board checks the response state and stores it in the state register in the command status register 250 of FIG. .

In addition, when the BWGO, which is a multi-read command, occurs in the internal bus filter 210 of FIG. 3 at the WIDLE 900 stage, the process transitions to the MWR stage 930 to transmit data from the master processor board to the slave processor board. Each time a unit of data transmission is performed in a data unit counter (not shown) in the protocol state shifter 240, it decreases by one in the data unit size (CNTSIZ) to be transmitted. M indicates that the master processor board is in the transmit state and S indicates that the slave board is in the transmit state.

Accordingly, the state is stored in the state register in the MWDACK 940 until the data size CNTSIZ becomes 0, and the state transitions to the MWR 930 to continue transmitting data to the slave processor board. In step MWDACK 940, the state is stored in the state register.

On the other hand, when the error ERR or CNTSIZ becomes 0 in the MWDACK 940 step, the transition to the WIDLE 900 step.

Since the RMC cycle is a read-write write transfer, a single read is performed at the address and read state transition described in FIG. 8, and then a single write is performed at the write state transition described in FIG. 9 to complete the cycle.

At this time, address information transmitted before reading and writing is transmitted in the AINFO step 810 during the address and read state transition.

Therefore, as described above, the bus protocol controller of the present invention performs arbitration of the address bus and the data bus for data transmission, thereby enabling data transmission and reception at the same time to increase bus efficiency. Each processor board has one bus protocol controller, so it has a simple interface with the internal logic of the processor board, making it easy to use universally. In addition, it provides the function to perform the test and performance test of the application program by providing the signal or status signal generated when using the system bus.

Claims (17)

A bus protocol controller in a multiprocessor system, comprising: an internal bus connector for interfacing control signals of a microprocessor (CPU) in a processor board and respective functional blocks in a protocol controller; A command generator for generating address information of a protocol according to a control signal introduced from the internal bus connector; An arbiter for arbitrating a system bus by a priority method when an address bus request signal or a data transmission ready signal is received from the internal bus connector; An RMC controller which reads data of a single address by a command introduced from the internal bus connector and subsequently controls a write operation of data of a single address; A protocol state transition to perform read and write commands by a data transfer command when the arbitrator arbitrates and occupies a system bus; And a clock generator for generating a transmission and reception clock for data transmission and a clock for state transition to the arbiter, the RMC controller, the command generator, and the protocol transition. Protocol controller. The multiprocessor of claim 1, further comprising an application having a system bus measurement function through address bus arbitration by counting a signal for notifying an error occurrence while using the system bus and occupying and retrying an address during mediation. Bus protocol controller in the system. The system of claim 1, wherein the RMC controller comprises: a system address register configured to latch and store an address at every system bus clock when an RMC command is already being executed; A local address register for storing a corresponding address of an RMC operation already performed on the master processor board; And an RMCBUSY signal generator which compares the system address register with the local address register and generates a signal (SRMCBSY signal) for inhibiting RMC operation of another master processor board if it is the same. Controller. The method of claim 1, wherein the protocol state transition unit comprises: an address and read state transition unit for the master processor board to read data of a single address and a plurality of addresses to the slave processor board; And a write state transition in which the master processor board writes data of a single address and a plurality of addresses to the slave processor board. 2. The apparatus of claim 1, wherein the arbiter comprises: an address bus arbiter that arbitrates an address bus; And a data bus arbiter for arbitrating the data bus. 6. The bus protocol controller according to claim 5, wherein the address bus and the data bus arbitration are arbitrated separately in the address arbiter and the data bus arbiter to separately perform transmission commands and data transmission and reception. The bus protocol controller of claim 1, further comprising a command status register for driving the protocol state transition without software intervention or recording a state on a system bus. 2. The system of claim 1, wherein the bus protocol controller comprises: a single read that reads data of a single address; Single write to write data of a single address; Reading a plurality of data at a plurality of addresses; Plural writes to write data of plural addresses; And transmitting data to an RMC cycle which reads data of a single address and then writes data of a single address. CLAIMS What is claimed is: 1. A data transmission method of a non-sequential read cycle in a multiprocessor system, comprising: requesting use of an address bus at a master processor board and arbitrating address bus requests by priority; Transmitting address information to a slave processor board when the address bus is occupied by the arbitration; Responding to the master processor board whether there is an abnormal state after receiving the address information; Requesting the use of the data bus when the read data is ready to be transmitted and mediating the occupation of the data bus according to priority; Transmitting data information and transmitting data from the slave processor board to the master processor board at the receiving end when the data bus is occupied in the data bus arbitration step; And responsive to the slave processor board by the master processor board receiving data from the slave processor board after receiving the data, from the slave processor board. 10. The method of claim 9, wherein when transmitting a plurality of units of data, the data is continuously transmitted until the number is zero by counting the size of the transmission data included in the address information each time one unit of data is transmitted. Read cycle data transmission method in a multiprocessor system. 10. The method of claim 9, wherein the address information includes information on an address, a transmission type, a transmission master processor board number, and a size of a transmission data. 10. The method of claim 9, wherein the status information in the step of responding to the abnormality status is normal, error, retransmission information. 10. The method of claim 9, wherein the data information is a number of a master processor board that has transmitted a read command. CLAIMS What is claimed is: 1. A data transfer method of a non-sequential write cycle in a multiprocessor system, comprising: requesting use of an address bus at a master processor board and arbitrating address bus requests by priority; Transmitting address information to a slave processor board when the address bus is occupied by the arbitration; A response step of transmitting an abnormal state state to the master processor board after receiving the address information; Transmitting data from the master processor board to the slave processor board; And transmitting a status of abnormality to the master processor board after receiving data from the slave processor board. 15. The method of claim 14, wherein when transmitting a plurality of data units, data is continuously transmitted until a value of 0 is obtained by reversing the size of the transmission data included in the address information for each transmission of one unit of data. A write cycle data transfer method in a multiprocessor system. 15. The method of claim 14, wherein the status information in the step of responding to the abnormal status is normal, error, retransmission information. 15. The method of claim 14, wherein the address information includes information on an address, a transmission type, a transmission master processor board number, and size of transmission data.