JPH02154387A - Solid-state memory device - Google Patents

Abstract

PURPOSE:To make high-speed access to an arbitrary data block with the less number of signal lines by successively outputting addresses of relevant storing blocks of a memory section from the leading address outputted from a block address storing means. CONSTITUTION:A block designating data storing means 28 stores block designating data which designate arbitrary storing blocks of a randomly accessible memory section 24. A block address storing means 30 holds the leading addresses of plural storing blocks of the section 24 and outputs the leading address of a relevant storing block in accordance with block designating data outputted from the means 28. Then a sheet number counter 32 successively outputs addresses of relevant storing blocks of the section 24 from the leading address outputted from the means 30. Therefore, high-speed access can be made to an arbitrary data block with the less number of signal lines.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a solid state memory device that is removable from a main device such as an electronic still camera.

[Conventional technology]

Electronic still cameras that use magnetic floppy disks as recording media are currently on the market, but as semiconductor memory becomes cheaper and more highly integrated, solid-state memories such as semiconductor memory are being used instead of magnetic floppy disks. An electronic still camera system has been proposed.

[Problem to be solved by the invention]

When a solid-state memory device consisting of a large-capacity IC memory that is removable from the camera body is used as a recording medium, it is necessary to reduce the number of connection lines with the camera body and to enable high-speed access. Specifically, in order to simplify the connection, increase reliability, and reduce the cost, the connection between such a solid-state memory device and the camera body is performed using a serial data line and several control lines. Configuring the data lines and address lines in parallel, as in a normal circuit-embedded image memory, results in an increase in the number of connection lines.
This is because reliability decreases and costs increase.

In normal use, the solid-state memory device has random
Since there is no access, a serial data line is sufficient, but for example, when performing high-speed continuous shooting or random playback of captured images, high-speed random data lines can be used for each image storage unit (block).
Access ability is required.

Therefore, the present invention requires fewer connection lines, and also allows for random connection.
The purpose is to present a solid state memory device with access capability.

[Means to solve the problem]

A solid-state memory device according to the present invention includes a randomly accessible memory section, block designation data storage means for storing block designation data that designates an arbitrary storage block of the memory section, and a memory section that stores a plurality of storage blocks of the memory section. block address storage means that holds each start address and outputs the start address of the corresponding storage block according to the block specification data output from the block specification data storage means; It is characterized by comprising an address means for sequentially outputting addresses of corresponding storage blocks in the memory section from the first address.

[Effect]

By providing the above block address storage means,
When accessing a specified storage block in the memory section,
This saves the effort of calculating each address value in the memory section. Therefore, the main device only needs to apply information specifying the memory block to be accessed to the solid-state memory device, and high-speed data transfer is possible with fewer signal lines.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a configuration block diagram of an embodiment in which the present invention is applied to an all-solid-state electronic still camera using an IC memory. The light transmitted through the photographic lens 10 enters the image sensor 12, and the image sensor 12 outputs RGB signals corresponding to the subject. The signal processing circuit 14 converts the RGB signals into image data,
For example, it is converted into luminance signal data, color difference signal data, or RGB data. The signal processing circuit 14 serially outputs this image data to the solid state memory device 1 consisting of an IC memory.
Supply to 6. The system control circuit 18 controls each part of the circuit including the display device according to input from a shutter switch and the like. Timing generator 20 is system control circuit 1
A series of sequence timing signals are applied to the signal processing circuitry 14 and the solid state memory device 16 according to instructions from the memory device 8 .

A lens 10, an image sensor 12, a signal processing circuit 14, a system control circuit 18, and a timing control circuit 20 are installed in the camera body, and the solid state memory device 16 is removable from the camera body. Solid state memory device 16 is connected to the camera body by serial data lines 14A, clock lines 14B, address/control lines 14C and status lines 140. Of course, there are power supplies and various auxiliary signal lines in addition to these, but they are not directly related to the present invention and are therefore not shown.

FIG. 2 shows an example of the internal configuration of the solid-state memory device 16. 22
24 is a parallel-to-serial converter, 24 is a memory section consisting of a randomly accessible semiconductor memory, 26 is an address counter, 28 is a preset setting ROM that holds the preset value of the address counter 26, and 30 is a storage section of the memory section 24. Storage state storage memory for storing state, 32
is the sheet number counter, 34 is the clock line 16B1 address/
This is a timing generator that generates various timing signals according to the control 1i16c and status line 16D. In addition, there are a power supply and various signal lines, but for ease of understanding, those that are unrelated to this embodiment are omitted from illustration.

A timing chart for setting the operation mode of the solid-state memory device F16 is shown in FIG. A and B in Figure 3.

Table 1 shows the correspondence between the binary values of parts C and D and the operation mode.
Shown below. The operating mode of solid state memory device 16 can be set by applying predetermined commands to solid state memory device 16 (specifically timing generator 34) via address control line 16C. The number counter 32 is
The address of the preset value setting ROM that holds the start address of the address counter 26 for each block is output. The output of the sheet number counter 32 is also the address of the stored state storage memory 30. For example, if the memory unit 24 has a storage area for 50 images, that is, 50 blocks, the storage state storage memory 30 stores a 1-bit signal (for example, "1") indicating whether each block is used or not. When it is "0", it is used, and when it is "0", it is unused). Incidentally, assuming that the amount of information per image is 100 Kbytes, the storage capacity of the memory unit 24 is 5 Mbytes for 50 images.

Since images in the memory section 24 can be read/written on an image-by-image basis, the address conflict counter 26 only needs to output a Natres signal that is incremented by one. Since the bit width of the density gradation per pixel of the image is 6 to 8 bits, the memory unit 24 is also accessed simultaneously in accordance with the bit width. In the case of reading from the memory section 24, this parallel data is sent to a parallel-to-serial converter 22, where it is converted into serial data. Memory section 2'
In the case of writing to 4, of course, this process is reversed.

FIG. 4 shows a timing chart of the setting command for the sheet number counter 32. The signal on address/control line 16C is sampled on the falling edge of the clock on clock line 16B. Normally it is in the H state, but the operation is determined by the 4-bit command (see Table 1) following one start bit. After a predetermined number of bits according to the command, address/control line 16C returns to the H state. In order to check the free area of the solid-state memory device 16 from the camera body side, a command to clear the number of shots counter 32 is sent (see 4.r.(1)). In response to this command, the sheet number counter 32 is cleared. As a result,
The used/unused data of the first block of the memory section 24 is read out from the stored state storage memory 30 and sent to the camera body side via the status line 16D.

Next, as shown in FIG. 4(2), a count up command is sent from the camera body side to the solid state memory device 16, and the number of sheets counter 32 is counted up. As a result, the used/unused data of the second block is read out from the stored state storage memory 30 and sent to the camera body via the status line LSD. By repeating this sequentially, the number of empty sheets in the memory section 24 can be confirmed.

For example, assume that you have used up to the third sheet.

When writing images, the number of images is written from the camera body side to the solid-state memory device 16 at the timing shown in FIG. 4 (3).
Send the download/load command, then change the setting value “
3" to specify the fourth memory block. In Fig. 4, 6 bits are sent out sequentially from the least significant bit. With this setting, the preset value setting ROM
28 outputs the start address of the fourth block.

A timing chart for writing data to the memory section 24 is shown in FIG. A data write command is sent to the solid state memory device 16 via the address/control line 16C, and then the data to be written is placed on the data line 16A in synchronization with the clock on the clock line 16D. The address counter 26 of the solid-state memory device 16 increments at the rising edge of this clock, and the memory section 24 takes in data at the falling edge of the clock. When the image data for one image is written, the solid-state memory device 16 waits for a command.

A timing chart for successive output of data from the memory section 24 is shown in FIG. When a memory read command is received,
As in the case of writing, the address counter 26 is incremented at the rising edge of the clock, and the stored data is read from the memory section 2-4 in response to the falling edge of the clock. The data read from the memory section 24 is serialized by the parallel/serial converter 22.

In the above embodiment, the camera body and the solid state memory device 16 are connected by four signal lines, but the clock line 16D and the data line 16A may be combined into one signal line.
Further, another control line (for example, write prohibition) may be added to expand the functionality. The status line 16B is normally used to refer to the contents of the stored state storage memory 30, but may of course be used for other purposes. Various formats are conceivable for storing image data in the memory unit 24, such as the NTSC system or PAL system itself, those using luminance signals and color difference signals, those using RGB signals, and those using compression.

According to Table 1, any data block can be accessed at high speed with a small number of signal lines. Another advantage is that the main device is freed from the burden of troublesome memory management and address calculation.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram of an embodiment of the present invention, FIG. 2 is a configuration block diagram of the solid-state memory device 16 of FIG. 1, FIG. 3 is a timing chart of two commands for the solid-state memory device 16, and FIG. 4 is a timing chart of the setting command for the sheet number counter 32 shown in FIG. 2, and FIG. 5 is a timing chart of the write command for the memory unit 24 shown in FIG.
FIG. 6 shows the timing of the read command of the memory section 24.
It is a chart. 16: Solid-state memory device 24-comemory part 26: Address counter 28 Nib reset value setting ROM 30
:Storage state storage memory 32:Number of sheets counter [Effect of the invention] As can be easily understood from the above explanation, the number of sheets of the invention is as follows: Figure 2

Claims (1)

[Claims] a randomly accessible memory section; a block specification data storage means for storing block specification data specifying an arbitrary storage block in the memory section; block address storage means for outputting the start address of the corresponding memory block according to the block designation data output from the block designation data storage means; 1. A solid-state memory device, comprising: address means for outputting an address of a corresponding memory block.