JPH02143347A - Information processor - Google Patents

Abstract

PURPOSE:To send out a memory request with respect to the storage area where access time is different at a timing avoiding a collision with a previously sent- out memory request by referring to a previously sent-out access history when the access history to a memory device is held and the memory device is newly made access. CONSTITUTION:When memory request instruction information M2 specifying reading to the storage area A2 of an access time is sent out at time t3, a memory request formation part 110 forms the memory request. Simultaneously, the memory request is sent out to a main memory device 130 at time t4, after access information C and D are referred to and it is confirmed that both of them are '0', namely that the a reply timing to the memory request does not collide with the reply timing to another request is confirmed. Thus, the memory request to the storage area where access time is different can be sent at the timing avoiding the collision with the previously sent-out memory request.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory access method for an information processing device that performs pipeline control on a storage device.

(Prior Art) Conventionally, a storage device that is pipeline-controlled by an information processing device has a configuration in which the entire storage area has a single access time. Alternatively, memory with medium to low speed and low price per unit of capacity was used.

[Three problems to be solved by the invention] In the conventional information processing device described above, despite the requirement for high-speed memory access, the storage device is pipeline controlled.
Because of this, it is considered very difficult to form a hierarchical structure regarding access time, which is considered to be the most traditional and effective in terms of performance and cost. Therefore, in order to improve the performance, an approach is taken in which all the devices are unified with a memory that has a fast access time and is expensive per capacity, but this has the disadvantage that it leads to a decrease in price performance.

[Means to solve the problem An information processing device of the present invention is.

The storage devices are TAl, TA2. ..., TAm f
It has a storage area of mJJl with an access time of TA+<TAa<...<TAm).

When you need to access the storage device, read/1! Sends memory request instruction information including Y write specification and address specification, and in the case of write specification.

It consists of an information processing unit that adds write data and sends it out, and a shift register that shifts at regular intervals.When a memory request specifying read is sent, access history information indicating the reply timing for the request is shifted. From the first stage of the register, for the access times TAG, TAz, . . . , TAm of the storage device iii, D2=TAm-TA2. Di=TAm-TAm
,..., D+ fi such that Di=TAm-TAm
=2.3°..., an access history register held in m-1 registers shifted by m1 hours.

In response to the memory request instruction information and write data sent by the information processing unit, a memory request including read/write designation and address designation is generated, and if the request is a 3-write designation, the write data is sent along with the memory request. If it is sent to a storage device and read is specified, it is based on the access time of the storage area related to the address specified in the request and the access history information related to the already sent memory request held in the access history register. ,
It is determined whether the reply timing when the generated memory request is sent matches the noburei timing related to the already sent request, and if it is determined that they do not match, the request is sent to the storage device and , registers the access history information related to the request in the access history register, and if it is determined that they match, the memory request generation unit suspends sending the memory request and waits until it is determined in 711 that there is no match. be.

Further, the information processing device of the present invention performs read/? when accessing the storage device is required. It is composed of an information processing unit that sends memory request instruction information including J-input specification and address specification, and also adds and sends write data in the case of write specification, and a shift register that performs a shift operation at fixed time intervals. When a memory request is sent, an access history register that holds multiple bits of access history information indicating the reply timing for the request and a multiple bits of access history MWd held by the access history register are decoded, A memory request ID detection unit that outputs ID information indicating reply timing for already sent memory requests, and a memory request ID detection unit that receives memory request instruction information sent by the information processing unit and write data at the time of writing, and performs read/write specification and address specification. Generates a memory request that includes the request, and if the request specifies writing, sends the write data along with the memory request to the storage device, and if the request specifies reading, detects the access time and ID of the storage area related to the address specified in the request. Based on the ID information related to the already sent memory request output by the unit, it is determined whether the reply timing when the generated memory request is sent matches the reply timing related to the already sent request. If it is determined that they do not match, the request is sent to the 3[2] storage device, and multiple bits of access history information related to the request are registered in the access history register, and if it is determined that they match, the request is sent to the memory The memory request generation unit suspends sending and waits until it is determined that there is no match.

[Operation] Since the access history to the storage device is maintained and the previously sent access history is referenced when newly accessing the storage device, memory requests for storage areas with different access times can be handled with a reply timing that is similar to the previously sent access history. It can be sent at a timing that does not conflict with the reply timing of the memory request.

[Embodiment 1] Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the information processing apparatus of the present invention, FIG. 2 is a block diagram showing the configuration of the access history register 120, and FIG. 3 is a block diagram showing the configuration of the access history register 120, and FIG. 3 shows how the information processing unit 100 outputs memory request instruction information. FIG. 4 is a timing chart showing an example of the timing, and FIG. 4 is a timing chart showing the output timing of the memory request of the memory request generation unit +10 and the reply timing of the main 2l device +30 with respect to the output timing of the memory request instruction information of FIG. be.

As shown in FIG. 1, this information processing device includes an information processing section 100, a memory request generation section +10, an access history register 120, and a main storage device 130.

The information processing unit +00 operates in machine cycle "C" and performs normal information processing, and when access to the main storage device 130 is required, it stores memory request instruction information such as read/write designation and address designation in the memory. It is output to the request generation unit 110. Furthermore, in the case of old specification, write data is added to the memory request generation unit 11.
Output to 0.

Main storage +30 is memory request input port 131
, write data human-powered boat 132 , Tsuburi data output boat 133 , and storage area A with access time “14C”
1, a storage area A2 with an access time of 26°C, and a storage area A3 with an access time of 30°C. Memory requests can be accepted every 2 hours, and if read is specified, memory requests are accepted. At the reply timing after the access time of the storage area corresponding to the specified address has elapsed, the data at the specified address is output as reply data to the reply data output port 1.3.
3 to the information processing section 100.

When the memory request sent by the memory request generation unit 110 specifies reading, the access history register +20 receives access history information from the memory request generation unit 110 according to the storage area corresponding to the address specified in the request. , and further outputs access information indicating the reply timing regarding the memory request that has already been sent to the memory request generation unit 110.

As shown in FIG. 2, this access history register 120 is an 8-bit (A
It consists of shift registers from RO to AR7), and the main memory to be accessed is TAm, A3,...
TAm.

If there are m types of storage areas with m types of access times such that fTAI<TAm <...<TA-), for the access times TAm, TAm,..., TAm.

0□=TA-TA2゜D3=TAm-TAm,...
Di=TAm~TA.

Considering (l・2,3...,m), the access history information from the memory request generation unit 110 is the register ARO of the first stage and the register of the stage shifted by one hour from the first stage. 0 input to m-] registers
In this embodiment, the main storage device 130 has three types of storage areas A1. A2. Since it has A3, lm=3 and Di
=TAm-TA3=O Di=TAm-TAm =3(Hl; -26C=4G
Therefore, the registers to which the access history information is input are the first-stage register ARO and the register AR2, which is shifted by 4 times, that is, 2 bits, from the register ARO.
Access history information A from 0 is input and register AR
2 is provided with a gate circuit 121 whose input terminal receives the access information C that is the output of the register ARI and the access history information NB from the memory request generation unit +10. Furthermore, the access information that is input and output to the memory request generation unit 110 is the access information C that is the output of the register AR+ and the access information that is the output of the register Al17.

The memory request generation unit +10 receives memory request instruction information from the information processing unit 100, and further receives write data if the instruction information includes -F specification, and generates a memory request consisting of a request, read/write specification, and address. generate. If this is a memory request or read specification, the reply timing when a newly generated memory request is sent and the memory that has already been sent, taking into account the contents of the access information C9D that is being output from the access history register +20. After confirming that the reply timing of the request does not match, that is, there is no conflict, the memory request is sent to the main memory +30 at the timing when the main memory +30 can accept the next memory request, and at the same time, the memory request is accessed. Access history information A or B is output to the history register 120. Furthermore, when it is recognized that the reply timings will conflict, the sending of the memory request is suspended until it is confirmed that there is no conflict. Furthermore, if the memory request specifies writing, there is no actual data, so the memory request and write data are unconditionally sent to the main storage device 130 at a timing when the memory request can be accepted.

Here, Table 1 shows the memory request generated by the memory request generation unit +10, the access information C and D that are the output of the access history register 120, and the memory request that is output from the memory request generation unit +10. The relationship with the data set in registers ARO and AR2 is shown.

Table 1 shows that after the memory request generation unit 110 generates a memory request at time t and refers to access information C and D that are output from the access history register +20, at time t+
Determination of sending or pending memory request in 2G and access history register + 20 registers ARO, A
Setting data for R2 is shown. If the memory request is specified with δ included (W), the memory request can be sent regardless of the storage area to be accessed and the contents of access information C and D, and the setting data at that time is "0" in register ARO. '', the output of register ARI at time t, ie, the contents of access information C, is sent to register ^R2. To explain the case where the memory request specifies read (R) using the access to storage area A2 as an example, in this case, if the access information IC is "0", the memory request can be sent, and the register at this time A.R.
The setting data for O and AR2 are “0” and “1” respectively.
It is. Furthermore, if the access information C is "1", the sending of the memory request is suspended, and the contents of the register ARO and R2 are "0" and the contents of the register ARI at time t, that is, the contents of the access information C are "1". " is set. Note that r-J in Table 1 is undefined, and is "0" or "1".
This indicates that either of these is acceptable.

Therefore, from the contents of Table 1, access history register 1
The access information C, which is the old output of the register 20, was sent as a memory request for reading to the storage area A3 time ``2C'' ago, and the reply timing for that request is 28C'' after the current time, that is, The main storage device 130 will be able to accept the next memory request from the timing after the time “2C” to the time “26G”.
The access information output from the register ^R7 of the access history register 120 indicates that a memory request specifying readout is made to the storage area A2 at the time "IOC". The reply timing for the request is ``16C'' from the current time, that is, the time ``2G'' when the main storage device 130 will be able to accept the next memory request.
? This indicates that the time is "14C" after the timing of &. Furthermore, the access information indicates that a memory request specifying readout was sent to the storage area A3 at time ``14C''nη, and the reply timing for that request is ``16G'' after the current time, that is, the main storage +30 will be the next It also shows that it is possible to accept a memory request at time 14G'7J from the timing of time 2G=11.

Next, the operation of this embodiment will be explained.

First, in FIG. 3, consider the timing t of the period "2C", and the time t. + h, j3+ j4+ t6. tI
It is assumed that memory request instruction information is issued from the information processing unit 100 at . In addition, the memory request generation unit +10 receives the memory request instruction information.
Table 2 shows the timing of memory request transmission and the contents held in the access history register 120 in correspondence with the timing shown in FIG.

In addition, here is the time. In ii1, the main memory +3
It is assumed that there is no memory request being processed at 0 and that the access history register 120 does not hold any access history f or ffl. Therefore, the contents of the access history register 120 at time t0 are all rOJ.

First, at time t0, the information processing unit 100 receives memory request instruction information M specifying readout for storage area A3 with access time "30C". When sent to the memory request main generator Ifro, the memory request generator! 10 generates a memory request R0 and also sends access information C,
See D. Here, the access information C and D common numbers "
O'', the memory request generation unit 11.0
At the next timing, that is, time t1 after time "2C", the memory request R8 is sent to the main storage device 130, and as shown in Table 1, the access history information A is sent to the register ARO of the access history register 120 as rlJ. Set. Furthermore, the contents of register AR (are shifted to register AR2 at time t).

Since the contents of register ARI are "0", register A
rQJ is set in R2. Reply timing I't for the memory request sent at time t1
As shown in FIG. 4, Do is at time tII+ after one hour "30C", and the data set in the access history register 120 indicates this.

Subsequently, at time t2, memory request instruction information M specifying write to storage area A2 is written as write data WDi.
However, in the case of write specification, there is no rewriting data, so the data is sent out unconditionally at time t3 after the time '°2C'.
Then, the memory request R is sent to the main storage device 130 together with the write data WDi, and writing is performed. At this time, for access history register +20, [OJ is sent to register ARO, and register AR is sent to register AR2.
The content "1" of I at time t2 is respectively set.

Furthermore, at time t, access time ``26C'' is recorded.
i! Memory refresh for read specification for tdA 2]
- When the instruction information M2 is sent, the memory request generation unit 110 generates a memory request R2, and also refers to the access information C and D and determines that both are "0", that is, the reply timing for the memory request R2 is After confirming that there is no conflict with the reply timing of other requests, the memory request R2 is sent to the main storage device 130 at time 11t4. The reply timing RD2 for this memory request R2 is the fourth
As shown in the figure, time t17 occurs after time "26C" from time t4. In addition, the contents of the access history register I20 at time t4 are that the setting data at the time of sending memory request R2 is "0" for register ARO as access history information A in Table 1, and the access history for register 8R2 is "0". Since information B is "1", register A
This means that R2 and AR3 hold "1".

Then, at time t4, memory request instruction information M3 specifying readout for storage area A3 is sent, and at time t5, memory request generation unit +10 generates memory request R3. When making a memory request specifying read for this storage area A3, memory request R3 is
can be sent. As shown in FIG. 4, the reply timing RD3 for this memory request R3 is at time t2° after the time "30C". Furthermore, the setting data to the access history register 120 when sending the memory request R3 is "1" to the register RO as the access history information A, and the contents of the register ARI at time t to the register AR2. be. therefore,
As for the contents of the access history register 120 at time ts, registers ARO, ^R3, and 8R4 are "1".

Subsequently, when the memory request instruction information M4 specifying continuous output for the storage area A1 is sent at time ○, the memory request generation unit 110 generates a memory request R4 and refers to the access information C and D. At time t7, after confirming that there is no conflict in the reply timing.
Sends memory request R4. The reply timing 1104 for this memory reply l' R4 is as follows:
As shown in FIG. 4, it is time t14 after time "14C". Also, the access history register 120 at time t7
The contents of register ^R2, A115 and 8R6 are “1”.
”.

Next, when the memory request instruction information M5 designating reading for the storage area AI is sent at time 0, the memory request generation unit 110 generates a memory request R6 and refers to the access information C and D. At this time, the contents of the access history register 120 are the register ^R3, Al
6 and Al7, that is, the access information is "1". In this case, in Table 1, the sending of memory request R5 to storage area A1 at time t9 is suspended, and the contents of access history register ]20 at time L9 are set to "1" in registers ^R4 and Al7. therefore,
At this time as well, the access information is "1", so the time tl
The sending of memory request R5 at o is also put on hold. Then, at time tlo, access history register again! 20, here, only the contents of register ^R5 are "1", and access information C and D are both "0".
”, it is determined that the reply timings do not conflict, and memory request R5 will be sent at the next time tl+. Access history register 120 at this time
The setting data to register ARO is "0", and register ^R2 is set to time tl (the contents of register All at + r
QJ, access history register 12 at time tll
As for the contents of 0, only the contents of register AR6 are "1". Furthermore, at this time, when the memory request instruction information M6 for the storage area A1 is sent, the memory request generation unit 110 generates the memory request R6 and refers to the access information C and D to ensure that the reply timings do not conflict. Once confirmed, the memory request R6 is sent at time t12. This memory request R6
The reply timing RD6 for
A later time tl'l occurs.

FIG. 5 is a block diagram showing a second embodiment of the present invention.

In this embodiment, the memory request generation unit +10 is equipped with a selector III and receives access information from the access history register 120 via the selector 1117. The main storage device 130 includes a memory request input port 131, a write data input port 132, and a write data output port +33, and has access times TAI, TA2, . -..., T
Am (TAI<TA2<...<TAm) storage areas A1, A2 . ..., Am. The access history register 120 has n stages of registers 8RO and AIII.

..., ^Rn-1, it is a shift register that shifts every "2C", and the third stage register AR
Gate circuits are provided at the input terminals of the registers ARn-1 from the registers ARn-1 at the final stage, and the outputs from the registers at each previous stage or the access history information from the memory request generation unit 110 are input manually. This access history register +20
is the storage area A2. in the main storage device 130 mentioned above.・−,
AIII access time TA2°TA1.・-, T.A.
For m, [1,=TAm-T^21 Di=T^, -TA3゜Dyu=TAm-TA.

Considering (f"2.3.・", m), the access history information is manually input to m-1 registers: the register ARO in the first stage and the register in the stage shifted by D5 hours from the first stage. Ru. This access history information is directly input from the memory request generation unit 110 to the register All0 in the first stage, and is input directly to the register All0 in the first stage from the switching unit 1 provided at the input part of the other registers in the stages subsequent to register ^R2.
22 in accordance with the number m of storage areas in the main storage device 130, and then input from the memory request generation unit 110 to the register of the required stage. Furthermore, the access information output from the access history register 120 to the memory request generation unit 110 is stored in the second stage register ^R.
Memory request generator as output of register after 1! 10 is sent to the selector I11, and the memory request generation unit +10 uses the selector +11 to determine the number m of storage areas.
and the necessary access information according to their access times.

For example, as in the first embodiment described above, the number of storage areas is three, and the access times for these areas are "14C" and "26C".
G”, “30C”, access history register 12
The number of stages for 0 is r30c - 14G =]6CJ, so eight stages are required, and the switching unit 122 is connected to the register A in the third stage.
Switching is performed so that the access history information is manually input to R2. Further, the selector Ill of the memory request generation unit 110 selects the output of the second stage register A old and the output of the eighth stage register AR7 of the access history register +20.

Also, the number of storage areas has been changed to four, A1-A4, and the access times for each are “14C” and “18C” respectively.
, "26G", and "30C", similarly eight stages of registers are required, and the switching unit 122 is the third stage register^.
The memory request generation unit 110 switches so that the access history information is input to R2 and the seventh register AR6.
The selector 111 of the access history register 120
Select the output from the second stage A old, the sixth stage register ^R5, and the eighth stage register A1 (7).

Then, storage area A2. A3. When a memory request with read specification is sent to A4, the access history information for each memory request is sent to the register AR6 in the seventh stage of the access history register 120 in the case of storage area A2.
3, to the third stage register 8R4, and also to the storage area A4.
In the case of , the signals are respectively input to the first stage register ARO. In this case, selector 1. of the memory request generation unit 110. The output of register ARj of the access history register 120 selected by II is access time "3".
A memory request specifying readout was sent to the storage area A4 of "0C" a time "2G" ago, and after a time "28C" from the current time, that is, the next time when the main storage device 130 can accept a memory request. This indicates that the reply timing is a time "26C" after the timing "20" later. Similarly, the output of register 8F (5) indicates that a memory request with a read specification for storage area A4 can be easily executed at a time of "IOC", and an access time of "2".
A memory request specifying readout was sent to the storage area A3 of 6C before time 6C, and the timing is 20 after which the main storage device 130 can accept the next memory request. This indicates that the reply timing is 18 minutes after the time. Also,
The output of register 8R7 is the time “1” for storage area A4.
4C'' plane or for storage area A3.
A memory request specifying readout was sent to the storage area A2 with an access time of 18G before or at a time of −2C, and in either case, the main storage device 1
30 can accept memory requests “
This indicates that the reply timing is a time “14C” after the timing after “2C”. Therefore,
The output of the register ^R1 is the storage area A3, the output of the register AR5 is the storage area A2, and the output of the register ^R7 is the storage area A1.The reply timing for memory requests to each storage area is based on the memory request that has already been sent. This indicates the possibility of a conflict with the related reply timing.

In this way, according to the present embodiment, even if there is a change in the number of storage areas in the main storage device 130 or the access time thereof, the switching unit 122 of the access history register 120 and the selector 11 of the memory request generation unit +10
This can be handled by operating 1.

FIG. 6 is a block diagram of a third embodiment of the present invention.

In this embodiment, the memory request ID detection unit 14 is provided between the memory request generation unit +10 and the access history information.
0, and the main memory +30 is the access time.
It has a storage area A1 of 14G'' and a storage area A3 of access time 26C and storage area A3 of access time 30C1. is generated, and after confirming that the reply timings do not conflict by referring to ID information A, B, and C output from the memory request ID detection unit 140, the memory request is sent.
Bit-encoded access history information is output to the access history register 120. Access history register 12
As shown in FIG. 7, 0 is a shift register consisting of 8 stages of registers (^RO-AR7) each having 2 bits, and its shift timing is time "2G". Furthermore, the access history information from the memory request generation unit +10 is stored in the first stage register RO, and the outputs of the register ^R1, register AR5, and register AR7 are sent to the memory request ID detection unit 140 as access information A, B, and C, respectively. Sent out. Memory request ID
The detection unit 140 receives the access information A, B, and C from the access history register 120, and detects the access information from the access information A, B, and C from the access history register 120.

It detects the reply timing for the read-designated memory request sent by the memory request generation unit 110, and outputs ID information A, B, and C indicating the reply timing to the memory request generation unit 1it).

Here, Table 3 shows access history information and ID information A, B, C.
shows the relationship between

In Table 3, the memory request generation unit 110 generates a memory request every 3 times, and the ID information A, B is the output of the memory request generation unit 10 detection unit +40.

It shows the determination of whether the memory request is to be sent or put on hold at time t+2C, one after referring to C, and the access history information that is the setting data to the access history register 120. First, if the memory request is Yoshikomi specification (W), there is no transfer data from the main storage device 130, so the memory request can be sent regardless of the contents of ID information A, B, and C, and the access history information at that time is It is roOJ. Next, in the case of read R) designation, for example, if the storage area to be accessed is assumed to be A2, if the content of ID information A is "0", a memory request is made regardless of ID-1# information B and C. If it can be sent and the access history information at that time is "01", and if the content of TD information A is rIJ, the sending of the memory request is suspended regardless of IO information B and C, and the access history information at that time is "01". 00'', and the ``-'' in Table 5 indicates indeterminate, and ``0''
, "1" is acceptable. therefore.

The rD information A indicates whether or not there is a conflict with the reply timing regarding an already sent memory request when sending a memory request with read specification to the storage area A2. In this case, for ID information A, a memory request specifying readout is sent to vUA3 at time b, and the reply timing is 28G after time t, that is, when the main recording device 130 next receives the memory request. This indicates that the timing will be ``26C'' after the time ``2G'' when it is possible to do so. Furthermore, ID information B and C indicate whether or not there is a conflict with the reply timing regarding an already sent memory request when sending a memory request specifying readout to the storage area AI. In this case, ID information B is the time “IOC
A memory request specifying readout was sent to the storage area A2 before, that is, at time t-10C, and the nobli timing was a time "16c" after time t.

In other words, this indicates that the timing will be "14C" after the time "2C" when the main memory bag ff1130 can accept the next memory request, and the ID+
The IIf report C indicates that a memory request specifying readout was sent to the storage area A3 a time "14G" ago, and the reply timing will similarly be after a time "14c".

In this way, in this embodiment, the memory request generation unit 11
The access history information output as 0 or 62 bits is held for a certain period of time in the access history register 120, and the access history information is similarly output as 2 bits.
Bit access 44 is output as ff1 to the memory request ID detection unit 140, and the access information is decoded by the memory request ID detection unit 140 to create an IDf indicating the reply timing related to the memory request for completion.
This is sent to the memory request generation unit 110 as an f1 report.

FIG. 8 is a block diagram of a fourth embodiment of the present invention.

In this embodiment, the memory request generation section 210 includes a selector I11, and receives the ID information from the memory request ID detection section 140 via the selector III. The access history register 120 is an 8-stage shift register with 2 bits each, as in the third embodiment described above, and the output of R7 to the registers except the first stage register ARO is used as memory request information as access information. It is connected to the ID detection section 140. Further, the memory request ID detection unit 140 outputs the output corresponding to each piece of access information from the access history register 120.
It is connected to the selector 111 of the memory request generation unit 110 as D information. Memory request generation unit 11
0, the selector I11 is controlled to select necessary ID information according to the access time of the storage area provided in the main storage device 130. For example, as mentioned above, the storage areas are AI, A2. If the access times are 14G", 126G" and "30G" for three A3, respectively, register ARI of the access history register 120, Aft5.
Select ID information corresponding to the output of AI7.

Also, the access time of the storage area is changed, and the storage area A
l, A2. Each A3 is “14G”.

In the case of "20G" and "30C", the reply timing can be predicted by selecting ID information corresponding to the outputs of registers AR2, AI4, and AI7 of the access history register 120. In this way, according to the present embodiment, it is possible to cope with changes in the access time of the storage area included in the main storage device 130.

FIG. 9 is a block diagram of a fifth embodiment of the present invention.

In this embodiment, the memory request ID detection section 140 includes a selector 141. In this case as well, the outputs of registers A1 to ^R7 from the access history register 120 are connected to the memory request ID detection unit 140, and the memory request ID detection unit 140 controls the selector l to access the storage area. Select access information according to the time. Furthermore, in this embodiment, the storage area is AI.

A2. Since the number is A3, three pieces of ID information are output from the memory request ID detection unit +40 to the memory request generation unit +10.

Here, storage areas AI, A2. If the access time of A3 is "+4(:", "26C", "30C"), the access history register +20 is set by the selector 141.
The outputs of registers ARI, AI5 and AI7 are selected. Furthermore, if the access times are changed to "14C", "20C", and "30G", the outputs of registers AR2, 8R4, and AI7 will be selected.

Therefore, in this embodiment as well, changes in the access time of the storage area can be handled in the same way as when a selector is provided in the memory request generation unit +10.

(Effects of the Invention) As explained above, when the memory request generation unit sends a memory request to a storage device, the access history is held in the access history register for a certain period of time, so that the next memory request can be sent. When doing so, the memory request can be sent to the storage device after checking the access history in the register to confirm that there is no conflict in reply timing, and without making any major changes to conventional access control. By simply adding a very small piece of hardware, such as a memory request generator with an access history register and judgment function, you can create a pipeline-controlled storage device that has traditionally been considered to be the most automatic, efficient, and cost-effective. It is possible to adopt a hierarchical structure regarding the access time in the storage device, and furthermore, even if the access time of the storage device is changed, there is an effect that it can be handled without significantly changing the hardware.

4. 17 on the IA side! FF vehicle description FIG. 1 is a block diagram showing the information processing device of the present invention, FIG. 2 is a block diagram showing the configuration of the access history register +20, and FIG. A timing chart 'fJ4 showing an example of the timing of outputting the instruction information shows the output timing of the memory request of the memory request generator 110 and the reply timing of the main storage device 130 with respect to the output timing of the memory request instruction information of FIG. 3. The timing charts shown in FIGS. 5 to 9 are block diagrams showing other embodiments of the present invention.

100...-+l information processing unit, +10... memory request generation unit, +11. ,+4
DESCRIPTION OF SYMBOLS 1...Selector, 120...Access history register, 121...Gate circuit, 122...Switching unit, 130...Main storage device 6, +31...Memory request manual boat, 132...
・Light data human powered boat, 133...Reply data output capo-1-.

+40...Memory request 10 detection unit.

Claims (1)

[Claims] 1. If there are multiple storage areas with different access times and the external memory request is to read data, a reply after the access time of the storage area that stores the specified data has elapsed. In an information processing device that includes a storage device that outputs the data as reply data at a timing, and performs pipeline control on the storage device, the storage device includes TA_1, TA_2, . . . , TA_
It is equipped with m types of storage areas with an access time of m (TA_1<TA_2<...<TA_m), and when it is necessary to access the storage device, it sends memory request instruction information including read/write specification and address specification. In addition, in the case of write specification, the memory request is composed of an information processing unit that adds write data and sends it out, and a shift register that performs a shift operation at fixed time intervals, and when a memory request with read specification is sent, the request From the first stage of the shift register, the access history information indicating the reply timing for the storage device, TA_1,
For TA_2..., TA_m, D_2=TA_m
-TA_2,D_3=TA_m-TA_3,...,D
D_i (i=2, 3,
..., m) The access history register held in m-1 registers shifted by time, the memory request instruction information sent by the information processing unit, and the write data at the time of writing are received, and the read/write designation is made. Generates a memory request that includes address specification; if the request is a write specification, the write data is sent to the storage device along with the memory request; if the request is a read specification, the access time of the storage area related to the address specified in the request is and the access history information related to already sent memory requests held in the access history register, determine whether the reply timing when the generated memory request is sent matches the reply timing related to the already sent requests. If it is determined that they do not match, the request is sent to the storage device, and access history information related to the request is registered in the access history register, and if it is determined that they match, the memory request is not sent. An information processing device comprising: a memory request generation unit that suspends and waits until it is determined that there is no match. 2. If you have multiple storage areas with different access times and the external memory request is to read data, the specified data will be read at the reply timing after the access time of the storage area that stores the specified data has elapsed. In an information processing device that is equipped with a storage device that outputs reply data and that controls the storage device in a pipeline, when access to the storage device is required, it sends out memory request instruction information including read/write designation and address designation, and further It consists of an information processing unit that adds write data and sends it out in the case of a write specification, and a shift register that performs a shift operation at regular intervals, and when a memory request with a read specification is sent, it indicates the reply timing for the request. An access history register that holds multiple bits of access history information, and a memory request that decodes the multiple bits of access history information held by the access history register and outputs ID information that indicates reply timing for already sent memory requests. Upon receiving the memory request instruction information and write data sent by the ID detection unit and the information processing unit, generates a memory request including read/write designation and address designation, and if the request is write designation, a memory request is generated. At the same time, the write data is sent to the storage device, and if read is specified, the access time of the storage area related to the address specified in the request and the ID information related to the already sent memory request output by the ID detection unit. , it is determined whether the reply timing when the generated memory request is sent matches the reply timing related to the already sent request, and if it is determined that they do not match, the request is sent to the storage device. It also has a memory request generation unit that registers multiple bits of access history information related to the request in an access history register, and if it is determined that they match, it suspends sending the memory request and waits until it is determined that they do not match. An information processing device characterized by: