JPH02111996A - Raster arithmetic processor - Google Patents

Abstract

PURPOSE:To eliminate the need for a separate memory such as main memory by applying the data of planes to desired circuits via a ring shifter and storing the results of computation similarly into only the corresponding planes. CONSTITUTION:A frame buffer memory FBM 101 consisting of the plural planes 1l to 1o, each of which stores the data for raster display, and a raster operating part ROP 102 consisting of plural arithmetic circuits 2l to 2o corresponding to the respective planes 1l to 1o are provided. The ring shifter RSF 103 is provided between the two parts 101 and 102 and the data of the planes 1l to 1o are applied to the desired arithmetic circuits 2l to 2o; in addition, the results of the computation are stored only into the corresponding planes. The need for the separate memory such as main memory is eliminated in this way and the time for arithmetic processing is shortened.

Description

[Detailed Description of the Invention] [Field of Application in the United States and the United Kingdom] When image data is displayed in a raster format in a workstation or the like, the present invention performs arithmetic processing using a plurality of raster display data. The present invention relates to a raster arithmetic processing device that displays raster data based on the results of this arithmetic operation.

[Conventional technology]

In such cases, conventionally, the data for raster display, which is the basis of the calculation, is temporarily stored in the main memory, etc., and the program is executed using this data and data in the 7-frame buffer memory (hereinafter referred to as FBM). The system performs arithmetic processing, stores the result in F B ki again, and uses this content to display a raster according to the image data.

[Problem to be solved by the invention]

However, when using the above-mentioned method, a separate memory such as main memory is required, and data access to this is required.
Since these processes and arithmetic operations are executed by software or firmware, there is a drawback that the time required increases.

[Means to solve the problem]

In order to solve the above-mentioned problems, the present invention is configured by the following means.

That is, there is an FBM consisting of a plurality of planes, each of which stores data for shifter display, and a plurality of FBMs that are provided corresponding to each plane and that perform calculations based on the data in the planes and store the calculation results in the corresponding planes. A raster arithmetic unit consisting of an arithmetic circuit, and a raster arithmetic unit that is interposed between the FBM and the raster arithmetic unit, arbitrarily shifts plane data and arithmetic results, supplies the plane data to a desired arithmetic circuit, and transfers the arithmetic results to a corresponding plane. It is equipped with a ring sick to apply to the button, and a prohibition circuit that prohibits writing to the button and other planes when storing the calculation result in the corresponding plane.

[For production]

Therefore, the data of the plane is given to the desired arithmetic circuit via ringsick, and the arithmetic result is similarly stored in the corresponding plane, and at this time, other planes become write-protected. , content updates are prevented and valid data is prevented from disappearing.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to block diagrams showing embodiments.

In the figure, FBMlol and a raster operation unit (hereinafter referred to as ROP) 102 are provided, and a bidirectional ring shifter (hereinafter referred to as R8F) 103 is provided between them. Divided into multiple areas,
This constitutes planes 10 to 1t, each of which stores data for shifter display, and each plane is provided with a write enable terminal WE. A write signal W and a write inhibit signal WINH are applied, and in response to the write inhibit signal WINH from a control unit such as a processor (not shown), the corresponding plane is set to a write inhibit state.

In addition, the ROP 102 is connected to each plane 1 of the FBM 101.
o to 1t and corresponding arithmetic circuits 20 to 2tK, and one of the arithmetic circuits performs arithmetic processing based on the data of at least two planes in each of the branes 1G to 1L, and this calculation The results are stored in the corresponding plane.

However, when storing the calculation result in the corresponding plane, the write signal W is applied to the corresponding plane and the write inhibit signal WINH is also applied, whereas the write inhibit signal WINII is applied to the other planes. is given, only the content of the corresponding plane is updated, and valid data in other planes is preserved.

On the other hand, the R8F103 is configured with multiple stages of shift registers, etc., and is supplied with a control signal OS indicating the υ shift direction and the number of shifts from the same control unit as described above. ~1 is shifted and given to the desired arithmetic circuit, and the arithmetic circuit 2
The calculation results from 0 to 2t are given to the corresponding planes from 1° to 1t.

Therefore, when performing a raster operation using the data of plane 1n as source data and the data of plane 1m as destination data, and storing this result in plane 1, first set the shift status of R8F103 to "0".
Then, the data of the plane 1n is given to the calculation circuit 2n, R3F103 is shifted upward by rm-nJ, and after this, the data of the plane 1m is given to the calculation circuit 2n, and the shift status of R8F 103 is again It is sufficient to return it to rOJ, and in this state, send out the calculation result of the calculation circuit 2n and store it in the plane 1n.

In this case, the write inhibit signal WINI is not given only to the plane 1n, and the same signal W is not given to the other planes.
Give INH.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, an FBM is provided which is redirected from a plurality of planes, each of which stores data for shifter display, and an ROP consisting of a plurality of arithmetic circuits corresponding to each plane. 1. An R8F is provided between the two, thereby giving the data of the plane to the desired arithmetic circuit, and giving the arithmetic result to the corresponding brane, and transmitting the arithmetic result based on the data of the plane only to the corresponding brane. This eliminates the need to provide a separate memory such as a main memory in addition to the FBM, and since raster clearing processing is performed by an arithmetic circuit, these processing speeds up and the shift table Significant force effect can be obtained in arithmetic processing of private data -0

[Brief explanation of drawings]

The figure is a block diagram showing an embodiment of the present invention. 1o~1t...Plain, 20~2t...
Arithmetic circuit, 101... Frame buffer/Mori,
102...Raster operation unit, 103...Fist ring shifter, 104...AND gate, W...Write signal, WINH...Write stop signal, DS...
··Control signal. Patent applicant Nippon'4Kishiki Company

Claims (1)

[Claims] A frame buffer memory consisting of a plurality of planes each storing data for raster display, and a frame buffer memory provided corresponding to each plane to perform calculations based on the data in the planes and store the calculation results in the corresponding planes. a raster arithmetic unit consisting of a plurality of arithmetic circuits, and a raster arithmetic unit that is interposed between the frame buffer memory and the raster arithmetic unit, and arbitrarily shifts the data and arithmetic results of the plane and provides the data of the plane to a desired arithmetic circuit. and a ring shifter that provides the calculation result to the corresponding plane;
A raster arithmetic processing device comprising: a prohibition circuit that prohibits writing to other planes when storing the arithmetic results in a corresponding plane.