JPH0198047A - Interruption processing system - Google Patents

Abstract

PURPOSE:To increase the success frequency of reinterruptions and to shorten the information processing time by securing mutual connections among an arithmetic processor, a main memory and plural input/output controllers via a system of an information processor and adding an information means, a rewrite permission means and a timer means to each input/output controller. CONSTITUTION:An arithmetic processor 2, a main memory 3 and input/output controllers 41-43 are connected to a system bus 1 of an interruption processing system for exchange of data. Then the controllers 41-43 perform the transfer of data to the memory 3 based on command codes given from the processor 2. The end report on the transfer of data is given to the processor 2 via the information means of controllers 41-43. Then a reinterruption is permitted by a permission means with a reinterruption command code in case an interruption is rejected and held. The reinterruption time is set at a part of the reinterruption command code by a timer means and the reinterruption is permitted at the set time.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a processing method of an information processing device, and particularly relates to an interrupt method from a peripheral control device to an arithmetic processing device.

(Prior Art) When software called multiple tasks are executed simultaneously, in an information processing device that operates a peripheral control device used by each of those tasks, interrupts are required to operate the device efficiently. concepts are introduced. A task that has issued an operation instruction to the input/output control device remains in a waiting state until the operation is completed, so that execution can be entrusted to other tasks. Each of these tasks is assigned a level of precision to be executed, and the higher the level of priority, the higher the right to transition from the wait state to the execution state.

In other words, a task with a low priority level does not enter the execution state even if there is a report that the human output control device has completed the operation because a higher level task takes priority. The arithmetic processing unit compares the interrupt instruction code with its own execution level, and if the execution level has a higher priority, returns interrupt rejection to the input/output control unit. By rejecting this interrupt, the interrupt of the input/output control device is suspended.

When a processing unit finishes execution at a higher level and transitions to a lower level, it issues a re-interrupt enable command code in the form of a simultaneous notification to all input/output control units connected to the bus. , the I/O controller can be re-interrupted. When an arithmetic processing unit is executing multiple tasks simultaneously, such level changes always occur, and each time a re-interrupt occurs on the bus.

(Problems to be Solved by the Invention) In the conventional multi-task processing system described above in which a plurality of tasks are executed simultaneously, there are also a plurality of resources. Therefore, a plurality of peripheral devices, which are these plural resources, operate simultaneously.

In the input/output control device that controls these peripheral devices,
The completion of the operation of each peripheral device is notified to the arithmetic processing unit by an interrupt. If the running level of the % arithmetic processing unit has higher priority than the value of the interrupt level, 1 interrupt will be in a pending state. If a re-interrupt permission is issued due to a change in the running level of the processing unit, the I/O control unit will re-interrupt, but the time from receiving permission to issuing an interrupt on the bus depends on the hardware of the I/O control unit. It depends.

For example, between a resource given a high-priority interrupt level and a low-priority resource, the time from receiving re-interrupt permission to re-interrupting is reversed, and the low-priority resource is There is a possibility of early re-interruption. Such a case is not desirable for the system. In other words, after the processing unit receives a re-interrupt with a low priority,
Furthermore, there is the problem that tasks must be switched additionally when processing a high-priority interrupt.

An object of the present invention is to connect an arithmetic processing unit, a main storage device, and a plurality of input/output control devices to each other through a system bus, and to issue an interrupt command from the input/output control device to the arithmetic processing unit by reporting the completion of an operation. When this happens, the processing unit should be able to issue a re-interrupt permission command to the input/output control device, and some fields in the re-interrupt permission command will be set until the input/output control device receives re-interrupt permission and then issues the re-interrupt fee. The object of the present invention is to provide a next-side processing method that eliminates the above-mentioned drawbacks by specifying the time of 100% by a timer value, and eliminates the need for extra task switching.

(Means for Solving All Problems) The interrupt processing method according to the present invention is an information processing device that interconnects an arithmetic processing unit, a main storage device, a plurality of input/output control devices, and an entire system bus to exchange data. It is in. In the above configuration, each input/output control device is configured to include a notification means, a re-interrupt permission means, and a timer means.

The notification means transfers data to and from the main storage device according to a command code from the arithmetic processing unit.

A notification is sent to the arithmetic processing unit using an interrupt command code as a data transfer completion report.

The re-interrupt permission means is for permitting re-interruption using a re-interrupt command code when an interrupt has been previously rejected and the interrupt is in a pending state.

The timer means is for applying to processing a timer value that is set in a part of the re-interrupt command code and defines the time from when the re-interrupt is permitted until the re-interrupt is executed.

(Example) Next, one embodiment of the present invention will be explained with reference to all the drawings.

FIG. 1 is a block diagram showing an embodiment of an interrupt processing method according to the present invention. In FIG. 1, 1 is a system bus, 2 is an arithmetic processing unit 3, a main storage device, and 41 to 43 are input/output control devices, respectively.

In FIG. 1, each of the input/output control devices 41 to 43 has a notification means and a re-interrupt permission means.

and timer means. The notification means reports the completion of data transfer, and the re-interrupt permission means allows re-interrupt when it is issued to the input/output control device in an interrupt pending state. The timer means defines the time from acceptance of permission for re-interruption to execution of re-interruption, and automatically switches the priority of the interrupt based on the timer value.

In FIG. 1, an arithmetic processing unit [2, a main storage device 3, and an input/output control device 4] are connected to a system bus 1.
The L arithmetic processing unit R2 reads and executes software stored in the main storage device 3, that is, a program, and performs the processing intended by the program.

The program includes instructions for operating the input/output control devices 41 to 43. The command is input/output control device 4
This is executed by issuing an operation command code for operating peripheral devices (not shown) under the commands 1 to 43 and instructing them to exchange data.

When the data exchange, that is, the data transfer is completed, the input/output control devices 41 to 43 issue an interrupt command code to the arithmetic processing unit R2 as a report of the completion of the operation. If the execution level of arithmetic processing fci2 is input/output control device [41 to 43
When the interrupt level is higher than the interrupt level given to t2, the interrupt command code is rejected by the arithmetic processing unit t2, and the interrupt is placed in a pending state. When the level changes due to program execution in the suspended state, a re-interrupt permission command code is issued from the arithmetic processing unit [2]. The input/output control devices 41 to 43 in the pending state receive the above command and initiate a re-interruption to the arithmetic processing device 2.

FIG. 2 ((translation) to (C) are explanatory diagrams showing % type command codes.

The operation command code shown in FIG. 2(a) is
includes commands that instruct the input/output control devices 41 to 43 to operate. Destination ID, destination ID', and source IDFi, which are identification numbers assigned to devices on system bus l, that is, addresses. The destination ID' is an ID indicating a device connected under the input/output control devices 41 to 43, and has no direct relationship on the system path 1. The source ID is the arithmetic processing unit 2 that issued the above operation command code.
The ID will be entered.

The interrupt command code shown in FIG. 2(b) is a code for interrupting the arithmetic processing device 2 from the input/output control devices 41 to 43. Of course, the same one is used when re-interrupting. The interrupt level is the level to be reported at the end of the operation, and the arithmetic processing unit 2 compares this level with the execution level of the arithmetic processing unit 2, and approves the rejection te.

The re-interrupt permission command code shown in M2 diagram (C) is:

It is sent to prompt the input/output control devices 41 to 43 that have rejected the interrupt to interrupt again. The destination ID and ID' of this code are meaningless. The timer value indicates the time it takes for the input/output control devices 41 to 43 to receive the re-interruption permission and issue the re-interruption code to the system bus 1. here.

Rather than instructing the same timer value to the input/output control devices 41 to 43 at all levels, it is effective to apply it to a level with a lower priority than a predetermined interrupt level. If specified for all levels, especially when going from a low level to a high level, a minimum execution time of the switched new driving level is guaranteed.

If the actual running time of this task is very short, it is possible to finish running at the same level without having to switch to another level. Additionally, all logically possible levels are divided into at least two groups, and timer provisions are not applied to higher priority levels, and timer values are applied only to lower priority levels below 1/2 level. If applied, it is possible to increase the number of successful re-interrupts of the nine output control device given a high interrupt level.

(Effects of the Invention) As explained above, the present invention connects an arithmetic processing unit, a main storage device, and a plurality of input/output control devices to each other through a system bus, and connects the input/output control device to the arithmetic processing unit. When an interrupt command is sent by reporting the completion of an operation, the processing unit can issue a command to re-interrupt the input/output control device, and some fields of the re-interrupt permission command allow the input/output control device to enable re-interruption. By defining the time from when a task is received to when a re-interrupt is performed using the t-timer value, there is an effect that there is no need to switch to another level when the actual running time of a task is extremely short.

Therefore, in order to equalize the chance of re-interrupting for all I/O controllers, all logically possible levels are divided into at least two groups, and timer provisions are applied at higher priority levels. No, 1/! By applying the full timer value to lower priority levels below the level, the number of successful re-interrupts of the nine-person output control device can be increased by giving a higher interrupt level, and the information processing time can be shortened. This also has the effect of improving reliability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the interrupt processing method according to the present invention. FIGS. 2(a) to 2(c) are explanatory diagrams showing various instruction codes. 1...System bus 2...Arithmetic processing unit 3...
・Main storage devices 41 to 43...I/O control device

Claims (1)

[Claims] An interrupt processing method for an information processing device in which an arithmetic processing unit, a main storage device, and a plurality of input/output control devices are interconnected by a system bus to exchange data, wherein each of the input/output control devices is Transferring data to and from the main storage device according to a command code from an arithmetic processing unit;
Notifying means for notifying the arithmetic processing unit with an interrupt command code as a completion report of the data transfer, and a re-interrupting unit using a re-interrupt command code when the interrupt has been previously rejected and is in an interrupt pending state. To apply to processing a re-interrupt permission means for permitting the re-interrupt, and a timer value that defines the time from receiving the re-interrupt permission to executing the re-interrupt, which is set as a part of the re-interrupt command code. 1. An interrupt processing method characterized by comprising: a timer means.