JPH0196943A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH0196943A JPH0196943A JP25499287A JP25499287A JPH0196943A JP H0196943 A JPH0196943 A JP H0196943A JP 25499287 A JP25499287 A JP 25499287A JP 25499287 A JP25499287 A JP 25499287A JP H0196943 A JPH0196943 A JP H0196943A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit chip
- resin film
- capacitor
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 239000011347 resin Substances 0.000 claims abstract description 28
- 229920005989 resin Polymers 0.000 claims abstract description 28
- 239000003990 capacitor Substances 0.000 claims abstract description 27
- 230000002093 peripheral effect Effects 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 4
- 239000004642 Polyimide Substances 0.000 abstract description 2
- 238000005530 etching Methods 0.000 abstract description 2
- 238000001259 photo etching Methods 0.000 abstract description 2
- 229920001721 polyimide Polymers 0.000 abstract description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 abstract 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 8
- 230000000694 effects Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 210000002105 tongue Anatomy 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 229910018885 Pt—Au Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000007888 film coating Substances 0.000 description 1
- 238000009501 film coating Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的］ −
（産業上の利用分野）
本発明は半導体集積回路装置に係り、特にＧａＡｓ集積
回路に代表される高速動作の集積回路の実装構造に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] - (Industrial Application Field) The present invention relates to a semiconductor integrated circuit device, and particularly to a mounting structure of a high-speed operation integrated circuit typified by a GaAs integrated circuit.
（従来の技術）
高速論理動作を行う半導体集積回路としてＧａＡｓ集積
回路が知られている。近年、Ｇ ａ Ａ ｓ Ｍ Ｅ
Ｓ Ｆ Ｅ Ｔを集積して、スイッチング速度１００
ｐ ｓｅｅ程度の高速動作を実現したものが得られてい
る。しかしこの様な高速動作を行う集積回路チップを従
来のパッケージに搭載した場合、チップ単体で得られる
高速性能が引出されないという問題がある。その性能劣
化の原因の一つとして、集積回路チップ内の論理素子が
高速スイッチング動作を行なう際に電源線に急峻な過渡
電流が流れ、インダクタンス成分の影響で電源電位の低
下をもたらすことが挙げられる。電源線のインダクタン
スは、パッケージ内の配線部のインダクタンス分と、集
積回路チップと配線部を接続するボンディング・ワイヤ
のインダクタンス分がある。ボンディング・ワイヤのイ
ンダクタンスは通常、１朋当り０．５〜１ｎＨという値
であり、ワイヤ長を１〜２ｍ１４とすると１〜２ｎＨと
なる。パッケージ内電源配線のインダクタンス成分を合
せて仮に、２ｎＨとし、スイッチング時間１００ ｐ
ｓｅｅの間に流れる電流を１０ｍＡとすると、このとき
電源電圧降下は、Ｌ−ｄｉ／ｄｔにより計算して約２０
０ｍＶとなる。(Prior Art) GaAs integrated circuits are known as semiconductor integrated circuits that perform high-speed logic operations. In recent years, Ga As M E
By integrating SFET, the switching speed is 100
A device that achieves high-speed operation on the order of psee has been obtained. However, when such an integrated circuit chip that operates at high speed is mounted in a conventional package, there is a problem that the high-speed performance obtained by the chip alone cannot be brought out. One of the causes of performance deterioration is that when the logic elements in the integrated circuit chip perform high-speed switching operations, a sharp transient current flows through the power supply line, causing a drop in the power supply potential due to the influence of the inductance component. . The inductance of the power supply line includes the inductance of the wiring section within the package and the inductance of the bonding wire that connects the integrated circuit chip and the wiring section. The inductance of the bonding wire is usually 0.5 to 1 nH per wire, and when the wire length is 1 to 2 m14, it is 1 to 2 nH. Let's assume that the total inductance component of the power supply wiring inside the package is 2nH, and the switching time is 100p.
If the current flowing during see is 10mA, then the power supply voltage drop is approximately 20mA calculated by L-di/dt.
It becomes 0mV.
Ｇ ａ Ａ ｓ Ｍ Ｅ Ｓ Ｆ Ｅ Ｔを用いた論理
回路はノイズマージンが小さいため、この程度の電源変
動でも動作が不安定になる。Since a logic circuit using GaAs MESFET has a small noise margin, even a power supply fluctuation of this magnitude makes the operation unstable.
従来一般にこの様な電源電圧変動に対しては、パッケー
ジ外部に電源線と接地線間にデカップリング用コンデン
サを設けることが行われている。Conventionally, in order to cope with such power supply voltage fluctuations, a decoupling capacitor has been generally provided between the power supply line and the ground line outside the package.
しかし、ＧａＡｓ論理回路その他の高速集積回路では、
パッケージ外部にコンデンサを接続しても、パッケージ
内部の電源線の持つインダクタンスの影響を充分補償す
ることができない。However, in GaAs logic circuits and other high-speed integrated circuits,
Even if a capacitor is connected outside the package, it is not possible to sufficiently compensate for the influence of the inductance of the power supply line inside the package.
（発明が解決しようとする問題点）
以上のように高速動作を行なう集積回路では、電源線の
インダクタンスによりその本来持っている高速性を充分
に発揮させることができない、という問題があった。(Problems to be Solved by the Invention) As described above, integrated circuits that operate at high speeds have a problem in that they cannot fully utilize their inherent high speeds due to the inductance of the power supply line.
本発明はこの様な問題を解決した半導体集積回路装置を
提供することを目的とする。An object of the present invention is to provide a semiconductor integrated circuit device that solves these problems.
［発明の構成コ
（問題点を解決するための手段）
本発明では、半導体集積回路チップの実装にＴ Ａ Ｂ
（Ｔ ａｐｅ Ａ ｕｔｏｍａｔｅｄ Ｂ ｏｎ
ｄｉｎｇ）方式を採用する。ＴＡＢ基板は、テープ状の
樹脂フィルムに集積回路チップの載置部と、集積回路チ
ップと接続される金属箔からなるリード配線が形成され
たものである。この実装方式は、フィルムキャリア等と
も称される。この様なＴＡＢ方式の集積回路構造におい
て本発明は、樹脂フィルム上に櫛形電極によるデカップ
リング用コンデンサを搭載したことを特徴とする。[Configuration of the Invention (Means for Solving Problems) In the present invention, T A B is used for mounting a semiconductor integrated circuit chip.
(Tape Automated B on
ding) method will be adopted. The TAB substrate is a tape-shaped resin film on which a mounting portion for an integrated circuit chip and lead wiring made of metal foil to be connected to the integrated circuit chip are formed. This mounting method is also called a film carrier or the like. In such a TAB type integrated circuit structure, the present invention is characterized in that a decoupling capacitor using a comb-shaped electrode is mounted on a resin film.
（作用）
この様にＴＡＢ基板（フィルムキャリア）を用いれば、
基板上のリード配線と集積回路チップ間の接続は突起電
極により行われるためにインダクタンス成分が小さくな
り、またデカップリング用コンデンサを集積回路チップ
の近傍に配置することにって、樹脂フィルム上のリード
配線のインダクタンス成分の影響も非常に少なくするこ
とができる。(Function) If the TAB substrate (film carrier) is used in this way,
The connection between the lead wires on the board and the integrated circuit chip is made by protruding electrodes, which reduces the inductance component, and by placing the decoupling capacitor near the integrated circuit chip, the lead wires on the resin film can be easily connected. The influence of the inductance component of the wiring can also be greatly reduced.
（実施例） 以下、本発明の詳細な説明する。(Example) The present invention will be explained in detail below.
第１図（ａ）（ｂ）は、本発明の一実 施例のＧａＡｓ集積回路実装構造を示す平面図である。Figures 1(a) and 1(b) are examples of the present invention. FIG. 2 is a plan view showing an example GaAs integrated circuit mounting structure.
ＧａＡｓ集積回路は例えば、ＧａＡｓＭＥＳＦＥＴを用
いた、スイッチング速度１０ ｐ ｓｅｅ以下の高速動
作をおこなうマルチプレクサである。ＴＡＢ基板は、ポ
リイミド或いはガラスエポキシ等の樹脂フィルム１に、
フォト・エツチングを利用してリード配線を形成したも
のである。通常長尺のテープ状フィルムに繰返し配線パ
ターンが形成されており、これに集積回路チップが次々
に搭載される。第１図ではその１チツプ搭載部とその周
辺のリード配線部を示している。The GaAs integrated circuit is, for example, a multiplexer that uses GaAs MESFETs and operates at high speed with a switching speed of 10 psee or less. The TAB substrate is made of a resin film 1 made of polyimide or glass epoxy, etc.
Lead wiring is formed using photo-etching. Usually, a long tape-like film has a repeated wiring pattern formed thereon, and integrated circuit chips are mounted one after another on this. FIG. 1 shows the one-chip mounting area and the lead wiring area around it.
配線は、最終的に集積回路としてキャリアから切離され
る領域（−点鎖線で示す）内部のインナー・リード部３
、外部のアウター・リード部及び測定用パッド部５から
なる。インナー・リード部３の先端の集積回路チップ載
置部に、櫛形電極６１゜６□を噛合わせたパターンのデ
カップリング用コンデンサが構成されている。電極６．
．６２の一方は電源電位に、他方は接地電位に接続され
る。The wiring is connected to the inner lead portion 3 inside the area (indicated by the dashed line) which will be ultimately separated from the carrier as an integrated circuit.
, an external outer lead section, and a measurement pad section 5. A decoupling capacitor having a pattern of interlocking comb-shaped electrodes 61°6□ is formed on the integrated circuit chip mounting portion at the tip of the inner lead portion 3. Electrode 6.
．． One side of 62 is connected to the power supply potential, and the other side is connected to the ground potential.
これらリード配線及びコンデンサを構成する櫛形電極６
１．６２は、樹脂フィルム１上に貼り付けたＣｕ膜をエ
ツチングして得られる。Comb-shaped electrodes 6 that constitute these lead wiring and capacitors
1.62 is obtained by etching a Cu film stuck on the resin film 1.
第２図は第１図の要部を拡大して示す平面図であり、第
３図（ａ）（ｂ）はそのＡ−Ａ’及びＢ−Ｂ’断面図で
ある。集積回路チップ２は第３図に明らかなように、樹
脂フィルム１のリード配線形成面と反対側の面に配置さ
れ、インナー・リード部３は、樹脂フィルム１に形成さ
れたスルー配線７を介して、チップ２上の突起電極８に
接続されている。スルー配線７は、樹脂フィルム１にＣ
ｕ膜を貼る前に予め形成しておく。突起電極８は集積回
路チップ２上ではなく、樹脂フィルム１上に形成してお
いてもよく、その構造もＡｕバンブやハンダバンプなど
、如何なるものでもよい。FIG. 2 is an enlarged plan view showing the main part of FIG. 1, and FIGS. 3(a) and 3(b) are sectional views taken along line AA' and line BB'. As is clear from FIG. 3, the integrated circuit chip 2 is arranged on the surface of the resin film 1 opposite to the surface on which the lead wiring is formed, and the inner lead portion 3 is connected to the resin film 1 through the through wiring 7 formed on the resin film 1. and is connected to the protruding electrode 8 on the chip 2. The through wiring 7 is connected to the resin film 1 by C.
Form in advance before pasting the u film. The protruding electrode 8 may be formed on the resin film 1 instead of on the integrated circuit chip 2, and its structure may be of any type, such as an Au bump or a solder bump.
例えば、集積回路チップ２上に形成する場合には、Ｔｊ
−Ｐｔ −Ａｕ 、Ｃｒ −Ｃｕ−Ａｕなどのバリア
金属層を介してＡｕメツキを行なって、突起電極８が得
られる。この突起電極８と接する部分の樹脂フィルム１
には、ＳｎメツキあるいはＡｕメツキを施しておく。集
積回路チップ２と樹脂フィルム１の接合は、熱せられた
ツールを樹脂フィルム上面から押し当てることにより行
われる。ツールの熱は、スレー配線７を通し突起電極８
までよく伝わり、良好な接合が行われる。For example, when forming on the integrated circuit chip 2, Tj
The protruding electrode 8 is obtained by performing Au plating through a barrier metal layer such as -Pt-Au or Cr-Cu-Au. Resin film 1 in the part that comes into contact with this protruding electrode 8
is coated with Sn plating or Au plating. The integrated circuit chip 2 and the resin film 1 are bonded by pressing a heated tool against the resin film from above. The heat of the tool passes through the slay wiring 7 to the protruding electrode 8.
The contact is transmitted well, and a good bond is achieved.
デカップリング用コンデンサの電極６１．６２は前述の
ようにそれぞれ電源線、接地線に接続される。そして集
積回路チップ２とコンデンサはほぼ重なる位置に配置さ
れる。集積回路チップでは電源線に急峻な電流が流れる
ため、デカップリング用コンデンサはできるだけ集積回
路チップに近い位置に配置することが望ましいが、この
実施例でこれが実現されている。The electrodes 61 and 62 of the decoupling capacitor are connected to the power supply line and the ground line, respectively, as described above. The integrated circuit chip 2 and the capacitor are arranged at substantially overlapping positions. Since a steep current flows through the power supply line in an integrated circuit chip, it is desirable to place the decoupling capacitor as close to the integrated circuit chip as possible, and this is achieved in this embodiment.
第４図は、この実施例による集積回路の等価回路である
。図示のように、集積回路チップ２の電源Ｐと接地線Ｑ
の間にデカップリング用コンデンサＣが接続された形に
なる。FIG. 4 is an equivalent circuit of the integrated circuit according to this embodiment. As shown, the power supply P and ground line Q of the integrated circuit chip 2
A decoupling capacitor C is connected between them.
以上のようにこの実施例では、ＴＡＢ方式を用いてその
樹脂フィルム上に櫛形電極によるデカップリング用のコ
ンデンサを形成している。従ってリード配線のインダク
タンス成分の影響を除去し、電源電圧の安定化によって
集積回路チップの高速性を充分に発揮させることができ
る。特にこの実施例ではデカップリング用コンデンサは
、集積回路チップ搭載領域内に形成されているので、樹
脂フィルム上で格別の面積を占有する訳ではなく、リー
ド配線の高密度化を損うこともない。As described above, in this embodiment, a decoupling capacitor using a comb-shaped electrode is formed on the resin film using the TAB method. Therefore, the influence of the inductance component of the lead wires is removed, and the power supply voltage is stabilized, thereby making it possible to fully utilize the high speed performance of the integrated circuit chip. In particular, in this embodiment, the decoupling capacitor is formed within the integrated circuit chip mounting area, so it does not occupy a particular area on the resin film and does not impair the high density of the lead wiring. .
本発明は、樹脂フィルムの両面にデカップリング用コン
デンサを形成することも有効である。その実施例の構造
を第５図（ａ）（ｂ）に示す。第５図（ａ）（ｂ）はそ
れぞれ、先の実施例の第２図（ａ）（ｂ）に対応する断
面図である。先の実施例と同様に樹脂フィルム１の上面
に櫛形電極６、．６２によりデカップリング用コンデン
サを形成すると同時に、これと対向させて樹脂フィルム
１の下面にも櫛形電極６１ ’ ＋ ６２′ による
デカップリング用コンデンサを形成している。この場合
より厳密には、上面の電源線に接続される電極６１と下
面の接地線に接続される電極６□′とが対向し、上面の
接地線に接続される電極６２と下面の電源線に接続され
る電極６１′が対向するように、両面の櫛形電極パター
ンを重ね合せる。In the present invention, it is also effective to form decoupling capacitors on both sides of the resin film. The structure of this embodiment is shown in FIGS. 5(a) and 5(b). FIGS. 5(a) and 5(b) are sectional views corresponding to FIGS. 2(a) and 2(b) of the previous embodiment, respectively. As in the previous embodiment, comb-shaped electrodes 6, . A decoupling capacitor is formed by 62, and at the same time, a decoupling capacitor is formed by comb-shaped electrodes 61'+62' on the lower surface of the resin film 1 opposite to this. More precisely, in this case, the electrode 61 connected to the power line on the top surface and the electrode 6□' connected to the ground wire on the bottom surface face each other, and the electrode 62 connected to the ground wire on the top surface and the power line on the bottom surface face each other. The comb-shaped electrode patterns on both sides are overlapped so that the electrodes 61' connected to the electrodes 61' face each other.
この実施例によっても先の実施例と同様の効果が得られ
る。特にこの実施例では、上面の電極と下面の電極とは
互いに異なる電位に設定されるもの同士が対向するよう
にパターン設計することによって、樹脂フィルム１の厚
みが容量として入るため、先の実施例に比べて２倍以上
の大きい容量を得ることができる。This embodiment also provides the same effects as the previous embodiment. In particular, in this embodiment, the thickness of the resin film 1 is included as a capacitance by designing the pattern so that the electrodes on the upper surface and the electrodes on the lower surface are set at different potentials and face each other, so that the thickness of the resin film 1 is included as the capacitance. It is possible to obtain a capacity that is more than twice as large as that of the previous one.
第６図は、他の実施例の平面図を第１図に対応させて示
す。この実施例では、樹脂フィルム１の集積回路チップ
載５！２Ｈに孔を有し、この部分にリード配線の先端が
舌片として突出している。このリード配線の舌片を集積
回路チップの突起電極に接続するように、集積回路チッ
プ５が載置される。FIG. 6 shows a plan view of another embodiment corresponding to FIG. In this embodiment, a hole is provided in the integrated circuit chip mounting portion 5!2H of the resin film 1, and the tip of the lead wiring protrudes from this portion as a tongue piece. The integrated circuit chip 5 is placed so that the tongues of the lead wires are connected to the protruding electrodes of the integrated circuit chip.
この様な構成において、デカップリング用のコンデンサ
は、孔が開いた集積回路チップ載置部の４隅に、櫛形電
極６１，６□により形成されている。In this configuration, decoupling capacitors are formed by comb-shaped electrodes 61, 6□ at the four corners of the perforated integrated circuit chip mounting portion.
・この実施例によっても先の実施例と同様の効果が得ら
れる。- This embodiment also provides the same effects as the previous embodiment.
第７図は、更に他の実施例の第２図（ａ）に対応する断
面図である。この実施例では、第１図の実施例に加えて
、櫛形電極６１＋６２の領域上に誘電体膜９を形成して
いる。誘電体膜９は例えば、Ｂａ ”ｒｔ ０３ 、Ｔ
ａ ２０５ 、Ｔ１０２等の高誘電率の酸化物膜をスパ
ッタにより形成する。このとき、櫛形電極パターン領域
上に選択的に誘電体膜９を形成するために、例えばメタ
ルマスクを用いる。櫛形電極パターンの形成領域を例え
ば８ ｍｍ角とし、電極の幅Ｗ−５０μｍ、スペース５
−５０μ辺とすると、約４０対の電極パターンをこの領
域に形成できる。そしてこの上に誘電体膜を被覆するこ
とにより、大きい容量を得ることができる。FIG. 7 is a sectional view corresponding to FIG. 2(a) of still another embodiment. In this embodiment, in addition to the embodiment shown in FIG. 1, a dielectric film 9 is formed on the area of the comb-shaped electrodes 61+62. The dielectric film 9 is made of, for example, Ba ``rt 03 , T
A high dielectric constant oxide film such as a 205 and T102 is formed by sputtering. At this time, a metal mask, for example, is used to selectively form the dielectric film 9 on the comb-shaped electrode pattern region. For example, the formation area of the comb-shaped electrode pattern is 8 mm square, the electrode width W-50 μm, and the space 5.
If the side is -50μ, approximately 40 pairs of electrode patterns can be formed in this area. By covering this with a dielectric film, a large capacity can be obtained.
第８図はこの実施例において、誘電体膜９としてＴａ２
０５膜を用いた場合の、その膜厚と容量の関係を示した
ものである。これから、適当な膜厚の誘電体膜を重ねる
ことにより大きい容量が得られることがわかる。誘電体
膜９は、厚膜により形成してもよい。FIG. 8 shows that Ta2 is used as the dielectric film 9 in this embodiment.
This figure shows the relationship between the film thickness and capacity when a 05 film is used. It can be seen from this that a large capacitance can be obtained by stacking dielectric films of appropriate thickness. The dielectric film 9 may be formed of a thick film.
第９図は更に他の実施例である。電極パターンは若干具
なるが、基本的に第３図の構造をベースとし、その４隅
のデカップリング用コンデンサ上に先の実施例と同様に
誘電体膜９を形成したちのである。FIG. 9 shows yet another embodiment. Although the electrode pattern is slightly different, the structure is basically based on the structure shown in FIG. 3, and the dielectric film 9 is formed on the decoupling capacitors at the four corners as in the previous embodiment.
この実施例によっても、先の実施例と同様の効果が得ら
れる。This embodiment also provides the same effects as the previous embodiment.
［発明の効果コ
以上述べたように本発明によれば、ＴＡＢ方式を採用し
てその集積回路チップ載置位置近傍に櫛形電極によるデ
カップリング用コンデンサを配置することにより、効果
的に電源電圧の安定化が図られ、集積回路チップのもつ
高速性能を充分に発揮させることができる。[Effects of the Invention] As described above, according to the present invention, the power supply voltage can be effectively reduced by adopting the TAB method and arranging a decoupling capacitor with a comb-shaped electrode near the integrated circuit chip mounting position. Stabilization is achieved, and the high-speed performance of the integrated circuit chip can be fully demonstrated.
第１図は本発明の一実施例のＧａＡｓ論理集積回路の構
成を示す平面図、第２図はその要部の拡大平面図、第３
図（ａ）、（ｂ）はそれぞれ第２図のＡ−Ａ’、Ｂ−Ｂ
’断面図、第４図は本発明の詳細な説明するための等価
回路図、第５図（ａ）、（ｂ）は他の実施例の集積回路
を示す。
それぞれ第３図（ａ）、（ｂ）に対応する断面図、第６
図は他の実施例の集積回路を示す平面図、第７図は更に
他の実施例の集積回路を示す断面図、第８図は誘電体膜
被覆の効果を示す特性図、第９図は更に他の実施例の集
積回路を示す平面図である。
１・・・樹脂フィルム、２・・・集積回路チップ、３゜
４．５・・・リード配線、６１＋６２・・・櫛形電極、
６１ ’ ＋ ６２′・・・櫛形電極、７・・・スル
ー配線、８・・・突起電極、９・・・誘電体膜。
出願人代理人 弁理士 鈴江武彦
り
第４図
第７図
版／Ｓ Ｈ（Ｐｍ）
第８ 図
第９ｆｆｌFIG. 1 is a plan view showing the configuration of a GaAs logic integrated circuit according to an embodiment of the present invention, FIG. 2 is an enlarged plan view of the main parts thereof, and FIG.
Figures (a) and (b) are A-A' and B-B in Figure 2, respectively.
4 is an equivalent circuit diagram for explaining the present invention in detail, and FIGS. 5(a) and 5(b) show integrated circuits of other embodiments. Cross-sectional views corresponding to FIGS. 3(a) and 6(b), respectively.
The figure is a plan view showing an integrated circuit of another embodiment, FIG. 7 is a cross-sectional view showing an integrated circuit of still another embodiment, FIG. 8 is a characteristic diagram showing the effect of dielectric film coating, and FIG. FIG. 7 is a plan view showing an integrated circuit according to still another embodiment. DESCRIPTION OF SYMBOLS 1...Resin film, 2...Integrated circuit chip, 3°4.5...Lead wiring, 61+62...Comb-shaped electrode,
61' + 62'...Comb-shaped electrode, 7...Through wiring, 8...Protruding electrode, 9...Dielectric film. Applicant's agent Patent attorney Takehiko Suzue Figure 4 Figure 7 plate/S H (Pm) Figure 8 Figure 9ffl
Claims (5)
線が形成された樹脂フィルムと、この樹脂フィルムの前
記チップ載置部に載置された半導体集積回路チップとを
備えた半導体集積回路装置において、前記樹脂フィルム
上に櫛形状電極によるデカップリング用コンデンサを配
設したことを特徴とする半導体集積回路装置。(1) A semiconductor integrated circuit device comprising a resin film having an integrated circuit chip mounting portion and on which a plurality of lead wires are formed, and a semiconductor integrated circuit chip placed on the chip mounting portion of the resin film. 2. A semiconductor integrated circuit device according to claim 1, wherein a decoupling capacitor having a comb-shaped electrode is disposed on the resin film.
ド配線と同じ面に形成され、前記集積回路チップは前記
リード配線と反対側の面に載置される特許請求の範囲第
１項記載の半導体集積回路装置。(2) The semiconductor integrated circuit according to claim 1, wherein the capacitor is formed on the same side of the resin film as the lead wiring, and the integrated circuit chip is placed on the opposite side of the lead wiring. circuit device.
互いに異なる電位に設定される電極が対向するように配
設される特許請求の範囲第１項記載の半導体集積回路装
置。(3) The capacitor includes on both sides of the resin film,
The semiconductor integrated circuit device according to claim 1, wherein the electrodes set to different potentials are arranged to face each other.
周辺４隅に配置される特許請求の範囲第１項記載の半導
体集積回路装置。(4) The semiconductor integrated circuit device according to claim 1, wherein the capacitors are arranged at four peripheral corners of the integrated circuit chip mounting section.
覆されている特許請求の範囲第１項記載の半導体集積回
路装置。(5) The semiconductor integrated circuit device according to claim 1, wherein the capacitor has a comb-shaped upper electrode covered with a dielectric film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25499287A JPH0196943A (en) | 1987-10-09 | 1987-10-09 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25499287A JPH0196943A (en) | 1987-10-09 | 1987-10-09 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0196943A true JPH0196943A (en) | 1989-04-14 |
Family
ID=17272706
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25499287A Pending JPH0196943A (en) | 1987-10-09 | 1987-10-09 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0196943A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6784050B1 (en) | 2000-09-05 | 2004-08-31 | Marvell International Ltd. | Fringing capacitor structure |
| US6974744B1 (en) | 2000-09-05 | 2005-12-13 | Marvell International Ltd. | Fringing capacitor structure |
| US6980414B1 (en) | 2004-06-16 | 2005-12-27 | Marvell International, Ltd. | Capacitor structure in a semiconductor device |
| US7906424B2 (en) | 2007-08-01 | 2011-03-15 | Advanced Micro Devices, Inc. | Conductor bump method and apparatus |
| US8314474B2 (en) | 2008-07-25 | 2012-11-20 | Ati Technologies Ulc | Under bump metallization for on-die capacitor |
| US8941974B2 (en) | 2011-09-09 | 2015-01-27 | Xilinx, Inc. | Interdigitated capacitor having digits of varying width |
| US9270247B2 (en) | 2013-11-27 | 2016-02-23 | Xilinx, Inc. | High quality factor inductive and capacitive circuit structure |
| US9524964B2 (en) | 2014-08-14 | 2016-12-20 | Xilinx, Inc. | Capacitor structure in an integrated circuit |
-
1987
- 1987-10-09 JP JP25499287A patent/JPH0196943A/en active Pending
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6885543B1 (en) | 2000-09-05 | 2005-04-26 | Marvell International, Ltd. | Fringing capacitor structure |
| US6974744B1 (en) | 2000-09-05 | 2005-12-13 | Marvell International Ltd. | Fringing capacitor structure |
| US6784050B1 (en) | 2000-09-05 | 2004-08-31 | Marvell International Ltd. | Fringing capacitor structure |
| US9017427B1 (en) | 2001-01-18 | 2015-04-28 | Marvell International Ltd. | Method of creating capacitor structure in a semiconductor device |
| US8537524B1 (en) | 2004-06-16 | 2013-09-17 | Marvell International Ltd. | Capacitor structure in a semiconductor device |
| US6980414B1 (en) | 2004-06-16 | 2005-12-27 | Marvell International, Ltd. | Capacitor structure in a semiconductor device |
| US7116544B1 (en) | 2004-06-16 | 2006-10-03 | Marvell International, Ltd. | Capacitor structure in a semiconductor device |
| US7578858B1 (en) | 2004-06-16 | 2009-08-25 | Marvell International Ltd. | Making capacitor structure in a semiconductor device |
| US7988744B1 (en) | 2004-06-16 | 2011-08-02 | Marvell International Ltd. | Method of producing capacitor structure in a semiconductor device |
| US7906424B2 (en) | 2007-08-01 | 2011-03-15 | Advanced Micro Devices, Inc. | Conductor bump method and apparatus |
| US8294266B2 (en) | 2007-08-01 | 2012-10-23 | Advanced Micro Devices, Inc. | Conductor bump method and apparatus |
| US8314474B2 (en) | 2008-07-25 | 2012-11-20 | Ati Technologies Ulc | Under bump metallization for on-die capacitor |
| US8941974B2 (en) | 2011-09-09 | 2015-01-27 | Xilinx, Inc. | Interdigitated capacitor having digits of varying width |
| US9270247B2 (en) | 2013-11-27 | 2016-02-23 | Xilinx, Inc. | High quality factor inductive and capacitive circuit structure |
| US9524964B2 (en) | 2014-08-14 | 2016-12-20 | Xilinx, Inc. | Capacitor structure in an integrated circuit |
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