JPS58219757A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS58219757A JPS58219757A JP57103304A JP10330482A JPS58219757A JP S58219757 A JPS58219757 A JP S58219757A JP 57103304 A JP57103304 A JP 57103304A JP 10330482 A JP10330482 A JP 10330482A JP S58219757 A JPS58219757 A JP S58219757A
- Authority
- JP
- Japan
- Prior art keywords
- package
- semiconductor device
- unit
- envelope
- stacked
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1029—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being a lead frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/107—Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/1627—Disposition stacked type assemblies, e.g. stacked multi-cavities
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、ノ臂ツケージの両側面より外部導出リード
の引き出される外囲器を有する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device having an envelope from which external leads are drawn out from both sides of an arm cage.
電子機器の小型化・、多機能化が近年急速に進んでおり
、それに伴い、各種半導体装置をいかに高密度に実装す
るかについて様々な技術的検討がなされている。現在、
こういった高密度実装技術の中で実用化されているもの
にＴＡＢ技術と呼ばれるものがある・
このＴＡＢ技術とは、第１図に示すようにチップ部に孔
１１を有する長尺のポリイミドテープ１２に銅箔等でリ
ードパターン１３を形式し、このリードパターン１３の
フィンガリード１４と呼ばれる先端部を上記孔１１にお
いて突出させておき、これに、金のバンプ１５を上面に
有する半導体チ、ノ１６を、連続的にボンディングして
ゆくもので、その後、図のａ −ａ’でフィンガーリー
ド１４を切断し、基板上の導体やリードフレームに接続
する技術である。このＴＡＢ技術は、一般のＤＩＰ （
デュアルインライン）のパッケージのものに比べ形状を
、数分の工程度に小型化できるが、半導体チップノロに
金等によってバング１５を形成する必要がある。このバ
ンプ１５の形成工程は高度な技術を必要とする。また、
このＴＡＢ技術による実装は、組み立て技術が特殊で汎
用性に難点がある。2. Description of the Related Art In recent years, electronic devices have rapidly become smaller and more multifunctional, and various technical studies have been conducted on how to densely package various semiconductor devices. the current,
Among these high-density mounting technologies, one that has been put to practical use is called TAB technology. This TAB technology is a long polyimide tape with holes 11 in the chip part, as shown in Figure 1. A lead pattern 13 is formed on the hole 12 using copper foil or the like, and the tip of the lead pattern 13 called a finger lead 14 is made to protrude in the hole 11. This is a technique in which the finger leads 14 are bonded continuously, and then the finger leads 14 are cut along a-a' in the figure and connected to the conductor on the board or the lead frame. This TAB technology is similar to general DIP (
Although the shape can be reduced to a process time of a few minutes compared to a dual-in-line package, it is necessary to form the bang 15 with gold or the like on the semiconductor chip slag. This step of forming bumps 15 requires advanced technology. Also,
Implementation using this TAB technology requires special assembly technology and has a drawback in terms of versatility.
上記のような、ＴＡＢ技術の他に、チップキャリアタイ
プパッケージによる高密度実装化が行なわれる場合があ
る。このチップキャリアタイプパッケージという′のは
、例えば第２図に示すように、内部に半導体チップを収
納した平形のセラミック製外囲器１７の周囲に溝部１８
．１８・・・を設け、内部の半導体チップと接続した金
属電極１９．１９・・・を、この溝部１８．１８・・・
がら上記外囲器１７底面にかけて形成したものである。In addition to the TAB technology described above, high-density packaging using chip carrier type packages is sometimes performed. This chip carrier type package is, for example, as shown in FIG.
．． 18... are provided, and the metal electrodes 19, 19... connected to the internal semiconductor chip are connected to the grooves 18, 18...
It is formed over the bottom surface of the envelope 17.
このようなチップキャリアタイプパッケージ２０は例え
ば第３図に示すように、基板２１上に形成された導体パ
ターン２２と、金属電極１９．１９・・・の下部とを半
田付けして実装する。Such a chip carrier type package 20 is mounted by soldering the conductor pattern 22 formed on the substrate 21 and the lower part of the metal electrodes 19, 19, . . . , as shown in FIG. 3, for example.
このようにして実装するチップキャリアタイプのものも
、パッケージが小型で、かつ外部の基板２１と金属電極
１９．１９・・・との接続部は、殆んど面積を専有せず
高密度実装が可能である。The chip carrier type that is mounted in this manner also has a small package, and the connection portion between the external substrate 21 and the metal electrodes 19, 19, etc. occupies almost no area, allowing for high-density mounting. It is possible.
しかし、この場合は、パッケージそのものの構造が特殊
であり、組立コストが高いという欠点がある。However, this case has the disadvantage that the structure of the package itself is special and the assembly cost is high.
この発明は上記のような点に鑑みなされたもので、従来
の半導体装置の製造設備を用いて製造可能であり、安価
で高密度実装可能な半導体装置を提供しようとするもの
である。The present invention has been made in view of the above points, and aims to provide a semiconductor device that can be manufactured using conventional semiconductor device manufacturing equipment, and that can be mounted at low cost and with high density.
すなわち、この発明に係る半導体装置は、現在広く用い
られているＤＩＰ型の７４’ツケージの半導体装置を複
数積層するようにしたものである。That is, the semiconductor device according to the present invention has a plurality of stacked DIP type 74' cage semiconductor devices which are currently widely used.
〔発明の実施例〕、、。[Embodiments of the invention].
以下図面を参照してこの発明の一実施例につき説明する
。第４図はサーディツプタイグのＤＩＰ型パッケージに
おける本体の蓋を除いた断面図で、本体のアルミナ製基
台３１の上に半導体チップ３２が接着し、基台３１の両
側面に低融点ガラス３３によって固定された外部導出リ
ード３４と半導体チップ３２をワイヤデンディングした
ものである。このような半導体装置の外囲器を単位外囲
器３０として、第５図に示すように複数積み重ねる。こ
の際、上段となる単位外囲器３０の本体裏面に凹部３５
を形成しておき、上段の単位外囲器３０が下段の単位外
囲器３０を封止するように重ね、最上段の単位外囲器３
０はアルミナ製の蓋３６で封止する。An embodiment of the present invention will be described below with reference to the drawings. FIG. 4 is a cross-sectional view of the main body of the DIP type package of Surdip Type with the lid removed. A semiconductor chip 32 is adhered to the alumina base 31 of the main body, and low melting point glass is attached to both sides of the base 31. The semiconductor chip 32 and the external lead 34 fixed by the wire 33 are wire-ended. A plurality of such semiconductor device envelopes are stacked as a unit envelope 30 as shown in FIG. At this time, a recess 35 is formed on the back surface of the unit envelope 30 that is the upper stage.
are stacked so that the upper unit envelope 30 seals the lower unit envelope 30, and the uppermost unit envelope 3
0 is sealed with a lid 36 made of alumina.
上記で使用する単位外囲器３０の基台３１は現在広く使
用されているいわゆるサーディツプ（ｃ＠ｒ−ＤＩＰ
）タイグパ、ケージの製造装置で安価に形成でき、第５
図に示す装置は、ダイマウ ゛ントされた上記の安価な
単位外囲器３０の基台３１と、ワイヤデンディングされ
た外部導出リード３４とを順次低融点ガラスを挾んで積
層し、従来のサーディップタイグパ、ケージ用の炉等の
組み立て装置に通すことにより製造できる。The base 31 of the unit envelope 30 used above is a so-called cerdip (c@r-DIP) which is currently widely used.
) It can be formed inexpensively using Taigupa and cage manufacturing equipment, and the fifth
The device shown in the figure is constructed by stacking a die-mounted base 31 of the above-mentioned inexpensive unit envelope 30 and wire-ended external lead-out leads 34 with a piece of low-melting glass sandwiched between them. It can be manufactured by passing it through an assembly device such as a dip tie or cage furnace.
すなわち一般的で汎用性のある設備を利用し、少い工程
数で低摩に製造することができるものである。That is, it can be manufactured with low wear and a small number of steps using general and versatile equipment.
そして、この第５図に示す装置では半導体チ、プ３２と
外部導出リード３４のデンディングされているノ！ッケ
ージの本体が積層されており、通常のＤＩＰ Ｗパ、ケ
ージの半導体装置をプリント基板等へ実装する場合に比
ベプリント基板での専有面積を著しく減少させることが
できる。In the device shown in FIG. 5, the semiconductor chip 32 and the external lead 34 are connected to each other. Since the main body of the package is stacked, it is possible to significantly reduce the area occupied by the printed circuit board when mounting a semiconductor device of a normal DIP W package on a printed circuit board or the like.
第６図には上記のような半導体装置をプリントる。In FIG. 6, a semiconductor device as described above is printed.
また、第５図の場合では、上段の単位外囲器′ ３０裏
面に凹部３５を設けその直下の単位外囲器３０を封止す
るようにしたが、第７図に示すように、それぞれの単位
外囲器３０は封止用の蓋３１′付のものとして、それぞ
れの単位外囲器３０の本体を接着剤等で固定しても良い
。Further, in the case of FIG. 5, a recess 35 is provided on the back surface of the upper unit envelope 30 to seal the unit envelope 30 directly below it, but as shown in FIG. The unit envelopes 30 may be provided with a lid 31' for sealing, and the main body of each unit envelope 30 may be fixed with an adhesive or the like.
上記のようなサーディツプタイプの単位外囲器３０を多
段に積層するものは、比較的低摩で高い信頼性の気密封
止を行なうことができるが、サーディップタイグ程の高
信頼性を要求されない半導体素子には、例えば第８図に
示すよ、うに樹脂封止型パッケージの単位外囲器３８を
多段に積層するようにしても良い。この場合もパッケー
ジの本体３９を重ねることにより、特別のアセンブリ技
術や高度な技術を用いずに低摩に高密度実装可能な半導
体装置を製造できる。The above-mentioned cerdip type unit envelope 30 stacked in multiple stages can provide a highly reliable hermetic seal with relatively low friction, but it is not as reliable as the cerdip type. For semiconductor elements that do not require the following, for example, as shown in FIG. 8, unit envelopes 38 of resin-sealed packages may be stacked in multiple stages. In this case as well, by overlapping the package bodies 39, a semiconductor device that can be mounted with low friction and high density can be manufactured without using any special assembly technology or advanced technology.
なお、単位外囲器３８を積層する際、本体の位置合わせ
が容易なように単位外囲器３８の本体それぞれに継合部
を設ければざらに良い。In addition, when stacking the unit envelopes 38, it is generally better if a joint portion is provided in each body of the unit envelopes 38 so that alignment of the bodies is easy.
以上のようにこの発明によれは、グイマウントされた半
導体チップおよびワイヤビンディングされたリードフレ
ームを含む単位外囲器を複数積層することにより、安価
で高密度実装可能な半導体装置を提供できる。As described above, according to the present invention, by stacking a plurality of unit envelopes each including a semiconductor chip that is mounted on a wire and a lead frame that is wire-bound, it is possible to provide a semiconductor device that can be mounted at low cost and with high density.
第１図は従来の半導体装置を説明する断面図、第２図は
従来の半導体装置を示す斜視図、第３図は従来の半導体
装置を示す断面図、第４図はこの発明の一実施例を説明
する断面図、第５図はこの発明の一実施例を示す断面図
、第６図はその実装状態を示す斜視図、第７図および第
８図はそれぞれこの発明の他の実施例を示す断面図であ
る。
３０．３８・・・単位外囲器、３１・・・基台、３１′
。
３６・・・蓋、３２・・・半導体チップ、３３・・・低
融点ガラス、３４・・・外部導出リード。
出願人代理人 弁理士 鈴 江 武 彦第４図FIG. 1 is a sectional view illustrating a conventional semiconductor device, FIG. 2 is a perspective view illustrating a conventional semiconductor device, FIG. 3 is a sectional view illustrating a conventional semiconductor device, and FIG. 4 is an embodiment of the present invention. FIG. 5 is a cross-sectional view showing one embodiment of the invention, FIG. 6 is a perspective view showing its mounting state, and FIGS. 7 and 8 respectively show other embodiments of the invention. FIG. 30.38...Unit envelope, 31...Base, 31'
. 36... Lid, 32... Semiconductor chip, 33... Low melting point glass, 34... External lead-out lead. Applicant's agent Patent attorney Takehiko Suzue Figure 4
Claims (3)
ップに接続する外部導出リードを両側面に有する複数の
単位外囲器を具備し、上記単位外囲器は積層して一体化
されていることを特徴とする半導体装置。(1) It is equipped with a plurality of unit envelopes on which semiconductor chips, 7" are mounted or housed and have external lead-out leads connected to the semiconductor chips on both sides, and the unit envelopes are stacked and integrated. A semiconductor device characterized by:
の単位外囲器直下の単位外囲器を封止して積層し、最上
段の単位外囲器はこの単位外囲器封止用の蓋を備えてい
ることを特徴とする特許請求の範囲第１項記載の半導体
装置。(2) The above unit envelope is stacked with the bottom surface of the upper unit envelope sealing the unit envelope immediately below this unit envelope, and the uppermost unit envelope is stacked with the unit envelope directly below this unit envelope. 2. The semiconductor device according to claim 1, further comprising a lid for sealing the semiconductor device.
ることを特徴とする特許請求の範囲第１項ま・匙は第２
項記載の半導体装置。(3) Claim 1, characterized in that the unit envelope is of the type
1. Semiconductor device described in Section 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57103304A JPS58219757A (en) | 1982-06-16 | 1982-06-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57103304A JPS58219757A (en) | 1982-06-16 | 1982-06-16 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58219757A true JPS58219757A (en) | 1983-12-21 |
Family
ID=14350488
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57103304A Pending JPS58219757A (en) | 1982-06-16 | 1982-06-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58219757A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1988008203A1 (en) * | 1987-04-17 | 1988-10-20 | Xoc Devices, Inc. | Packaging system for stacking integrated circuits |
| JPH0197615U (en) * | 1987-11-26 | 1989-06-29 | ||
| EP0340241A1 (en) * | 1987-01-05 | 1989-11-08 | Irvine Sensors Corp | High density electronic package comprising stacked sub-modules. |
| US4953005A (en) * | 1987-04-17 | 1990-08-28 | Xoc Devices, Inc. | Packaging system for stacking integrated circuits |
| US5514907A (en) * | 1995-03-21 | 1996-05-07 | Simple Technology Incorporated | Apparatus for stacking semiconductor chips |
| US6380616B1 (en) | 1998-01-15 | 2002-04-30 | Infineon Technologies Ag | Semiconductor component with a number of substrate layers and at least one semiconductor chip, and method of producing the semiconductor component |
| US6683373B1 (en) * | 1999-08-02 | 2004-01-27 | Alcatel | Method of modifying connecting leads and thinning bases of encapsulated modular electronic components to obtain a high-density module, and a module obtained thereby |
| US6806120B2 (en) | 2001-03-27 | 2004-10-19 | Staktek Group, L.P. | Contact member stacking system and method |
-
1982
- 1982-06-16 JP JP57103304A patent/JPS58219757A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0340241A1 (en) * | 1987-01-05 | 1989-11-08 | Irvine Sensors Corp | High density electronic package comprising stacked sub-modules. |
| WO1988008203A1 (en) * | 1987-04-17 | 1988-10-20 | Xoc Devices, Inc. | Packaging system for stacking integrated circuits |
| US4862249A (en) * | 1987-04-17 | 1989-08-29 | Xoc Devices, Inc. | Packaging system for stacking integrated circuits |
| US4953005A (en) * | 1987-04-17 | 1990-08-28 | Xoc Devices, Inc. | Packaging system for stacking integrated circuits |
| JPH0197615U (en) * | 1987-11-26 | 1989-06-29 | ||
| US5514907A (en) * | 1995-03-21 | 1996-05-07 | Simple Technology Incorporated | Apparatus for stacking semiconductor chips |
| USRE36916E (en) * | 1995-03-21 | 2000-10-17 | Simple Technology Incorporated | Apparatus for stacking semiconductor chips |
| US6380616B1 (en) | 1998-01-15 | 2002-04-30 | Infineon Technologies Ag | Semiconductor component with a number of substrate layers and at least one semiconductor chip, and method of producing the semiconductor component |
| US6683373B1 (en) * | 1999-08-02 | 2004-01-27 | Alcatel | Method of modifying connecting leads and thinning bases of encapsulated modular electronic components to obtain a high-density module, and a module obtained thereby |
| US6806120B2 (en) | 2001-03-27 | 2004-10-19 | Staktek Group, L.P. | Contact member stacking system and method |
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