JPH0155788B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to code error control suitable for coded teletext broadcasting in which character and graphic information coded as digital signals are multiplexed and transmitted during the vertical blanking period of a TV signal. In particular, it relates to an error correction decoding circuit that attempts to recover as much as possible by correcting bit errors occurring on a transmission path.

(Technical Background) As an error correction method for this type of service that uses a TV transmission path, one packet consists of 272 bits, and a data signal of 272 data bits, 190 information bits, and 82 parity bits is formed and transmitted. The decoding method is based on patent application 1986-6579.
(Japanese Unexamined Patent Publication No. 59-133751), Japanese Patent Application No. 58-54002 (Unexamined Japanese Patent Application No. 59-181841), and Japanese Patent Application No. 58-90017
(Japanese Unexamined Patent Publication No. 59-216388).

FIG. 1 shows a schematic configuration of the error correction decoding circuit disclosed herein. In Figure 1, 1 is the CPU
(not shown), which is the input terminal of output port 2 and the input terminal of input port 3.
is connected to the output terminal of the

Output port 2 supplies uncorrected data 5 to error correction circuit 4 . The error correction circuit 4 includes a parallel-to-serial conversion circuit, a serial-to-parallel conversion circuit, a syndrome register,
Contains data registers, majority circuits, etc.
(272, 190) The code is corrected, and the corrected data 6 and ready signal 10 are supplied to the input port 3. A start signal 7, a load signal 8, and a collect signal 9 are supplied from the CPU to the error correction circuit 4 via the output port 2.

Next, the operation shown in FIG. 1 will be explained. To start error correction, the CPU first sends the start signal 7.
is supplied to the error correction circuit 4, and the syndrome register is cleared. Next, the CPU supplies the uncorrected data to the error correction circuit 4 in units of predetermined bits (for example, 8 bits or 16 bits) via the CPU bus line 1 and the output port, and provides a load signal 8 each time. The error correction circuit 4 performs parallel-to-serial conversion on 8-bit (or 16-bit) data and inputs it into the data register and syndrome register. Therefore, to introduce 272-bit packet data, it is repeated 34 times in 8-bit units (17 times in 16-bit units). Introducing 272 bits of data creates a syndrome in the syndrome register. Next, the CPU gives the collect signal to the error correction circuit 4 via the CPU bus line 1 and the output port 2, and the error correction circuit 4 corrects the error in units of 8 bits (or 16 bits) and performs serial-to-parallel conversion. Input port 3 as corrected data 6
and returns to the CPU via CPU bus line 1.
If you repeat this 34 times in 8-bit units (17 times in 16-bit units), all 272 bits will be corrected.
captured by the CPU.

The ready signal 10 indicates whether or not 8-bit (or 16-bit) uncorrected data may be supplied from the CPU, or whether the CPU may read 8-bit (or 16-bit) post-corrected data.
This is a signal to notify the CPU.

In this manner, the error correction of the (272, 190) code, which is the (273, 191) code shortened by 1 bit, can be performed in FIG.

However, in teletext broadcasting outside of Japan, systems in which one packet does not contain 272 bits are being considered.
Alternatively, methods other than 272 bits per packet are being considered for other uses as well. For such uses, the (272, 190) code was inconvenient.

(Object of the Invention) The purpose of the present invention is to solve the problems of the prior art described above, and to apply not only the (272, 190) code, which is one bit shortened from the (273, 191) code, but also other reduced bit numbers. The purpose is to specify and select a reduced number of information bits so that it can also be applied.

(Embodiment) A circuit diagram of a first embodiment of the present invention is shown in FIG. In FIG. 2, 20 is a data bus of the CPU (not shown), and 21 is an address bus of the CPU.
The data bus 20 of the CPU is the data bus control circuit 2
The second input/output terminal of the data bus control circuit 22 is connected to the local data bus 23.

The address bus 21 of the CPU is connected to a first input terminal of an address switching circuit 24, and an automatic address signal 26 is supplied from an address generation circuit 25 to a second input terminal of the address switching circuit 24. The address switching circuit 24 selects either the CPU address signal applied to the first input terminal or the automatic address signal 26 applied to the second input terminal in accordance with the bus control signal 28 supplied from the timing control circuit 27. The signal is selected and supplied to the address input terminal of the buffer memory 29 as a memory address signal.

The local data bus 23 is also connected to a data input/output terminal of the buffer memory 29 and a data input/output terminal of the data transfer circuit 30, so that the CPU, buffer memory, and data transfer circuit can exchange data with each other. Can be done. The data transfer circuit 30 receives serial reception data 31, which is packet reception data received and extracted by a character code broadcast receiving unit (not shown), and frame synchronization is performed using the character code broadcast framing signal. A synchronous clock 33 is supplied which is synchronized by a framing detection signal 32 indicating the character code broadcast and clock run-in of the character code broadcast.

34 is a data register for storing and shifting the information bits (190 bits for Japanese character code broadcasting) excluding the parity bits of the packet received data (272 bits for Japanese character code broadcasting). The register 36 is the same as that shown in Fig. 10 of Japanese Patent Application No. 58-6579.
It consists of 82 bits and has a feedback loop via an adder 37 modulo 2.

The load gate circuit 38 is the timing control circuit 2
By the load gate signal 39 supplied from 7,
It controls whether or not the uncorrected data 35 is supplied to the syndrome register 36 via the adder 37.
40 is a syndrome register signal, 41 is a majority decision circuit, 42 is a threshold signal that provides a threshold value for making a majority decision, 43 is a threshold generation circuit, 44 is a threshold clock for updating the threshold value, and 45 clears the syndrome register 36. 46 is a first loading clock signal for loading data into the syndrome register 36;
47 is a load end signal for incrementing the syndrome register by 1 bit, 48 is a first correction clock signal, 49 is a second loading clock signal for loading data into the data register 34, and 50 is a second clock signal. 51 is a collect gate circuit for controlling, by a collect gate signal 52, whether or not the result signal of the majority circuit 41 is supplied to the adder 54 as an error correction signal 53; 55 is a corrected data; , 56 is a data selection circuit, 57 is a data selection signal, 58 is a clock signal for serial-parallel conversion and parallel-serial conversion, 59 is a write pulse signal for writing received data into the buffer memory 29, and 60 is a data selection signal. This is a write pulse signal for writing into the buffer memory 29.

61 is a vertical blanking signal or a signal similar to the vertical blanking signal; 62 is a horizontal synchronization signal or a horizontal blanking signal; and 63 is a status signal for indicating the operating state. Reference numeral 64 denotes a register that is set when the syndrome register becomes "0", and its output signal, an error status signal 65, is supplied to the timing control circuit 27.

66 and 67 are address update signals, and 68 is an address update signal.
This is the CPU data request signal.

69 is a reduction bit number designation signal for specifying the number of bits to be shortened from the (272, 190) code, 70 is first correction completion data, 71 is second correction completion data, and 72 is third correction completion data. It is. 73
is an output data selection circuit, which receives an output data selection signal 74 given from the timing control circuit 27.
, one of 70, 71, or 72 is selected and supplied to the data transfer circuit 30 as corrected output data 75. Reference numeral 76 is a sending clock signal for sending out the corrected data.

Next, the operation shown in FIG. 2 will be explained.

The operating modes in Figure 2 are roughly divided into serial-to-parallel conversion of serial received data and writing to the buffer memory, reading uncorrected data from the buffer memory and loading it into the data register and syndrome register, circulating the data register and syndrome register, and deciding by majority. It consists of four operations: performing error correction by changing the judgment threshold value and repeating the cycle, and writing the corrected data to the buffer memory. Further, as a fifth operation mode, the CPU reads out the corrected data stored in the buffer memory.

A flowchart of the concept of these operations is shown in FIG. In some cases, it may be reasonable to correct only the data of a specifically specified packet or packets, rather than the data of all received packets. The packet data shall be corrected. As shown in FIG. 3, in the first operation mode, all the received data of the packets for one vertical blanking time are sequentially stored in the buffer memory.
In the second, third, and fourth operation modes, processing is performed in units of one packet, so the second, third, and fourth operation modes are repeated for each packet, and the second, third, and fourth operation modes are processed for every packet. When the fourth operation mode is executed, the correction ends.

When the data of all the packets are thus corrected and stored in the buffer memory, a status signal 63 is generated to inform the CPU that it may read the contents of the buffer memory.

The explanation will be given below in order starting from the first operation mode.

FIG. 4 is for explaining the first operation mode and shows the timing of packet reception data in the case of Japanese character code broadcasting. 10 in Figure 4
0 is horizontal synchronization signal, 101 is color burst, 1
02 is a 16-bit clock line in for clock synchronization, 103 is a framing signal for frame synchronization, and 104 is a 272-bit data bit which forms the serial reception data 31. The data transfer circuit 30 receives a framing detection signal 32 indicating that frame synchronization has been established by the framing signal 103, and can know the start timing of serial reception data. The received synchronous clock 33 is received.

For character code broadcasting outside of Japan or for other purposes, packet data is not limited to 272 bits.
272-n bits (n is an integer including 0), and the packet data is not necessarily transmitted during the vertical blanking time, nor is it transmitted in the format shown in Figure 4. Probably. However, for any of these applications, a signal 32 indicating the start time of serially received data and a synchronization clock 33 are necessary.

As mentioned above, the synchronous clock 33 is supplied so that during the time period of 272-n data bits,
Serial reception data 31 is sequentially taken in by a synchronous clock 33 and serial-to-parallel converted. If the capacity of the local data bus 23 is 8 bits, each time 8 bits of serial reception data arrive, it is sent to the local data bus. If the starting address of the buffer memory area that stores uncorrected data of a certain packet is address α, the data transfer circuit 30 will automatically send the address update signal 67 to the address generation circuit 25 every time 8-bit data is sent. The address signals are α+1, α+2, α+3,...
Step by step as follows. Also, each time these 8-bit data are sent out, the write pulse signal 59 is sent to the write pulse signal 6 via the timing control circuit 27.
It is supplied to the buffer memory 29 as 0. 1st
In the operation mode, the data bus control circuit 22
works to separate 20 and 23, so
The data bus of the CPU may be used for other purposes, and the address switching circuit 24 selects the automatic address signal 26 supplied from the address generation circuit 25 from among the two input signals to address the buffer memory 29. It operates to transmit information to the input terminal.

In this way, serial reception data 31 of 1 packet = 272-n bits are serial-parallel exchanged and sequentially written into buffer memory 29 starting from address α. FIG. 5 shows an operational flow for storing one packet of received data in the buffer memory 29. If 8 bits = 1 byte are processed and written, one packet is (272-n)/8 (if (272-n)/8 is not an integer, it is larger than (272-n)/8, and The closest integer value) times, for example, if n = 0 (in the case of Japanese character code broadcasting), 34 times, n =
If it is 8, it will be repeated 33 times, if n=16, it will be repeated 32 times, and the stored address will be α+(272-n)/8 from address α.
(If (272-n)/8 is an integer, then (272-n)/
(the nearest integer value greater than 8) - 1 address.

In Japanese character code broadcasting, up to 12 packets of data can be transmitted during one vertical blanking period. 61 in Figure 2 is a vertical blanking signal in the case of Japanese character code broadcasting, but more generally it is a signal indicating that a single packet or a series of multiple packet data is being input serially. . In the case of Japanese character code broadcasting, 62 is a horizontal synchronization signal (or horizontal blanking signal), but more generally it is a signal that indicates the interval between one packet data time and the next packet data time, that is, the transition point of a packet. This is a signal indicating. The address generation circuit 25 counts 62 while the signal 61 is being applied to generate a partial signal of the automatic address signal 26. When the data transfer for one packet is completed, 62 arrives, and by counting this, the address is switched to the address where the uncorrected data of the next packet is to be stored. Similarly, the flow shown in Figure 5 is repeated the desired number of times (12 times in Japanese character code broadcasting) to obtain uncorrected data for multiple packets of one series (12 packets in Japanese character code broadcasting). is stored in the buffer memory 29. In the case of Japanese character code broadcasting, an example of the correspondence between a packet number and an address for storing uncorrected packet data of that packet number is as shown in FIG. As the data area for one packet, 34 addresses would be sufficient even if n=0, but in order to simplify the configuration of the address generation circuit, 64 addresses are reserved in FIG. 6.
Therefore, of the 64 addresses in the data area of one packet, the latter 30 addresses are unused. When all packets of uncorrected data are written into the buffer memory, the signal 61 in FIG. 2 ends, and the first operation mode ends.

When the signal 61 ends, the second operating mode is entered.

In the second operation mode as well, the data bus control circuit 22 in FIG. It operates to supply the address input terminal. Also, address generation circuit 2
5 updates the address in response to an address update signal from the timing control circuit 27. In the second operation mode, the uncorrected packet data stored in the buffer memory as shown in FIG. data 35
is generated and supplied to the first data input terminal of the data selection circuit 56. The data selection circuit 56 selects between the pre-correction data 35 given to the first data input terminal and the post-correction data 55 given to the second data input terminal in response to a data selection signal 57 supplied from the timing control circuit 27. It operates in such a way as to select one and supply it to the data input terminal of the data register 34, but in the second operation mode, the uncorrected data 35 is selected and supplied to the data register 34.

Furthermore, the uncorrected data 35 is stored in the load gate circuit 3.
8 to the first input terminal of the adder 37 and, in turn, to the syndrome register 36 . One read from buffer memory 29 transfers 8 bits (272-n)/8((272-n)/
If 8 is not an integer, one packet of data is parallel-to-serial converted and loaded into the data register 34 and the syndrome register 36 by (272-n)/8 (the nearest integer) times. however,
Of the 272-n bits of data, only 190-n bits of information bit data are loaded into the data register 34. Error detection can be performed using the syndrome register thus formed. That is, if the syndrome register signal 40 is all "0", there is no error in the data, and on the other hand, if any bit is "1", there is an error in the data. If there is no error, the third operation mode may not be performed and the fourth operation mode may be performed.

The basic error correction method of this embodiment is as explained in Japanese Patent Application No. 58-6579, and the point that correction is performed by sequentially lowering the threshold value is explained in Japanese Patent Application No. 58-54002. That's exactly what was said.

The second operation mode and the third operation mode are sequential, and when the second operation mode ends, that is, data loading to the data register 34 and the syndrome register 36 is completed, the third operation automatically starts. Enter the mode.

In the third operation mode, two correction clocks 48 and 50 are generated from the timing control circuit 27, and the syndrome register 36 generates two correction clocks 48 and 50, respectively.
and data register 34. The load gate circuit 38 is turned off, while the data selection circuit 56 selects the corrected data 55 and supplies it to the data register. In addition, the collect date circuit 51
turns on. The first correction clock 48 outputs 272 clock pulses for each correction to cycle through the syndrome, and the second correction clock 5
0 circulates through the data register by issuing 190 clock pulses for each correction.

Error correction is performed by an exclusive OR circuit (modulo 2 adder) 54. The error correction signal 53 is output by forming 17 linear combinations of the 82 states of the syndrome register, and comparing the 17 states with a threshold value (the first threshold value is 17) by the majority circuit 41. be. However, this error correction signal 53 is configured to pass only during an error correction operation in response to the collect gate signal 52. Additionally, the error correction signal 53 modifies the syndrome register 36 to remove the effect of that bit when there is an error in that bit. The corrected data 55 is fed back to the data input terminal of the data register 34 via the data selection circuit 56.

Note that, prior to correction, the syndrome register 36 is incremented by one bit. This is because the majority code (273, 191) was chosen as the error correction code and one bit was reduced to make it the (272, 190) code.

In this way, by shifting 273 bits in the syndrome register and 190 bits in the data register, 190 information bits, excluding 82 parity bits, of the 272 data bits in one packet are restored. At this time, by checking the error status signal 65, it can be determined whether or not error correction has been performed correctly. If all the bits in the syndrome register 36 are not "0", it means that an error still exists in one of the bit positions.
The error correction operation is performed again. However, at this time, the threshold value clock 44 is given from the timing control circuit 27, and the threshold value generation circuit 43 subtracts and counts this, so that the threshold value is decreased by 1. That is, the threshold value is set to 16, and data after error correction is performed using the previous threshold value of 17 is used.

The above operations are performed until the threshold value 9 is reached. However, when all bits of the syndrome register 36 become "0" during the process, the error correction operation is completed. That is, since the data at that point is a correct value, there is no need to pass it through the error correction circuit thereafter.

As explained above, when the third operation mode ends, corrected data (information bits) is secured in the data register 34. When the third operating mode ends, the fourth operating mode is automatically entered.
In the fourth operation mode, the corrected data is serial-parallel converted and stored in the buffer memory 29. Second
In the figure, 70 is the 190th bit signal of the data register, 71 is, for example, the 182nd bit signal, and 72 is, for example, the 174th bit signal. The output data selection signal 74 corresponds to the reduction bit number designation signal 69, and is a signal for selecting one of 70, 71, and 72 depending on the specified reduction bit number. If the number of shortened bits n=0 (that is, a code of 272 data bits) is specified, the output data selection circuit 73 selects 70 and supplies it to the data transfer circuit 30, or the number of shortened bits n=0. 8 (i.e.
If the data bit is specified as a 264-bit code, 71 is selected and the data transfer circuit 30
72 is selected and supplied to the data transfer circuit 30 if the number of shortened bits n=16 (that is, a 256-bit code) is specified. This is done because the 190-bit data register is filled with corrected information only from the 1st bit to the 190-nth bit. Reference numeral 76 is a sending clock for shifting 190-n bit data and sending it to the data transfer circuit, and a clock pulse of 190-n is given to it. The corrected output data supplied to the data transfer circuit 30 is serial-parallel converted and sent to the buffer memory 29 via the local data bus 23, but an address update signal 66 is generated every time 8 bits are sent, and an automatic address signal is generated. 26 and write pulse 60 is updated to buffer memory 2.
9. Address switching circuit 24 selects automatic address signal 26 and buffer memory 29
Supplied to the address input terminal of Therefore, the corrected output data that has been corrected is written into the buffer memory 29 in units of 8 bits.

As disclosed in Japanese Patent Application No. 58-90017, in Japanese character code broadcasting, the beginning of 272-bit packet data is an 8-bit SI/IN indicating service identification and interrupt priority using (8, 4) expanded Hamming code. However, next, a 6-bit packet control (PC) is used to identify the packet content.
followed by 22 bytes of pure information bits. Therefore, if the corrected data is packed 8 bits at a time, the first 2 bits of each byte will become 1.
It will be mixed into the data section before the byte. In order to avoid this problem, in this embodiment, the patent application
Similar to 90017, 2 additional bits are added to the PC information to make it 8 bits. Therefore, in the case of Japanese character code broadcasting, 24 bytes of data per packet are stored in the buffer memory as corrected data. More generally, (190-n)/8 (if (190-n)/8 is not an integer, then the closest integer greater than (190-n)/8) bytes are written to buffer memory.

Note that in the fourth operation mode as well, the data bus control circuit 22 operates to separate 20 and 23, so the CPU may perform other operations.

As explained above, the second, third and fourth operation modes are a series of operations regarding one packet of data. That is, one packet of uncorrected data is read out from the buffer memory 29 and stored in the syndrome register 36 and data register 34.
(second operation mode), performs error correction (third operation mode), and writes one corrected packet of data to buffer memory 29 (fourth operation mode).
mode of operation).

Taking the case of Japanese character code broadcasting as an example, the corrected data is stored in the buffer memory 2 as shown in Figure 7.
It is stored in 9.

When all the corrected data of the packets are stored in the buffer memory 29 in this manner, the timing control circuit 27 issues a status signal 63 to indicate to the CPU that the buffer memory 29 may be read from the CPU.

In the fifth operating mode, the CPU sends the status signal 6
This is a mode in which the CPU reads out the contents of the buffer memory 29 upon detecting the buffer memory 29. In this mode,
The CPU provides a data request signal 68 to the timing control circuit 27. This causes the timing control circuit 27 to connect the CPU data bus 20 and the local data bus 23, and also disables the automatic address signal 26 to connect the CPU data bus 20 and the local data bus 23.
The signal of the address bus 21 is transferred to the buffer memory 29.
A bus control signal 28 is applied to the address input terminal of the bus.

In this way, the output data of the buffer memory 29 is obtained via the local data bus 23 to the data bus 20 of the CPU, so that the CPU can read data from an area of the buffer memory arbitrarily specified.

As explained above, in the first embodiment, by taking out outputs from different bit positions of the data register 34, data of a specified number of shortened bits can be corrected and stored in the buffer memory.

FIG. 8 shows a circuit diagram of a second embodiment of the invention. In FIG. 8, 20 to 69 are the same as in FIG. 2, and 70 is the 190th bit output signal of the data register 34, which is the correction completion data.
The output gate circuit 77 is the timing control circuit 27
This is for controlling whether or not the corrected completed data 70 is passed or prohibited by an output gate signal 78 supplied from the output gate signal 78 , and the corrected output data 75 that has been passed is supplied to the data transfer circuit 30 .
Further, 79 is a sending clock signal for sending out corrected data similar to 76 in FIG. 2, but it generates 190 clock pulses regardless of the number of shortened bits n.

The operation of the second embodiment is equivalent to that of the first embodiment in the first to third and fifth operation modes.

That is, in the second operation mode, a clock pulse of 190-n is given as the second loading clock signal 49, and the data register 34 receives a clock pulse of 190-n.
190-n bits of uncorrected data are secured. In the third operation mode, 190 clock pulses are applied as the second correction clock signal 50 for each threshold value, and the data circulates through the data register 34 while being corrected for each threshold value. When the correction at the last threshold value is completed, the data register 34 is filled with the corrected data from the 1st bit to the 190-nth bit. In the fourth operation mode, the output signal of the data register 34 is sent out in order starting from the 190th bit, but the first n bits are empty signals. Output gate signal 7
8 is the first n to send in the fourth mode of operation
This is a signal for inhibiting output data for a period corresponding to bits. Thus, in the second embodiment, the corrected data of the specified number of shortened bits n can be sent out and stored in the buffer memory 29 without switching and selecting a plurality of output signals of the data register 34.

In the first embodiment, an example was explained in which the correction completion data is taken out as a signal corresponding to the 190th-nth bit of the data register (assuming that n is switched) and is converted from parallel to serial in the data transfer circuit 30. As shown in FIG. 9 (third embodiment),
It is also possible to extract the data in 8-bit units as correction completion data. In FIG. 9, 70a, 71a and 72a are 8-bit correction completion data which are output signals from the 190-nth bit to the 190-n-7th bit. 70 by the output selection signal 74
A, 71a, or 70a is selected and supplied to the data transfer circuit 30 as corrected output data 75a. When corrected output data is supplied in 8-bit format in this manner, serial-to-parallel conversion is performed by simply latching at a predetermined timing in the data transfer circuit, which has the advantage of simplifying the circuit configuration.

In addition, in FIG. 2 and FIG. 9, an example is shown in which the number of shortening bits to be selectively switched is three, but a case in which selection can be switched in two or three or more ways is configured in the same way. be able to.

In the second embodiment (FIG. 8), the corrected data is taken out from the 190th bit of the data register 34 and serial-parallel converted into 8-bit data by the data transfer circuit 30, but as shown in FIG. It is also possible to extract the data from the 190th bit to the 183rd bit of the data register 34 as 8-bit data.
78 is an output gate signal equivalent to that in FIG.
By giving a signal to 8, 70b becomes 75
b and sent to the data transfer circuit 30. In this case, the data transfer circuit 30 can perform serial-to-parallel conversion to 8 bits simply by latching 75b at a predetermined timing, which has the advantage of simplifying the circuit configuration.

In the first to fourth embodiments described above, 8 bits are used as the bit capacity of the local data bus 23, and the buffer memory 29 and data transfer circuit 30
Although we have shown an example in which data is exchanged in units of 8 bits, other numbers of bits, such as 16 bits or 4 bits, are also possible.

In the above embodiment, the data register has a 190-bit configuration, but a 191-bit configuration can also accommodate (273, 191) codes. Alternatively, it is sufficient to have the number of bits equal to the maximum number of information bits to be selectively switched as a data register.

Further, in the above embodiment, an example was described in which the threshold value for majority decision is changed from 17 to 9, but the gist of the present invention is not limited to specific values such as 17 and 9. Furthermore, in the above embodiment, the fifth operation mode is not entered until the correction is completed and the status signal 63 is generated. It may be configured to enter the operating mode.

(Effects of the Invention) As explained above, according to the present invention, it is possible to specify the number of information bits of data to be corrected, and the correction operation is performed according to the specified number of information bits.
Since the corrected data is then transmitted, it is possible to correct errors in various numbers of information bits.

The present invention can be applied not only to a receiver for Japanese character code broadcasting, but also to other majority code decoding circuits.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of the prior art, FIG. 2 is a circuit diagram of a first embodiment of the present invention, and FIGS. 3 and 5 are flowcharts for explaining the operation of an embodiment of the present invention. FIG. 4 is a timing diagram for explaining the operation of one embodiment of the present invention, FIGS. 6 and 7 are mapping diagrams of buffer memory, and FIG. 8 is a circuit diagram of a second embodiment of the present invention. FIG. 9 is a circuit diagram showing a third embodiment of the invention, and FIG. 10 is a circuit diagram showing a fourth embodiment of the invention. 1...CPU bus line, 2...Output port,
3...Input port, 4...Error correction circuit, 5...
Data before correction, 6...Data after correction, 7...Start signal, 8...Load signal, 9...Collect signal, 10...Ready signal, 20...CPU data bus, 21...CPU address bus , 22
... Data bus control circuit, 23 ... Local data bus, 24 ... Address switching circuit, 25 ... Address generation circuit, 26 ... Automatic address signal, 2
7... Timing control circuit, 28... Bus control signal, 29... Buffer memory, 30... Data transfer circuit, 31... Serial reception data, 32...
A signal indicating that frame synchronization has been established, 33...
...Synchronization clock, 34...Data register, 35
... Data before correction, 36 ... Syndrome register, 37 ... Adder, 38 ... Load gate circuit, 39 ... Load gate signal, 40 ... Syndrome register signal, 41 ... Majority circuit, 42
...Threshold signal, 43...Threshold generation circuit, 44...
Threshold clock, 45... Clear signal, 46... First loading clock signal, 47... Load end signal, 48... First correction clock signal, 4
9...Second loading clock signal, 50...Second correction clock signal, 51...Collect gate circuit, 52...Collect gate signal, 53...
Error correction signal, 54...Adder, 55...Data after correction, 56...Data selection circuit, 57...Data selection signal, 58...Clock signal, 59...Write pulse, 60...Write pulse, 61 ... Vertical blanking signal or signal similar to vertical blanking signal, 62 ... Horizontal synchronization signal or horizontal blanking signal, 63 ... Status signal, 64 ...
Register, 65...Error status signal, 6
6, 67...address update signal, 68...data request signal, 69...shortening bit number designation signal, 70, 71, 72...correction completion signal, 73...
... Output data selection circuit, 74 ... Output data selection signal, 75 ... Correction output data, 76 ... Sending clock signal, 77 ... Output gate circuit, 78 ...
...Output gate signal, 79...Clock signal for sending out.

Claims (1)

[Claims] 1 Information bits are k bits, parity bits are l
- Specification for specifying that the (l, k) code, which is a code in which k bits of data bits are l bits, is shortened by n bits, which is an integer value including 0, to k−n bits as information bits. m of less than k bits having an input means, a syndrome register of l-k bits, and a plurality of bit outputs;
a bit data register; a majority circuit; means for loading k-n bits of uncorrected information bit data designated by the designation input means into the m-bit data register; and a signal from the designation input means. and an output data selection circuit that selects and outputs one of the plurality of bit outputs of the m-bit data register, and corrects errors in code data based on a majority error correction method using a difference set cyclic code. An error correction decoding circuit that corrects 2 Information bits are k bits, parity bits are l
The (l,k) code, which is a code with l bits of data bits, is shortened by n bits, which is a positive integer value including 0, and is used as information bits.
a designation input means for designating n bits; a l-k bit syndrome register; an m-bit data register of k bits or less; a majority circuit; - means for loading uncorrected information bit data of n bits into the m bit data register, and m-(k
-n) means for inhibiting the output signal of the m-bit data register for a time corresponding to n bits; the error correction method corrects errors in code data based on a majority error correction method using a difference set cyclic code; decoding circuit. 3 Information bits are k bits, parity bits are l
- k bits, to specify that the (l, k) code, which is a code with l bits of data bits, is shortened by n bits, which is an integer value including 0, to make k-n bits as information bits. a designated input means; a syndrome register of lk bits; a data register of m bits less than or equal to k bits having a plurality of consecutive plural bit outputs; a majority circuit; - means for loading n-bit uncorrected information bit data into the m-bit data register; an output data selection circuit that selects and outputs one continuous multi-bit output; and an error correction decoding circuit that corrects errors in coded data based on a majority error correction method using a difference set cyclic code. 4 Information bits are k bits, parity bits are l
- k bits, the (l, k) code, which is a code with l bits of data bits, is shortened by n bits, which is a positive integer including 0, and becomes k-n information bits.
a designation input means for designating that the data is a bit, a syndrome register of l-k bits, a data register of m bits less than or equal to k bits and having an output of a plurality of consecutive bits, a majority circuit, and the designation input means. specified by k−n
means for loading uncorrected bit information bit data into the m-bit data register; and m-(k
-n) means for inhibiting the output signal of the m-bit data register for a time corresponding to n bits; Correction decoding circuit. 5. The error correction decoding circuit according to claim 1, 2, 3, or 4, characterized in that l=273 and k=191.