JPH0141260Y2 - - Google Patents
Info
- Publication number
- JPH0141260Y2 JPH0141260Y2 JP1983178608U JP17860883U JPH0141260Y2 JP H0141260 Y2 JPH0141260 Y2 JP H0141260Y2 JP 1983178608 U JP1983178608 U JP 1983178608U JP 17860883 U JP17860883 U JP 17860883U JP H0141260 Y2 JPH0141260 Y2 JP H0141260Y2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- video signal
- period
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000605 extraction Methods 0.000 claims description 7
- 230000001934 delay Effects 0.000 claims description 3
- 239000002131 composite material Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
Description
【考案の詳細な説明】
産業上の利用分野
本考案は映像信号の信号対雑音比改善回路に係
り、特に映像信号の垂直相関性を利用して信号対
雑音比の改善された映像信号を出力する回路に関
する。[Detailed description of the invention] Industrial application field The present invention relates to a circuit for improving the signal-to-noise ratio of a video signal, and in particular, outputs a video signal with an improved signal-to-noise ratio by utilizing the vertical correlation of the video signal. related to circuits.
従来技術とその問題点
従来より、例えばヘリカルスキヤンニング方式
VTRの輝度信号再生系には、再生輝度信号を1H
遅延する遅延回路と、この遅延回路の入力再生輝
度信号と出力遅延再生輝度信号とを夫々加算する
加算回路とよりなる回路が設けられているものが
あつた。これにより、上記の加算回路からは映像
信号成分が入力複合映像信号の２倍であり、か
つ、雑音成分が入力複合映像信号中に含まれてい
た雑音が垂直相関がないために√２倍である映像
信号、すなわち信号対雑音比（以下「Ｓ／Ｎ比」
と記す）が３〓改善された映像信号が取り出され
る。Conventional technology and its problems Traditionally, for example, helical scanning method
The brightness signal reproduction system of the VTR uses 1H of the reproduced brightness signal.
Some devices are provided with a circuit including a delay circuit that delays and an adder circuit that adds the input reproduction luminance signal and the output delayed reproduction luminance signal of the delay circuit, respectively. As a result, the video signal component from the above adder circuit is twice the input composite video signal, and the noise component is √2 times the input composite video signal because the noise contained in the input composite video signal has no vertical correlation. A certain video signal, i.e., signal-to-noise ratio (hereinafter referred to as "S/N ratio")
) is 3 = An improved video signal is extracted.
しかるに、上記の従来回路は映像信号の相隣る
１水平走査期間間隔の情報は極めて近似性が強い
という垂直相関性を利用してＳ／Ｎ比改善を図る
回路であるから、入力映像信号に垂直相関性が無
い場合は出力映像信号に誤差を生じていた。 However, since the above-mentioned conventional circuit is a circuit that aims to improve the S/N ratio by utilizing the vertical correlation in which the information of adjacent horizontal scanning period intervals of the video signal is extremely similar, the S/N ratio is improved. When there is no vertical correlation, errors occur in the output video signal.
ところで、最近実用化された文字放送において
は、複合映像信号の垂直帰線消去期間内に文字信
号が重畳されて伝送されることは周知の通りであ
る。上記の文字信号は文字又は図形に関するデイ
ジタルデータ（画素データ）に、受信機で再生す
るときに必要な同期符号を付加してなるデイジタ
ル信号であり、奇数フイールドでは第１図Ａに
a1，a2で示す如く垂直帰線消去期間内の第16走査
線と第21走査線の計2H区間に重畳されて伝送さ
れ、また偶数フイールドでは同図Ｂにb1，b2で示
す如く、垂直帰線消去期間内の第279走査線と第
284走査線の計2H区間に重畳されて伝送される。 By the way, it is well known that in text broadcasting, which has recently been put into practical use, text signals are superimposed and transmitted within the vertical blanking period of a composite video signal. The above character signal is a digital signal obtained by adding a synchronization code necessary for reproduction by a receiver to digital data (pixel data) related to characters or figures.
As shown by a 1 and a 2 , it is superimposed and transmitted in a total of 2H intervals of the 16th scanning line and 21st scanning line within the vertical blanking period, and in the even field, as shown by b 1 and b 2 in B of the same figure. As shown, the 279th scan line and the 279th scan line within the vertical blanking period
It is transmitted by being superimposed on a total of 2H sections of 284 scanning lines.
従つて、かかる文字信号が重畳された複合映像
信号が磁気テープに記録され、そしてこれを再生
した場合は、文字信号a1，a2，b1，b2とその前後
の1H期間の情報とは垂直相関性が全くないため、
前記した従来のＳ／Ｎ比改善回路の出力映像信号
中の文字信号は誤つたデータ値で取り出してしま
い、正常な文字や図形を表示させることができな
いという問題点があつた。 Therefore, when a composite video signal on which such character signals are superimposed is recorded on a magnetic tape and played back, the character signals a 1 , a 2 , b 1 , b 2 and the information of the 1H period before and after them are Since there is no vertical correlation at all,
There was a problem in that character signals in the output video signal of the conventional S/N ratio improvement circuit described above are extracted with incorrect data values, making it impossible to display normal characters and figures.
そこで、本考案は垂直帰線消去期間中は入力映
像信号をそのまま通過することにより、上記の問
題点を解決した映像信号の信号対雑音比改善回路
を提供することを目的とする。 SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit for improving the signal-to-noise ratio of a video signal, which solves the above-mentioned problems by passing the input video signal as is during the vertical blanking period.
問題点を解決するための手段
本考案は、入力映像信号を１水平走査期間の自
然数倍の期間遅延する遅延回路を少なくとも有す
る垂直相関性を利用した雑音抽出回路と、一方の
端子に前記入力映像信号が供給される演算回路
と、入力映像信号の垂直帰線消去期間に略対応し
た期間の幅を有するスイツチングパルスを発生す
るスイツチングパルス発生回路と、スイツチング
パルスによりスイツチング制御され、スイツチン
グパルスのパルス幅に対応する期間は雑音抽出回
路の出力信号を上記演算回路の他方の端子への出
力を阻止し、パルス幅以外の期間は雑音抽出回路
の出力信号を前記演算回路の他方の端子へ出力す
るスイツチ回路とより構成したものであり、以下
その一実施例について第２図と共に説明する。Means for Solving the Problems The present invention includes a noise extraction circuit using vertical correlation that has at least a delay circuit that delays an input video signal for a period equal to a natural number multiple of one horizontal scanning period; an arithmetic circuit to which a video signal is supplied; a switching pulse generation circuit that generates a switching pulse having a period width approximately corresponding to the vertical blanking period of the input video signal; During a period corresponding to the pulse width of the processing pulse, the output signal of the noise extraction circuit is prevented from being output to the other terminal of the arithmetic circuit, and during a period other than the pulse width, the output signal of the noise extraction circuit is prevented from being output to the other terminal of the arithmetic circuit. It consists of a switch circuit for outputting to a terminal, and one embodiment thereof will be described below with reference to FIG. 2.
実施例
第２図は本考案になる映像信号の信号対雑音比
改善回路の一実施例のブロツク系統図を示す。同
図中、入力端子１に入来した、例えば記録媒体よ
り再生された映像信号（例えば輝度信号）は、
1H遅延回路２に供給されここで１水平走査期間
1H遅延される一方、減算回路３及び４に夫々供
給される。減算回路３は入力映像信号から1H遅
延回路２の出力複合映像信号を減算する動作を行
なう。従つて、減算回路３からは入力映像信号中
の垂直相関性が無い映像信号成分と、垂直相関性
が無い雑音とよりなる信号が取り出され、次段の
スイツチ回路５に供給される。Embodiment FIG. 2 shows a block diagram of an embodiment of a circuit for improving the signal-to-noise ratio of a video signal according to the present invention. In the figure, a video signal (for example, a luminance signal) inputted to the input terminal 1 and reproduced from a recording medium, for example,
1H delay circuit 2 where 1 horizontal scanning period
The signals are delayed by 1H and supplied to subtraction circuits 3 and 4, respectively. The subtraction circuit 3 performs an operation of subtracting the output composite video signal of the 1H delay circuit 2 from the input video signal. Therefore, a signal consisting of a video signal component having no vertical correlation in the input video signal and noise having no vertical correlation is extracted from the subtraction circuit 3 and supplied to the switch circuit 5 at the next stage.
一方、入力端子１に入来した映像信号は垂直同
期信号分離回路６に供給され、ここで複合同期信
号が分離された後積分回路を通されることにより
垂直同期信号が分離出力される。この垂直同期信
号は波形整形回路７に供給され、ここで波形整形
された後スイツチングパルス発生回路８に供給さ
れる。スイツチングパルス発生回路８は、例えば
単安定マルチバイブレータ等から構成されてお
り、入力映像信号の垂直帰線消去期間に対応した
期間のパルス幅を持つパルスを発生する回路で、
その出力パルスをスイツチングパルスとしてスイ
ツチ回路５へ印加する。 On the other hand, the video signal input to the input terminal 1 is supplied to a vertical synchronizing signal separation circuit 6, where the composite synchronizing signal is separated and then passed through an integrating circuit to separate and output a vertical synchronizing signal. This vertical synchronizing signal is supplied to a waveform shaping circuit 7, where the waveform is shaped, and then supplied to a switching pulse generation circuit 8. The switching pulse generation circuit 8 is composed of, for example, a monostable multivibrator, and is a circuit that generates a pulse having a pulse width of a period corresponding to the vertical blanking period of the input video signal.
The output pulse is applied to the switch circuit 5 as a switching pulse.
スイツチ回路５は上記のスイツチングパルスの
パルス幅の期間、すなわち垂直帰線消去期間はオ
フとされて、減算回路３よりの信号の通過を阻止
し、他方、上記のスイツチングパルスのパルス幅
以外の期間、すなわち、映像期間はオンとされて
演算回路３よりの信号を通過させて減算回路４へ
供給する。 The switch circuit 5 is turned off during the pulse width period of the above-mentioned switching pulse, that is, the vertical blanking period, to prevent the passage of the signal from the subtraction circuit 3, and on the other hand, during the pulse width period of the above-mentioned switching pulse, During the period, that is, the video period, the signal from the arithmetic circuit 3 is passed through and supplied to the subtraction circuit 4.
なお、第２図では図示は省略したが、減算器３
から演算回路４に到る伝送路中に係数回路が設け
られ、減算回路３よりの信号に所定の係数が付与
されることは周知の通りである。 Although not shown in FIG. 2, the subtracter 3
As is well known, a coefficient circuit is provided in the transmission path from the subtraction circuit 3 to the arithmetic circuit 4, and a predetermined coefficient is assigned to the signal from the subtraction circuit 3.
演算回路４は入力端子１よりの入力映像信号か
らスイツチ回路５の出力信号を減算する動作を行
なう。ここで、スイツチ回路５の出力信号は、前
記したように、映像期間内の雑音と垂直相関の無
い信号成分とからなる信号であるから、結局、演
算回路４の出力信号は、入力映像信号中の映像期
間の雑音が大幅に低減されてＳ／Ｎ比が改善され
た映像信号となり、出力端子９へ出力される。ま
た、入力映像信号の垂直帰線消去期間ではスイツ
チ回路５がオフとされるため、出力端子９には入
力映像信号の垂直帰線消去期間の信号がそのまま
出力される。 The arithmetic circuit 4 performs an operation of subtracting the output signal of the switch circuit 5 from the input video signal from the input terminal 1. Here, as described above, the output signal of the switch circuit 5 is a signal consisting of noise within the video period and signal components with no vertical correlation, so in the end, the output signal of the arithmetic circuit 4 is The noise during the video period is significantly reduced, resulting in a video signal with an improved S/N ratio, which is output to the output terminal 9. Further, since the switch circuit 5 is turned off during the vertical blanking period of the input video signal, the signal of the vertical blanking period of the input video signal is outputted as is to the output terminal 9.
本実施例によれば、垂直帰線消去期間では雑音
低減用の映像信号処理回路（回路２，３，４より
なる）の出力信号の代りに入力映像信号をそのま
ま出力するようにしたため、前記の文字放送信号
の如く、文字信号が垂直帰線消去期間内の特定の
期間に重畳されている映像信号が入力端子１に入
来した場合には、従来の如く文字信号を誤つて出
力することはない。なお、垂直帰線消去期間の信
号は、垂直同期信号、等化パルス、水平同期信号
などからなり、２値信号であり、また文字信号も
デイジタル信号であるから、雑音の低減処理を行
なわなくても実用上の問題は殆どない。 According to this embodiment, during the vertical blanking period, the input video signal is output as is instead of the output signal of the video signal processing circuit for noise reduction (consisting of circuits 2, 3, and 4). When a video signal, such as a teletext signal, in which a character signal is superimposed on a specific period within the vertical blanking period is input to the input terminal 1, the character signal cannot be erroneously output as in the past. do not have. Note that the signal during the vertical blanking period consists of a vertical synchronization signal, an equalization pulse, a horizontal synchronization signal, etc., and is a binary signal, and the character signal is also a digital signal, so it is not necessary to perform noise reduction processing. There are almost no practical problems.
応用例
なお、本考案は上記の実施例に限定されるもの
ではなく、例えば雑音抽出用の処理回路は垂直相
関性を利用した公知の回路をすべて使用でき、ま
た1H遅延回路２の代りに、nH（ただし、ｎは２
以上の整数）の遅延時間をもつ遅延回路を使用し
得る。更に、入力映像信号をそのまま出力する期
間は、垂直帰線消去期間内の、例えば垂直同期信
号の次の等化パルスの伝送終了直後から一定期間
であつてもよく、要は文字信号が伝送される期間
を含んでいればよい。Application Examples The present invention is not limited to the above-mentioned embodiments; for example, any known circuit that utilizes vertical correlation can be used as a processing circuit for noise extraction, and instead of the 1H delay circuit 2, nH (where n is 2
A delay circuit having a delay time of (an integer greater than or equal to) may be used. Furthermore, the period during which the input video signal is output as is may be a certain period within the vertical blanking period, for example, immediately after the transmission of the next equalization pulse of the vertical synchronization signal ends, and in short, the period when the character signal is transmitted. It is sufficient as long as it includes the period in which the
効 果
上述の如く、本考案によれば、雑音低減用の映
像信号処理回路によつて雑音が低減された出力映
像信号を入力映像信号の少なくとも映像期間中は
出力し、入力映像信号の略垂直帰線消去期間は入
力映像信号をそのまま出力するようにしたので、
文字放送信号等の如く垂直帰線消去期間内の特定
の期間に別の情報信号が重畳されているような映
像信号が入力された場合でも、上記の別の情報信
号を正確に伝送することができ、よつて文字放送
信号の場合は伝送された文字、図形を正確に表示
させることができる等の特長を有するものであ
る。Effects As described above, according to the present invention, the output video signal whose noise has been reduced by the noise reduction video signal processing circuit is output at least during the video period of the input video signal, and During the blanking period, the input video signal is output as is, so
Even when a video signal, such as a teletext signal, in which another information signal is superimposed during a specific period within the vertical blanking period is input, it is not possible to accurately transmit the other information signal. Therefore, in the case of teletext signals, the transmitted characters and figures can be displayed accurately.
第１図Ａ，Ｂは夫々文字放送信号を説明するた
めの信号波形図、第２図は本考案回路の一実施例
を示すブロツク系統図である。
１……映像信号入力端子、２……1H遅延回路、
３……減算回路、４……演算回路、５……スイツ
チ回路、６……垂直同期信号分離回路、８……ス
イツチングパルス発生回路、９……出力端子。
1A and 1B are signal waveform diagrams for explaining teletext signals, respectively, and FIG. 2 is a block system diagram showing an embodiment of the circuit of the present invention. 1...Video signal input terminal, 2...1H delay circuit,
3... Subtraction circuit, 4... Arithmetic circuit, 5... Switch circuit, 6... Vertical synchronizing signal separation circuit, 8... Switching pulse generation circuit, 9... Output terminal.
Claims (1)
間遅延する遅延回路を少なくとも有する垂直相関
性を利用した雑音抽出回路と、一方の端子に前記
入力映像信号が供給される演算回路と、該入力映
像信号の垂直帰線消去期間に略対応した期間の幅
を有するスイツチングパルスを発生するスイツチ
ングパルス発生回路と、該スイツチングパルスに
よりスイツチング制御され、該スイツチングパル
スのパルス幅に対応する期間は上記雑音抽出回路
の出力信号を上記演算回路の他方の端子への出力
を阻止し、該パルス幅以外の期間は該雑音抽出回
路の出力信号を前記演算回路の他方の端子へ出力
するスイツチ回路とより構成した映像信号の信号
対雑音比改善回路。 a noise extraction circuit utilizing vertical correlation having at least a delay circuit that delays an input video signal for a period equal to a natural number multiple of one horizontal scanning period; an arithmetic circuit to which the input video signal is supplied to one terminal; and the input video signal. A switching pulse generation circuit that generates a switching pulse having a period width approximately corresponding to a vertical blanking period of a video signal, and a switching pulse generating circuit that is controlled by the switching pulse and has a period corresponding to the pulse width of the switching pulse. a switch circuit that prevents the output signal of the noise extraction circuit from being output to the other terminal of the arithmetic circuit, and outputs the output signal of the noise extraction circuit to the other terminal of the arithmetic circuit during periods other than the pulse width; A circuit for improving the signal-to-noise ratio of a video signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17860883U JPS6085484U (en) | 1983-11-18 | 1983-11-18 | Video signal signal-to-noise ratio improvement circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17860883U JPS6085484U (en) | 1983-11-18 | 1983-11-18 | Video signal signal-to-noise ratio improvement circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6085484U JPS6085484U (en) | 1985-06-12 |
| JPH0141260Y2 true JPH0141260Y2 (en) | 1989-12-06 |
Family
ID=30387733
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17860883U Granted JPS6085484U (en) | 1983-11-18 | 1983-11-18 | Video signal signal-to-noise ratio improvement circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6085484U (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59101565U (en) * | 1982-12-27 | 1984-07-09 | 株式会社東芝 | Processing device for video signals including text information signals |
-
1983
- 1983-11-18 JP JP17860883U patent/JPS6085484U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6085484U (en) | 1985-06-12 |
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