JPH01318546A - Pulse width modulation stabilized power source and integrated circuit containing the same power source - Google Patents

Abstract

PURPOSE:To reduce a chip area and to cut down the price by being equipped with a holding means to hold an output signal of a comparison means, a low- pass filter and a timing means and by integrating them into the same chip. CONSTITUTION:A pulse width modulation stabilized power source is composed of a comparator 1, a timing generator 2, a multiplexer 3, a latch 4, a D/A converter 5, a RAM 6, a selector 7, a computing element 8, a MAIN PWM circuit 9, a control means 20 and a low-pass filter 30. Together with a microprocessor to control the operation of an image formation device, a memory, a timer, etc., they are integrated into the same chip for composition except the control means 20. This stabilized power source is equipped with two sorts of modes of the operation as an A/D converter and as a PWM control circuit. The operation as the PWM control circuit is compared with the output of the D/A converter 5 through the multiplexer 3 by the comparator 1 and is held to the latch 4. One of them is supplied to the above PWM circuit 9.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a pulse width modulation stabilized power supply suitable for image forming apparatuses such as copying machines and printers.

[Conventional technology]

Conventionally, the electrical components of image forming apparatuses such as copying machines and printers include a sequence controller circuit centered on a microprocessor that controls the entire printing sequence, and a DC
Various things, such as a power supply, an exposure power supply, and a high-voltage power supply for charging, etc., were independent. Therefore, there is a limit to miniaturization and cost reduction of this type of image forming apparatus.

Therefore, in order to form the above components on one board,
Microprocessor, RAM, ROM and digital peripheral circuits, as well as A/D converters.

There have been proposals to integrate a D/A converter, a PWM circuit for controlling a power supply system, etc. onto a single chip.

[Problem to be solved by the invention]

However, as described above, simply integrating each element increases the circuit scale, especially the circuit scale of the PWM circuit, and the overall chip area increases, making it difficult to reduce the price.

The present invention was made under these circumstances, and has the following points:
The object of the present invention is to provide a pulse width modulation stabilized power supply that requires a small chip area when integrated on a chip and can be manufactured at a low cost.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a pulse width modulation stabilized power supply and an integrated circuit including the power supply as follows (1) and (2).
).

(1) For a pulse width modulation stabilized power supply, there is a control means for controlling the output voltage or output current, a reference signal generation means, a reference signal from the reference signal generation means, and an output voltage or output current from the control means. a comparison means for comparing the output signal with a feedback signal proportional to the comparison means; a holding means for holding the output signal of the comparison means; and a low-pass filter for inputting the output signal of the holding means and outputting a control signal to the control means. , and timing means for causing each operation of the comparing means and the holding means to be performed at predetermined time intervals.

(2) The integrated circuit including the pulse width modulation stabilized power supply is controlled by the pulse width modulation stabilized power supply according to claim 1, together with a microprocessor that controls the operation of the image forming apparatus and peripheral digital circuits such as memory and timer. All parts except the means are integrated on the same chip.

[Effect]

The configuration (1) allows control using pulse width modulation with a simple circuit configuration, and the configuration (2) allows the circuit scale of the entire control circuit of the image forming apparatus including the pulse width modulation circuit to be reduced.

(Example) The present invention will be explained below with reference to Examples.

FIG. 1 is a block diagram of the main parts of a "pulse width modulation stabilized power supply" which is a first embodiment of the present invention, FIG. 2(a) is a block diagram of the same embodiment, and FIG. 2(b) is a block diagram of the same embodiment. The circuit diagram of the comparator used in the same example, FIG. 2 (C) is the MA used in the same example.
A block diagram of the I N -PWM circuit and FIG. 3 are timing charts of the same embodiment.

This pulse width modulation stabilized power supply includes an A/D converter and a PW
M (Pulse Idth Modulation
n, pulse width modulation) There are two modes of operation as a control circuit.

In FIG. 2(a), 1 is a comparator, 3 is a multiplexer (M
PX circuit), 4 is a latch having a plurality of latch means, 5
is a D/A converter, 2 controls the timing of each block,
A timing generator that changes the timing speed depending on the type of multiplexer output.

The operation will be explained with reference to the timing chart in FIG.

The MPX circuit 3 is switched so that the timing generator 2 inputs external detection data (external input) as a comparison value. By turning on SWI and SW3 and turning off SW2 shown in FIG. 2(b), the detection value selected by the MPX circuit 3 is input to the comparator 1. At the same time D/
A conversion data is selected from the D/A conversion table on the RAM 6 and set in the D/A converter 5. Next, by turning on SW2 and turning off SWl and SW3, the value selected by the MPX circuit 3 is compared with the D/A conversion value of the comparison reference, and the result is held in the latch 4.

In FIG. 2(a), the selector 7 normally inputs the output of the arithmetic unit 8, selects it, and outputs it to the RAM 6.

The A/D converter compares the analog value of the external input selected by the MPX circuit 3 with the reference voltage from the D/A converter 5 using a comparator 1, and based on this result, determines the next standard to be compared with the input. The voltage is determined by the calculator 8 and compared with the analog value. The arithmetic unit 8 determines the reference voltage from the D/A converter 5 from the most significant bit to the least significant bit until the reference voltage from the D/A converter 5 comes closest to the input analog value, and when all bits are determined, the A/A converter 5 It is latched into register B as a D conversion value.

The operation as a PWM control circuit will be explained. MPX circuit 3
The comparator 1 compares the external input via the reference value with the output of the D/A converter 5, and the comparison result is sent to the latch 4.
to hold. One of the outputs of latch 4 is MA I N
-PWM circuit 9, others are SU B -PW
It is supplied to M circuits 13-15.

Data is exchanged between this pulse width modulation stabilized power supply and the CPU, each register 10 to 12 (register A
, register B, register C). Register A
is a register for setting data on the D/A conversion table. Register B sends the A/D conversion result to the CPU.
- This is a register for reading on BUS19. Register C is used for status settings such as A/D-D/A conversion operations and RA.
M6. MPX circuit 3. This register is used to set each address of the latch 4 and the like.

As described above, this pulse width modulation stabilized power supply has two modes: operation as a PWM control circuit and operation as an A/D converter, and the timing generator is a block that controls the timing of each operation. Yes, CPU-Bu
Data exchange with s is performed via each register.

FIG. 2(C) is a block diagram of the MAIN-PWM circuit used in this pulse width modulation stabilized power supply.

As mentioned above, the inputs of the multiplexer 3 are compared by the analog comparator 1, and the results are each held in the latch means of the latch 4. In the MAIN-PWM circuit, the results are held in one of the latch means. FLI
Input to P-FLOP21. Input analog
The comparison result of the comparator is that FLIP-FLOP21 has clock synchronization, the next stage (7) UP-DOUN (:0
UNTER22 (7) Input to UP/DOWN decision terminal. At this time, UP-DOUNCO mouth NTER
22 receives the initial value of the counter from the CPU-BUS 19 via the 4-bit register 25. The initial value is the UP/DOWN value of the FLIP-FLOP 21 for counting up and counting down, and the counting result is sent to the UP-COUNTER 23 at the next stage. The sent count value is read in synchronization with the LOAD signal of up-couNTER 23, and counting is started. Also,
The output signal of UP-C0UNTER23 is DIGITAL
-(: With OMPARETER24, CPU/BUS 1
9 to the value set in the 4-bit register 26, and the comparison result is output as a pulse width modulation (PWM) output result. In Figure 2 (C), UP-(:0UNT
The output of ER23 is connected to 7bit AND27, which is used to detect the end of counting, and the output of the synchronous circuit is logically summed with OR circuit 28 and UP-11:0U
It is input to the LOAD terminal of NTER23 and UP-(:0U
NTER23 up・00υN C0U based on this signal
Read the data of NTER22. Here, UP-DO
UN C0UNTER22 and UP-C0UNTER23
and DIGETAL-COMPARETER24 is 7bi
t configuration, and the necessary accuracy has been obtained.

Next, the main parts of the "pulse width modulation stabilized power supply" of this embodiment will be explained in the first section.

In the figure, A-1 is the MA I N -PWN circuit 9
By driving the main transistor A-13 and driving the primary side of the transformer A-10, an output A-11 is obtained from one winding on the secondary side. The output A-11 is voltage-divided and fed back as an A-3 signal to become one input of the MAX circuit 3. In addition, the output is taken out from the other winding on the secondary side of the transformer A-10 to A-12, which is a SUB-PWM output, and the low voltage side of the A-12 output is connected to a capacitor Cx1 with one side grounded. The other terminal of a certain A-8 is connected, and one is connected to a transistor T,...
A resistor Rx22. connected to the collector of A-5. The other terminal of A-7 is connected. Transistors T, X,, A-
The emitter of 5 is connected to a resistor Rx, one terminal of which is grounded.
Connected to the other terminal of A-6. Also, 1 of latch 4
The output A-2 is connected to the resistor Rx3. Transistor A-5 via a low-pass filter 30 consisting of capacitor CX2
Driving the base of. The emitter of the transistor, ie the high side of the resistor RxI, receives the feedback signal A-4.
As such, it becomes one input of the MPX circuit 3. In addition, A-
3, the feedback signal of A-4 is sent to the MPX circuit 3. An appropriate voltage division ratio is selected so that it falls within the operating range of comparator 1, etc., and it is pulled up to VCC or pulled down to GND with an appropriate resistor according to the polarity of A-11° and A-12.

Further, A-9 is a varistor and a current control resistor for protecting the transistor A-5 when the low voltage side A-12b of the output A-12 rises excessively. RAM6 contains A-11, A
-12 output setting values are stored. The circuit of transistor A-5 excluding the low-pass filter section is the control means 2.
It constitutes 0.

The operation of this embodiment will be described in detail below.

First, the timing generator 2 drives the MPX circuit 3 to select the A-3 input and inputs it to the comparator 1. At the same time, the address storing the setting value of the A-11 output is given to the RAM 6 and read out, and the D/A converter 5
Enter. The D/A converter 5 generates an analog voltage according to the input and uses it as the other input of the comparator 1.

In this way, in PWM operation, RAM 6 and D/A converter 5
functions as a reference signal generating means. The comparator 1 operates as described above to compare the output of the MPX circuit 3 and the output of the D/A converter 5, and outputs high or low depending on the magnitude.

At this time, the timing generator 2
- At the same time, a bit corresponding to the PWM circuit 9 is given to the latch 4, a latch signal is output, and the high level of the comparator l is
Latch the gh/low output.

The output of the latch 4 is connected as an input signal to the MA I N -PWM circuit 9 to the UP/DOWN selection input of the UP/DOWN counter in the MA I N -PWM circuit 9, as described above, resulting in pulse width modulation. MAIN
-The output A-1 of the PWM circuit 9 is the main transistor A
-13 and controls the A-11 output to a constant voltage. The above is the MA I N -PWM operation.

Next, the timing generator 2 drives the MPX circuit 3 to select the A-4 input and inputs it to the comparator 1. At the same time, the address storing the setting value of A-12 output is given to the RAM 6, read out, and inputted to the D/A converter 5. The D/A converter 5 converts the input value into an analog voltage, input to the other terminal.

Similarly to the above, the comparator 1 compares the two and generates a high/low signal depending on the magnitude, which is input to the latch 4. The latch 4 uses the signal from the timing generator 2 to select the bit corresponding to the A-2 output. Selected and latched. A-2 output connects transistor A-5 to resistor Rx3
is driven through a capacitor CX2 whose one side is grounded, and the operation described below is performed. The above is the operation of SUB-PWM.

The above operation is repeated as one cycle.

Assuming that this period is T, SUB-PWM becomes a pulse train that compares the set value and the output value every T and selects high/low. In other words, the high period is nT, 1ow
The period of time is mT (where n.

m is an integer).

Note that although this embodiment uses a two-output cadence, the present invention is not limited to this, and the same implementation can be performed using a scraped cadence.

Now, the A-12 output is stabilized as follows.

Low voltage side A-12b and high voltage side A-1 of A-12 output winding
2a controls the primary side of transformer A-10 with the feedback signal from output A-11, so A-11
Generates a voltage that follows the output of Assuming that the A-11 output is now in a steady state, A-12a and A-1
2b is a certain voltage V. It has become. At this time, the main part of the A-12 output was extracted and rewritten as an equivalent circuit, as shown in FIG. 4(a). In the same figure, the A-12 output voltage is V. Let the load impedance be R.

If the configuration is as shown in the figure, all the current flowing through the load RL will pass through the secondary winding side of the transformer and the transistor T r w I
, the A-4 voltage signal has a value proportional to the current flowing through the load RL. Since this value is fed back and compared with a reference value to become a pulse train of the A-2 signal, the present embodiment operates at a constant current.

Now, A-2 pulse train consists of resistor R83 and capacitor CM
The voltage is converted into a DC voltage by a low-pass filter 30 composed of 2. Let this DC voltage be Vd, and T r
Assuming that Xl is an ideal transistor, the current flowing through the load RL can be expressed as io'' (VdVBE)/RX+.

Therefore, the transistor T rX□ of this embodiment operates in the same way as a normal series regulator, and these operations are conceptually shown in FIG. 5.

Note that in reality, a ripple component that cannot be completely removed by the low-pass filter is superimposed on Vd, and i.

will include ripple current. For that reason, resistor Rx2
The output is stabilized by smoothing it with the filter of capacitor CXI.

In addition, Fig. 4(b) shows the SUB-PW according to another proposal.
This is an equivalent circuit of M circuit. In this circuit, since the configuration does not use a low-pass filter and the current flowing through the resistor Rx is intermittent, it is impossible to control the output current by extracting the feedback signal from the resistor Rx1. , in this embodiment, resistors Rx3. By using a low-pass filter consisting of capacitor CX2, the output current can be controlled with a simple configuration.

Furthermore, in this embodiment, if it is desired to reduce output ripples, it is sufficient to increase the time constant of the low-pass filter, but the response may become slow, for example, when it is desired to change the output rapidly.

In such a case, an analog switch and a resistor Rx4 are placed in parallel with the main filter resistor Rx3, and Rx3>>Rx
4, and if you want to make the response faster, turn the analog switch ON/L, rapidly change the output, and then turn the analog switch OFF to increase the time constant and obtain an output with small ripple. Analog switch ON1
0FF requires only 1 bit of port, and there is almost no increase in cost.

In the first embodiment described above, in SUB-PWM, constant current control is performed using a feedback signal proportional to the output current, but constant voltage control can also be performed using a feedback signal proportional to the output voltage.

FIG. 8 is a configuration diagram showing a "pulse width modulation stabilized power supply" according to a second embodiment of the present invention that performs constant voltage control.

As shown in the figure, the A-12 output is voltage-divided by a resistor voltage divider to form a feedback signal A-4, which is used as one input of the MAX circuit 3. With this configuration, a constant voltage output can be obtained between 8-12a and A-12b with the same operation as in the first embodiment.

One end of the resistive voltage divider is connected to Vc depending on the polarity of output A-12.
Pull up to c or pull down to GND.

FIG. 8 shows a microcomputer (microprocessor), peripheral memory, digital circuits such as a timer, a portion of the stabilized power supply of the first or second embodiment, excluding the control means, and the SUB-PWM2. An overall configuration diagram of an "integrated circuit" according to a third embodiment of the present invention in which circuits are integrated on the same chip is shown. This chip can perform most controls such as sequence control and power supply control for copying machines and printers.

The configuration of this integrated circuit is centered around the CPU-C0RE.
TA-MEMORY PROGRAM-MEMORY
INTERRUPT-(:0C with built-in NTROL etc.
PU-CoRE section 31 and a RESET function 32 including a standby function at low voltage in the periphery. IfATCHDOG TIMER33,C for monitoring program runaway
Digital based on PU information.

D/A converter that performs digital to analog conversion5. Also, D/A
An A/D conversion block that functions as an analog-to-digital converter by the converter 5 and the comparator circuit 1, a D/A converter/A/D conversion block, and a D/A-A/D controller 36 that controls each operation timing. Placed.

The A/D conversion block includes a multiplexer circuit (MPX circuit) 3 that performs input switching according to the operation timing of the D/A/A/D controller 36 at the stage before the A/D conversion in order to A/D convert a plurality of analog values. Built-in.

A/D conversion is used to read various voltages of a fixing thermistor of a copying machine, a volume for copy density adjustment, etc. D/A
The converter is used as a reference voltage for a comparator 1 in a pulse width modulation (PWM) circuit for fluorescent light dimming control, high voltage control, etc. of copying machines.

The development AC bias drive pulse generator includes a 4-bit frequency divider 35 for dividing the CPU internal clock, and a development AC bias drive pulse generator.
A 1/2 frequency divider 34 is used to set the duty of the C bias drive pulse to 50%.

Pulse width modulation (PWM) circuits 9, 13, 14, and 15 are used for low voltage power supply control, high voltage power supply, and fluorescent lamp dimming control.
- PWM circuit 9 is used, and the other PWM circuits are SUB/PWM circuits-3 to 15, which are configured so that the output result of the comparator directly becomes a PWM signal. In addition, the PWM circuit for low-voltage power supply control has a
The output output momentary shirt ladder 92 functions, and the input consists of a comparator 38, and when a certain specified value is exceeded, the PWM
The output is immediately turned off to protect the circuit and increase the safety of the copier.

The integrated circuit also includes an input boat 42 for inputting various sensor inputs, operation section key switch information such as copy start/copy number settings, motors, heaters, etc.
There are an output port 41 for controlling solenoids and the like, and an output port 39 for display LED drive.

Furthermore, a checker is connected to the main body of the copying machine in order to check the operation of the copying machine in factories, markets, etc., and there is also a serial communication boat 40 for this purpose.

In FIG. 8, D/A-A/D C0NT36 is
Timing generator 2 and RAM 6 in Fig. 2(a)
．． Selector 7, arithmetic unit 8. Contains portions corresponding to registers 10 to 12. For example, as shown below, the CPU is MAIN-
Data is set in each block to control each output of PWM and SUB-PWM.

Register A10. shown in FIG. 2(a). Register B11.
The register C12 and the 4-bit register 25.4-bit register 26 shown in FIG. 2(C) are each assigned an independent address in the case of the memory Matsubuto I10, and similarly, each is assigned an independent boat number in the case of the boat I10. be done.

Since the 4-bit registers 25 and 26 in FIG. 2C can be set independently, the CPU specifies the parameters that define the MAIN-PWM operation by addressing each register and setting a predetermined value. Further, the RAM that stores the D/A conversion values, that is, the MAIN and SUB PWM setting values and A/D conversion data, is composed of, for example, a shift register, and communicates with the CPU as shown below.

First, FIG. 9 shows the bit configuration of register C. Bits 0 to 3 are the designation No. of RAM6 in FIG. 2(a) or MP
X circuit 3 designation NO1, bit 4 is Read or WRIT
E is specified, and when it is Read, one of the 8ch inputs of the A/D MPX circuit 3 is set to RAM No. (bit 0).
~3) and stored in a latch in the timing generator 2. Also, in the case of WRITE, the address in RAMB to be D/A converted is RAMNo.

It is indicated by the value of (bits 0 to 3). Bit 5 is MAIN
- PWM, SUB - Specifies whether to output each PWM output. Bit 7 is a timing signal for communication between the CPU and timing generator. For example, when bit 7 is set to O or 61, bits 0 to 5 Data and register A
IO data becomes valid. Note that in the bit configuration, the RAM No. is divided into 4 bits of bits 0 to 3, but in this embodiment, there are 5 types of RAM 6 and 8 channels of external input, so 3 bits is actually sufficient.

The following procedure is used to set the output value of each PWM in RAMa. The CPU first addresses register AIO and writes data corresponding to the output it wants to set.

Next, address register C and set the RAM No. of the output you want to set in bits 0 to 3, for example, MA I N -PW.
The value of 0° for M and 1 for SUB-PWMO, and bi
Set t44 to WRITE state and further change bit from 0 to 1
and write it. In this embodiment, the RAM 6 has a shift register configuration as described above, so the timing generator 2 refers to the RAM No. of the register C12, and at the same time the data of the corresponding RAM No. is output to the D/A 5. The selector 7, which normally selects the arithmetic unit 8, is set to the register A side, and the data in the register A is written into the RAM 6 by the next shift clock. The selector 7 selects the data on the arithmetic unit 8 side again when the aforementioned shift clock ends. Here, the arithmetic unit 8 has an input, that is, a RAM
The output of the selector 6 is output as is and is input to the selector 7.

Through the above steps, the setting values for each PWM output can be set in the RAM 6. Also, to set the address for A/D conversion, the CPU addresses register C and sets the channel number for which A/D conversion is desired.

(0 to 7) are set to bits 0 to 3 (actually 0 to 2), bit 4 is set to Read, and bit 7 is changed from O to 1. Set the value of bito~3. The timing generator 2, at the timing when the channel number indicated by the latch should be A/D converted,
It is given to MPX circuit 3. At this time, the arithmetic unit 8 selects whether the bit data to be determined by the comparator result is 0 or 1.
output to selector 7. The arithmetic unit 8 sequentially sets 1 from the most significant bit, repeats the above-mentioned comparator operation, and rewrites the data in the RAM 6 until the least significant bit is determined. Then, at the stage when the least significant bit is determined, timing generator 2 gives a latch pulse to register B, and register B as A/D conversion data.
In order to perform the comparison operation again from the most significant bit, the arithmetic unit 8 sets only the most significant bit to 1 and sets the other bits to O
and writes it into the RAM 6 through the selector 7. CPU
can know the A/D conversion value by addressing and reading register B.

(Effects of the Invention) As described above, according to the present invention, a pulse width modulation stabilized power supply can be realized with a simple circuit, and when integrated on the same chip with other control units of an image forming apparatus, the chip area can be reduced. The cost of the entire device can be reduced.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of the main parts of the first embodiment of the present invention, and Figure 2 (a
) is a block diagram of the same embodiment, FIG. 2(b) is a circuit diagram of a comparator of the same embodiment, and FIG. 2(C) is a MA of the same embodiment.
A block diagram of the I N -PWM circuit, Fig. 3 is a timing chart of the same embodiment, and Fig. 4 (a) is a SUB-PW circuit.
The equivalent circuit of M circuit, Fig. 4(b) is another proposed SUB-P.
Equivalent circuit of the WM circuit, Fig. 5 is a conceptual diagram of the SUB-PWM circuit, Fig. 6 is a circuit diagram showing a modification of the SUB-PWM circuit, Fig. 7 is a configuration diagram of the second embodiment, and Fig. 8 is a schematic diagram of the SUB-PWM circuit. FIG. 9 is a diagram showing the bit configuration of the resist C according to the third embodiment. 2...-Timing generator 4...
Latch 5 ------- D/A converter 6 ------- RAM 20 ... Control means 30 ------- Low pass filter

Claims (2)

[Claims] (1) Comparing the control means for controlling the output voltage or output current, the reference signal generation means, the reference signal from the reference signal generation means, and the feedback signal proportional to the output voltage or output current from the control means a comparison means, a holding means for holding the output signal of the comparison means, a low-pass filter for inputting the output signal of the holding means and outputting a control signal to the control means; and timing means for performing each operation at predetermined time intervals. (2) The pulse width modulation stabilized power supply according to claim 1, except for the control means, is integrated on the same chip, together with a microprocessor that controls the operation of the image forming apparatus and peripheral digital circuits such as memory and timer. An integrated circuit containing a modulated regulated power supply.