JP2717662B2 - Pulse width modulation circuit and stabilized power supply using the circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a pulse width modulation circuit and a stabilized power supply using the circuit.

[Conventional technology]

2. Description of the Related Art Conventionally, in an image forming apparatus such as a copying machine and a printer, various components such as a sequence controller circuit centered on a microprocessor for controlling an entire print sequence, a DC power supply, an exposure power supply, and a high voltage power supply such as charging are provided independently. Had been. Therefore, there is a limit to reducing the size and cost of the apparatus.

Therefore, in order to form the components on one board, a microprocessor, a RAM, a ROM, a digital peripheral circuit, an A / D converter, a D / A converter, and a pulse width modulation circuit (hereinafter, referred to as a power supply system) for controlling a power supply system. PWM circuit)
Proposals have been made to integrate them on chips.

[Problems to be solved by the invention]

However, simply integrating each component on a single chip requires a large circuit scale, especially in a PWM circuit.
The chip area became large, and the effect of cost reduction was small.

The present invention has been made in view of such a point,
An object of the present invention is to provide a PWM circuit having a small circuit size and a small chip area, and a stabilized power supply using the PWM circuit.

[Means for solving the problem]

According to the present invention, in order to achieve the above object, the pulse width modulation circuit is configured as in the following (1), and the stabilized power supply is configured as in the following (2) and (3).

(1) An input section for inputting an analog signal, an analog comparator for directly inputting the analog signal from the input section and comparing the input value with a reference value, and storing a comparison result of the analog comparator, and pulse width modulation of the stored data. , A pulse width modulation means for outputting a pulse width modulated signal in accordance with the control signal from the storage means, and a constant value for each of the input section, the analog comparator, and the storage means. Timing signal generating means for repeatedly outputting a timing signal every time; and the input unit outputs an analog signal input to the analog comparator according to a timing signal from the timing signal generating means, and the analog comparator Is the ratio according to the timing signal from the timing signal generating means. Performs an operation, pulse width modulation circuit for performing a memory operation in response to a timing signal from said memory means a timing signal generating means.

(2) A power supply circuit, an input section for inputting an analog signal proportional to the output of the power supply circuit, and an analog signal from the input section directly input and compared with a reference value corresponding to a target output of the power supply circuit. An analog comparator; storage means for storing a comparison result of the analog comparator; and outputting the stored data as a control signal for pulse width modulation; and a power supply for outputting a signal pulse-width modulated according to a control signal from the storage means. Pulse width modulation means for outputting a control signal for a circuit; and timing signal generation means for repeatedly outputting a timing signal to the input section, the analog comparator, and the storage means at regular time intervals. Converts the analog signal input according to the timing signal from the timing signal generating means into the analog Output to over data, the analog comparator performs a comparison operation in response to a timing signal from the timing signal generating means, regulated power supply the storage means for performing storage operation in response to a timing signal from the timing signal generating means.

(3) The power supply circuit has a series circuit of a resistor and a transistor connected in series to a secondary winding circuit of a transformer, and a capacitor connected in parallel to the series circuit. The stabilized power supply according to (2), wherein the output of the line circuit is input, and the pulse width modulation means controls the transistor.

[Action]

With the above-described configuration, the circuit scale of the PWM circuit can be reduced, and the chip area can be reduced. Also, the circuit scale of the PWM circuit, which is the control circuit of the stabilized power supply, can be similarly reduced to reduce the chip area. Become.

〔Example〕

 Hereinafter, the present invention will be described with reference to examples.

In describing the embodiment, the entire control system of the image forming apparatus using the PWM circuit of the embodiment will be described.

FIG. 5 is a block diagram of an A / D / D / A controller which is the entire control system.

The A / D / D / A controller has two modes, an operation as an A / D converter and an operation as a PWM control circuit.

First, the operation as an A / D converter will be described. The comparator 1 compares the analog value selected by the MPX circuit 3, which is an analog multiplexer circuit, with the reference voltage of the D / A converter 5. Based on the result, the next reference voltage to be compared with the input is calculated by the arithmetic unit 8. We will compare with the determined analog value. In the comparison, the arithmetic unit 8 determines from the most significant bit to the least significant bit by the D / A conversion decision 5 until the reference voltage becomes closest to the input analog value.

In this way, the analog value selected by the MPX circuit 3 is set to A
/ D conversion.

 Next, the operation of the PWM control circuit will be described.

The external input is compared via the MPX circuit 3 with the D / A converter 5 serving as a reference value by the comparator 1, and the comparison result is held in the latch 4. The output of latch 4 is MAIN / PWM circuit 9 and S
The UB-PWM circuits 13 to 15 are supplied.

The transfer of data to and from the CPU of the A / D / D / A controller is performed using the registers (register A, register B, and register C) shown in FIG.
Done through. The register A is a register for setting data on the D / A conversion table. Register B is A /
This register is used to read the result of D conversion onto the CPU / BUS. Register C sets the status of A / D / D / A conversion operation
A register for setting each address of the M6, the MPX circuit 3, the latch 4, and the like.

As described above, the A / D / D / A controller is a block having two types of modes, an operation as a PWM control circuit and an operation as an A / D converter, and controlling the timing of each operation. -Data exchange between BUS is performed through each register.

FIG. 6 is an example of the comparator 1 of FIG. 5, and FIG. 7 is a timing chart of the comparator.

 The operation of the comparator 1 will be described.

The MPX circuit 3 is switched so that the timing generator 2 inputs external detection data serving as a comparison value.
Next, by turning on the switches SW1 and SW3 and turning off the switch SW2, the detection value selected by the MPX circuit 3 is input to the comparator. At the same time, D / A conversion data is stored in RAM
6. Select from the D / A conversion table above and set in the D / A converter 5. Next, by turning on the switch SW2 and turning off the switches SW1 and SW3, the value selected by the MPX circuit 3 is compared with the reference D / A conversion value, and the result is held in the latch.

FIG. 8 is a block diagram showing an example of the MAIN / PWM circuit of FIG. In the preceding A / D / D / A controller, the input of the multiplexer is compared by an analog comparator, and the results are held in latches, respectively.In the MAIN / PWM circuit, the results held in this latch are read by FLIP / FLOP81
To enter. The input comparison result of the analog comparator is clock-synchronized by the FLIP / FLOP81, and the UP /
Input to the UP / DOUN determination terminal of DOUN COUNTER82. At this time, the initial value of the counter is input to the UP / DOUN COUNTER 82 from the CPU / BUS 89 via the 4-bit register. Initial value is FL
The result is counted up and down by the value of UP / DOUN of IP • FLOP 1, and the result is sent to the next stage UP • COUNTER83. The value of the sent count is UP · COUNTER83 L
Reading is performed in synchronization with the OAD signal, and counting is started. The UP / COUNTER83 output signal is DIGITAL / COMPAR
In the ETER84, it is compared with the value set in the 4-bit register from the CPU / BUS89, and the result of the comparison is output as a pulse width modulation (PWM) output result. In the figure, the output of UP / COUNTER83 is connected to 7-bit AND85.This is to detect the end of the count.・ COUNTER
83 reads the data of UP / DOUN COUNTER 82 based on this signal. Here, UP ・ DOUN COUNTER82, UP ・ COUNTER83 and D
The IGITAL / COMPARETER84 has a 7-bit configuration and has the required precision.

An embodiment will be described with reference to the configuration and operation of the entire control system of the image forming apparatus described above.

FIG. 1 is a circuit diagram showing a pulse width modulation circuit according to an embodiment of the present invention and a stabilized power supply using the circuit.

A-1 is an output of the MAIN-PWM circuit 9, which drives the main transistor A-13 and outputs one of the transformers A-10.
The secondary side is driven, and an output A-11 is obtained from one of the secondary windings. The output A-11 is divided and fed back as an A-3 signal to become one input of the MPX circuit 3. A-12 output is taken out from another secondary winding of the transformer A-10, and the other terminal of the capacitor A-8, one of which is grounded, is connected to the low voltage side of the A-12 output, And a resistor A- connected to one end to the collector of the transistor A-5.
7 is connected to the other terminal. The emitter of the transistor A-5 has one terminal connected to the other terminal of the resistor A-6 whose ground is connected. The output A-2 of the SUB-PWM circuit drives the base of the sub-transistor A-5 via a resistor. The output A-12 is divided by a resistor and the feedback signal A
-4 is one input of the MPX circuit 3. Note that A
For the feedback signals of -3 and A-4, the voltage dividing ratio is appropriately selected so as to be within the operating range of the MPX circuit 3, the comparator 1, etc., and the voltage dividing resistor is pulled up to Vcc according to the polarities of A-11 and A-12. Or pull-down to GND is selected.

A-9 is a varistor and a current limiting resistor for protecting the transistor A-5 when the low voltage side of A-12 rises excessively. The RAM 6 is a storage device in which the set values of the outputs A-11 and A-12 are stored.

 Hereinafter, the operation of this embodiment will be described in detail.

First, the timing generator 2 drives the MPX circuit 3 to select the A-3 input and inputs it to the comparator 1. At the same time, an address storing the set value of the A-11 output is given to the RAM 6 and read out, and inputted to the D / A converter 5. The D / A converter 5 generates an analog voltage according to the input and uses it as the other input of the comparator 1. The comparator 1 compares the output of the MPX circuit 3 with the output of the D / A converter 5 by the operation described above, and determines whether the output is high or low according to the magnitude of the output.
Is output. At this time, the timing generator 2
The bit corresponding to the IN / PWM circuit 9 is supplied to the latch 4 and, at the same time, the latch signal is output.
Latch the ow output. The output of the latch 4 is connected as an input signal to the MAIN / PWM circuit 9 to the up / down selection input of the up / down counter in the MAIN / PWM circuit 9 as described above. Output A− of PWM circuit 9
1 drives the main transistor A-13 and controls the output of A-11 to a constant voltage.

Next, the timing generator 2 drives the MPX circuit 3 so as to select the A-4 input and inputs it to the comparator 1. At the same time, an address storing the set value of the A-12 output is given to the RAM 6 and read out, inputted to the D / A converter 5, and
The / A converter 5 converts the input value into an analog voltage and inputs the analog voltage to the other terminal of the comparator 1.

As described above, the comparator 1 compares the two and generates a high / low signal according to the magnitude of the comparison, and uses it as the input of the latch 4. The latch 4 selects the bit corresponding to the A-2 output by the signal of the timing generator 2. Latched.
The A-2 output drives the transistor A-5 via a resistor and performs the operation described below.

The above operation is repeated as one cycle. Although the present embodiment is applied to a two-output transformer, the present invention can be similarly realized when there are many PWM targets.

As described above, when one cycle is T, the SUB-PWM circuit compares a set value with an output value and selects a high / low pulse for each T, and controls the ON / OFF period of the transistor A-5. Control A-12 output to set value.

In summary, 1 is the input signal from MPX circuit 3 and D / A
The latch 4 is a storage unit that stores the output of the comparator 1, and the timing generator 2 is a unit that updates the storage contents of the storage unit at regular time intervals. ,
The stored content is an output signal, which constitutes a pulse width modulation circuit according to an embodiment of the present invention.

Further, a rectified power supply of A-12 output and a transistor A-5 and the like connected thereto are power supplies controlled by the pulse width modulation circuit, and the output A-12 is divided by a resistor divider to be supplied to MPX3. Together with the feedback means, a stabilized power supply according to an embodiment of the present invention is constituted.

Next, the operation of the stabilized power supply will be analyzed. The A-12 output is stabilized as follows. The low voltage side and high voltage side A-12a of the A-12 output winding output the primary side of the transformer A-10 to the output A-1.
Because it is controlled by the feedback signal from 1, A-1
A voltage that follows the output of 1 is generated. Now the A-11 output is that in a steady state, A-12a, between A-12b is constant voltage V ₀ in. At this time, the main part of the A-12 output was extracted and rewritten in the equivalent circuit in the second place.
FIG. The current flowing into the A-12a in FIG. 2 and i _1,
The current flowing through the transistor A-5 and i _2, the OFF state of the transistor A-5, i.e. 0V base potential at low output of A-2, when ON of the transistor A-5, i.e. A-2
Let the base potential at the time of high output be V _d V. Further, the OFF time of the transistor A-5 is t ₁ , the ON time is t _2, and A-12b
_Is V _CX .

At this time, the transistor A-5 is OFF, the capacitor C _X is charged with i _1, transistor A-5 is the time ON, the capacitor C _x is charged with i ₁ -i _2. That is, C _x
If the current flowing through is i _Cx , i _CX = i ₁ (when A-5 is OFF) i _CX = i ₁ -i ₂ (when A-5 is ON) i ₂ = (V _d −V _BE / R _x1 (V _BE : A (Base-emitter voltage of -5) V _Cx is Is represented by Δi _CX = i ₁ · t ₁ + (i _1- i ₂ ) · t ₂ = i ₁ · (t ₁ + t ₂ )-i ₂ · t ₂ Here, if Δi _Cx = 0, then V _Cx Is stabilized, and A-12 becomes V ₀ + V _{Cx and} becomes stable. FIG. 3 shows this operation. As shown in the figure, the A-12 output is divided and fed back to control the A-2 signal, so that a constant voltage operation is performed.

Now, t ₁ and t ₂ are integer multiples of the period T.

t ₁ = n ₁ · T, T ₂ = n ₂ · T (n ₁ and n ₂ are integers) In the above formula, ≠ is 0 for n ₁ and n ₂ . Because if n ₂ = 0, Δi _Cx = i ₁ , t ₁ > 0, and it is not stable. If n ₁ = 0, Δi _Cx = (i ₁ −i ₂ ) · n ₂ · T, and if i ₁ = i _2, Δi _CX = 0. However, since it is a feedback system, there is a steady-state error. ₁ ≠ i ₂ and Δi _Cx ≠ 0, which is not stable.

The ripple voltage peak-to-peak value is Its lowest value is It is. For this reason, the ripple becomes smaller as T, i ₁ , i ₂ is smaller, but i ₁ has a certain value in consideration of the output current, and i ₂ is also required to maintain the response characteristic of sudden load change. It cannot be made extremely small. T is constant. Further, the ripple as the C _x is large the smaller is unable extremely large in correspondence with the response, each parameter tolerances of the ripple from the output value is determined.

In the embodiment of FIG. 1, the transistor A-5 is operated at a constant current at the time of ON. However, the transistor A-5 may be modified to perform a switching operation as shown in FIG.

In this case, the aforementioned i ₂ is expressed as i ₂ = V _Cx / R _x2 , The analysis becomes difficult, but if V _Cx is kept constant in a stable state, the analysis can be performed in the same manner as V _Cx / R _x2 = i ₂ . With this method, the resistor R _x1 can be eliminated.

〔The invention's effect〕

As described above, according to the present invention, the circuit scale of the PWM circuit is reduced, the area occupied by the chip can be reduced during integration, and the integration into one chip is facilitated. As for the power supply, the circuit scale of the control circuit is reduced, the chip occupation area can be reduced, and significant cost reduction can be expected.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of the embodiment, FIG. 2 is an operation explanatory diagram of the embodiment, FIG. 3 is a conceptual diagram of the embodiment, and FIG. 4 is a modified view of the embodiment. FIG. 5 is a block diagram of an A / D / D / A controller using the PWM circuit of the embodiment, FIG. 6 is a configuration diagram of a comparator, FIG. 7 is a timing chart of the comparator, and FIG.
The figure is a block diagram of the MAIN / PWM circuit. 1 Comparator 2 Timing generator 4 Latch A-5 Transistor A-8 Capacitor

Claims (3)

(57) [Claims] An input section for inputting an analog signal, an analog comparator for directly inputting an analog signal from the input section, and comparing the input signal with a reference value, storing a comparison result of the analog comparator, and transmitting the stored data as a pulse. Storage means for outputting as a control signal for width modulation; pulse width modulation means for outputting a signal subjected to pulse width modulation in accordance with the control signal from the storage means; and each of the input section, the analog comparator, and the storage means And a timing signal generating means for repeatedly outputting a timing signal at predetermined time intervals, wherein the input unit outputs an analog signal input according to a timing signal from the timing signal generating means to the analog comparator, The analog comparator responds to the timing signal from the timing signal generating means. Perform comparison operation Te, the pulse width modulation circuit said storage means and performing a storage operation in response to a timing signal from the timing signal generating means. 2. A power supply circuit, an input section for inputting an analog signal proportional to an output of the power supply circuit, and a reference value corresponding to a target output of the power supply circuit for directly inputting an analog signal from the input section. An analog comparator to be compared, storage means for storing the comparison result of the analog comparator, and outputting the stored data as a control signal for pulse width modulation; and a pulse width modulated signal according to the control signal from the storage means. Pulse width modulation means for outputting as a control signal of the power supply circuit; and timing signal generation means for repeatedly outputting a timing signal to the input unit, the analog comparator, and the storage means at regular time intervals. The input unit converts the analog signal input according to the timing signal from the timing signal generating means into the analog signal. Output to the comparator, the analog comparator performs a comparison operation in response to a timing signal from the timing signal generation unit, and the storage unit performs a storage operation in response to a timing signal from the timing signal generation unit. Stabilized power supply. 3. The power supply circuit has a series circuit of a resistor and a transistor connected in series to a secondary winding circuit of a transformer, and a capacitor connected in parallel to the series circuit. The input of the output of the winding circuit,
3. The stabilized power supply according to claim 2, wherein said pulse width modulation means controls said transistor.