JPH0131814B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization acquisition circuit used in a frequency hopping spread spectrum communication receiver.

Figures 1a and 1b are block diagrams of a transmitter and a receiver, respectively, in a frequency hopping spectrum communication system. The transmitter shown in FIG. It has a container 4. This is exactly the same as the conventional modulation method except that the frequency of the carrier wave is hopping according to the PN code. The receiver shown in FIG. 1B includes a frequency synthesizer 9 for generating a local signal 102, a PN code generator 10, a balanced modulator 7 for demodulating a hopping carrier wave to generate an intermediate frequency signal 103, and a demodulating baseband signal 104. a synchronization circuit 11 that matches the hopping pattern of the received signal 101 with the hopping pattern of the local signal 102;
has. The information signal contained in the baseband signal 104 is extracted from the output terminal 12. FIG. 2a is a diagram showing the frequency pattern of the received signal 101, in which the frequency is hopping in accordance with the code pattern of the PN code generator 2. FIG. 1B is a diagram showing the frequency pattern of the local signal 102, in which the frequency is hopping in correspondence with the PN code represented by the output 106 of the PN code generator 10, as on the transmitting side. Here, f ₁ −f ₁ ′, f ₂ −f ₂ ′, . . . f ₅ −f ₅ ′ are all constant, and their values are selected equal to the frequency of the intermediate frequency signal 103. When the hopping patterns of the received signal 101 and the local signal 102 match (hereinafter referred to as a synchronous state), the baseband signal 104, which is the output of the demodulator 8, is maximum and constant as shown in FIG. 2c. becomes. Local signal 102
The circuit for bringing this into this synchronous state is the synchronous circuit 11.
and a synchronization acquisition circuit having an initial synchronization function,
It consists of a synchronization holding circuit that has the function of maintaining a synchronized state.

Among these, a block diagram of the conventional synchronization acquisition circuit is shown in FIG. 3, and FIG. 4 shows the time relationship between signals and frequency patterns of each part of this circuit. However, the synchronization acquisition circuit of FIG. 3 includes the receiver circuit of FIG. 1b as is. This method is called a step search, and the balanced modulator 7, demodulator 8, frequency synthesizer 9, and PN code generator 10 are the same circuits as shown in FIG. 1b. In addition to these circuits, an integrator 13 with an integration time Δτ, a timing signal generator 14, a clock generator 15, and a clock signal 11 in synchronization with the timing signal 108 when synchronization cannot be acquired.
A phase shift circuit 16 is provided that shifts the phase of 0 every Δτ. The operation of this step search type synchronization acquisition circuit will be explained below. A clock signal 110 generated by the clock generator 15 is sent to a phase shift circuit 16 which is controlled by a phase shift signal 109 generated by the timing signal generator 14.
By passing through the phase, the phase shifts at a constant time interval Δτ. Phase shift circuit 1 for delayed shift
The output 111 of 6 is shown in FIG. 4a. A clock signal 111 whose phase shifts at this fixed time interval Δτ
As a result, the phase of the hopping pattern of the local signal 102 is also shifted in synchronization with the clock signal 111, as shown in FIG. Now, when the hopping pattern of the received signal 101 is shown as c in the figure, the output 103 of the balanced modulator 7 becomes as shown in the figure d. The integrator 13 is reset by the timing signal 108 and integrates the baseband signal 104 over a time period Δτ in synchronization with the phase shift of the clock signal 110. Therefore, the output 107 of the integrator 13
is as shown in figure e, and the maximum output is obtained at the end of the section where the hopping patterns of the local signal 102 and the received signal 101 match. In this way, in the step search method, the clock signal 11
By a periodic phase shift of 0, the integrator 13
A synchronized state is obtained by finding the state where the output is maximum.

However, with the conventional circuit shown in Figure 3, the above operation can be performed without error when there is no interference or disturbance wave, but when a large interference wave is received, the synchronization state is lost. Even if the integrator output 107 is large, it is possible that a large integrator output 107 appears. For example, the fourth
As shown in _FIG .
It becomes as shown in figure g. At this time, the output 107 of the integrator 13 becomes as shown in h in the same figure, and even if it is not in the synchronous state, there is a section where the level is as high as in the synchronous state. can't do it correctly.

SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronization acquisition circuit in which the synchronization acquisition of a received signal in frequency hopping spread spectrum communication is less susceptible to interference waves or jamming waves.

The synchronization acquisition circuit according to the present invention receives a spread spectrum signal and a local signal in which the frequency of the carrier wave is hopping in correspondence with a pseudo-noise code, and the synchronization acquisition circuit receives the spread spectrum signal and the local signal in which the frequency of the carrier wave is hopping in accordance with the pseudo noise code, and the synchronization acquisition circuit receives the spread spectrum signal and the local signal in which the frequency of the carrier wave is hopping in accordance with the pseudo noise code. a demodulation circuit that generates a baseband signal with a magnitude proportional to the amplitude of the signal; a delay circuit that delays the baseband signal by a predetermined time; a first integrator that outputs an integral value; a limiter that limits the output of the delay circuit by using the integral value as a limit level; and a limiter that integrates the output of the limiter over the time and outputs the integral value when the time elapses. a second integrator, a clock generator that generates a clock signal having the same period as the clock period of the spread spectrum signal, and a circuit that controls the phase of the clock signal according to the integrated value of the second integrator. a pseudo-noise code generator that generates a signal representing the pseudo-noise code in synchronization with the output of the phase control circuit; and a frequency synthesizer that generates the local signal with frequency hopping according to the pseudo-noise code. configured.

The present invention will be described in detail below with reference to the drawings.
FIG. 5 is a block diagram of one embodiment of the present invention, and FIG. 6 is a waveform diagram of various signals of this embodiment. This embodiment includes, in addition to the conventional circuit shown in FIG. Limita that changes with time 19
It is equipped with Although the circuit has this configuration,
Next, its operation will be explained. FIG. 6a shows the demodulator 8
It is the output 104 of , and represents the waveform when it is in a synchronized state at time Δt ₁ and receives interference at time Δt ₂ . Figure b is the output 113 of the integrator 18,
The limit level of the limiter 19 is set by the value of the output 113 at the end of each Δτ.
In the same figure, c is the input signal 112 of the limiter 19,
This is a signal obtained by delaying the demodulator output 104 of a in the same figure by Δτ. The output 114 of the limiter 19 in response to this input signal 112 becomes as shown in the figure d due to the limit level set by the integrator 18 output 113, and the level for the Δt ₁ section does not change, but the level for Δt ₂ is suppressed. be done. Such an effect of the limiter 19 makes it possible to reduce the influence of interference waves on the synchronization acquisition circuit. This is because the output time width of the limiter 19 for the interference wave is smaller than the output time width τ for the received signal 101, so at the output 107 of the integrator 13, the level of the interference wave component is considerably smaller than the signal wave component, and therefore The timing signal generator 14 distinguishes both components and only when synchronization can be truly acquired.
This is because the phase shift of the phase shift circuit 16 can be stopped.

As described in detail above, according to the present invention, it is possible to provide a synchronization acquisition circuit in which synchronization acquisition of a received signal in frequency hopping spread spectrum communication is less susceptible to interference waves or jamming waves. Therefore, by using this synchronization acquisition circuit, a spread spectrum multiple access communication system that involves interference can be effectively constructed.

[Brief explanation of drawings]

1A and 1B are block diagrams of a transmitter and a receiver of the frequency hopping spread spectrum communication system, respectively; FIG. 2 is a diagram showing the frequencies and signal levels of signals in each part to explain the operation of this receiver; FIG. 3 is a block diagram of a conventional synchronization acquisition circuit using the step search method, and FIG. 4 is a diagram showing the time relationship between signals and frequency patterns of each part of this circuit.
FIG. 5 is a block diagram of one embodiment of the present invention, and FIG. 6 is a signal waveform diagram of each part of this embodiment.

Claims (1)

[Claims] 1. A spread spectrum signal whose carrier frequency is hopping corresponding to a pseudo noise code and a local signal are received, and only during a period when the frequency difference between these two signals is a predetermined value, a large amplitude proportional to the amplitude of the spread spectrum signal is received. a demodulation circuit that generates a baseband signal of 300 msec, a delay circuit that delays this baseband signal by a predetermined time, and a first circuit that integrates the baseband signal with respect to the time period and outputs an integral value when the time elapses. a limiter that limits the output of the delay circuit by using the integrated value as a limit level, and a second integrator that integrates the output of the limiter over the time and outputs the integrated value when the time elapses; a clock generator that generates a clock signal with the same period as the clock period of the spread spectrum signal; a circuit that controls the phase of the clock signal according to the integral value of the second integrator; A synchronization acquisition circuit comprising: a pseudo-noise code generator that generates a signal representing the signal in synchronization with the output of the phase control circuit; and a frequency synthesizer that generates the local signal with frequency hopping according to the pseudo-noise code.