JPH01313942A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH01313942A
JPH01313942A JP14484188A JP14484188A JPH01313942A JP H01313942 A JPH01313942 A JP H01313942A JP 14484188 A JP14484188 A JP 14484188A JP 14484188 A JP14484188 A JP 14484188A JP H01313942 A JPH01313942 A JP H01313942A
Authority
JP
Japan
Prior art keywords
insulating film
layer
interlayer insulating
group
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14484188A
Other languages
Japanese (ja)
Inventor
Akira Oikawa
及川 朗
Shunichi Fukuyama
俊一 福山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14484188A priority Critical patent/JPH01313942A/en
Publication of JPH01313942A publication Critical patent/JPH01313942A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To form a multilayer interconnection in high reliability by a method wherein a double layer structured interlayer insulating film comprising a resin layer capable of flattening an underneath stepped part is used as a lower layer and another resin layer in excellent oxidation resistance as an upper layer. CONSTITUTION:An applicable interlayer insulating film is double layer structured, i.e. the lower layer insulating film comprises an organic silicon polymer capable of flattening an underneath stepped part while the upper layer insulating film comprises an aryl group containing organic silicon polymer with oxidation resistance. Such a double layer structured interlayer insulating film can flatten the surface of semiconductor substrate having rugged surface and can maintain the film quality thereof subject to no crack or release even if it is exposed to the oxygen atmosphere exceeding 400 deg.C or oxygen radical in high concentration or oxygen ionic atmosphere. Through these procedures, a multilayer interconnection of high reliability can be formed.

Description

【発明の詳細な説明】 〔概 要〕 多層配線構造をもった半導体装置に関し、凹凸を有する
下地を平坦にでき、しかも、後続の工程における熱処理
等に原因してクラックを生じて破損することのない層間
絶縁膜を提供することを目的とし、 含まれる層間絶縁膜が二層構造を有していて、下層の絶
縁膜が下地段差を平坦化可能な有機ケイ素重合体からな
り、かつ上層の絶縁膜が耐酸化性を保有しているアリー
ル基含有有機ケイ素重合体からなるように構成する。
[Detailed Description of the Invention] [Summary] Regarding a semiconductor device having a multilayer wiring structure, it is possible to flatten an uneven base, and to prevent cracks and damage caused by heat treatment in subsequent steps. The purpose of this invention is to provide an interlayer insulating film that has a two-layer structure, in which the lower insulating film is made of an organosilicon polymer that can flatten the underlying step, and the upper insulating film is The film is made of an aryl group-containing organosilicon polymer that has oxidation resistance.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体装置に関し、さらに詳しく述べると、多
層配線構造をもった半導体装置に関する。
The present invention relates to a semiconductor device, and more specifically, to a semiconductor device having a multilayer wiring structure.

換言すると、本発明は、半導体集積回路の多層配線形成
方法に係わり、詳しくは、IC,LSI等の集積密度の
高い半導体の多層配線を形成する際に、下地段差を平坦
化しつつ優れた絶縁性を有する層間絶縁膜を提供するこ
とによる信頼性の高い多層配線形成方法に関する。
In other words, the present invention relates to a method for forming multilayer interconnections for semiconductor integrated circuits, and more specifically, when forming multilayer interconnections for semiconductors with high integration density such as ICs and LSIs, the present invention provides excellent insulation while flattening the underlying steps. The present invention relates to a highly reliable multilayer wiring formation method by providing an interlayer insulating film having the following characteristics.

〔従来の技術〕[Conventional technology]

半導体集積回路では、集積度が向上するとともに、配線
の容易さ、動作速度の向上を目的として配線を立体化す
ることが要求され、したがって多層配線が開発された。
BACKGROUND ART In semiconductor integrated circuits, as the degree of integration has improved, there has been a demand for three-dimensional wiring for the purpose of facilitating wiring and improving operating speed, and multilayer wiring has therefore been developed.

多層配線を形成する場合には、第−層配線を施した後、
絶縁膜を介して第二層配線を施し、順次この工程を繰り
返すことが一般的であった。
When forming multilayer wiring, after applying the first layer wiring,
It has been common practice to provide a second layer of wiring via an insulating film and repeat this process in sequence.

ここで、層間絶縁膜として用いる材料としては、従来、
二酸化珪素、窒化珪素、りんガラス(PSG)などの無
機膜をシラン系ガスを用いたCVDの気相成長法により
形成したSin、系材料、あるいはポリイミド、シリコ
ーン樹脂などの高分子絶縁材料、または、これらの積層
体を用いて行われているが、配線パターンの微細化に伴
い信頼性という点でより特性の優れた材料が要求されて
きた。
Here, the materials used for the interlayer insulating film are conventionally
Inorganic films such as silicon dioxide, silicon nitride, and phosphorous glass (PSG) are formed by CVD vapor phase growth using silane-based gases, or polymer insulating materials such as polyimide and silicone resin, or Although these laminates have been used, materials with better characteristics in terms of reliability have been required as wiring patterns become finer.

多層配線を考える場合、第−層配線を施した半導体基板
上は配線による凹凸を有するので、これを下地としてそ
の上に無機膜を形成すると層間絶縁膜の表面は下地の凹
凸をそのまま再現してしまう。このため、その上に形成
される上層配線の断線、絶縁不良等の原因となる。した
がって、凹凸を有する下地上に塗布したとき基板表面を
平坦になしうる層間絶縁材料の開発が行われ、エッチバ
ック法、バイアススパッタ法などの絶縁膜製造プロセス
上から平坦面を得る方法と、樹脂をスピンコード法によ
り成膜して平坦な絶縁膜を得る方法が検討されている。
When considering multilayer wiring, the semiconductor substrate with the first layer wiring has unevenness due to the wiring, so if you use this as a base and form an inorganic film on top of it, the surface of the interlayer insulating film will reproduce the unevenness of the base as it is. Put it away. This causes disconnection, poor insulation, etc. of the upper layer wiring formed thereon. Therefore, the development of interlayer insulating materials that can flatten the substrate surface when applied to an uneven substrate, and methods for obtaining a flat surface from an insulating film manufacturing process such as etch-back method and bias sputtering method, and resin A method of forming a flat insulating film using a spin code method is being considered.

これらの方法のなかで樹脂塗布法は、樹脂を塗布した後
に加熱硬化させ成膜するプロセス的に簡便な方法である
。ここで用いられる樹脂材料としては、従来からポリイ
ミド、スピンオングラス等がある。しかし、ポリイミド
のような炭素系の材料は後続のレジスト剥離工程におい
て、既存のレジストとのエツチング選択比が小さいなど
の欠点があり、また、スピンオングラスは、厚塗りした
際、硬化時の縮合による歪みでクラックを生じやすい。
Among these methods, the resin coating method is a simple process in which a resin is applied and then heated and cured to form a film. Conventional resin materials used here include polyimide, spin-on glass, and the like. However, carbon-based materials such as polyimide have drawbacks such as a low etching selectivity with existing resist in the subsequent resist stripping process, and spin-on glass has the disadvantage that when coated thickly, condensation occurs during curing. Cracks are likely to occur due to distortion.

そこで、これまで、多くのシリコーン樹脂が層間絶縁膜
用に開発された。
Therefore, many silicone resins have been developed for interlayer insulation films.

なかんずく、ポリメチルシルセスキオキサンに代表され
るラダー型シリコーン樹脂は、下地段差の平坦化性に優
れ、不活性ガス雰囲気下では3pm程度の膜厚までクラ
ックを生じない材料である。
Above all, a ladder-type silicone resin represented by polymethylsilsesquioxane is a material that has excellent ability to flatten base steps and does not cause cracks up to a film thickness of about 3 pm in an inert gas atmosphere.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

半導体装置の多層配線工程においては、多くの場合、上
述のようなシリコーン樹脂を塗布形成した後、400℃
以上の酸素雰囲気や、高濃度の酸素ラジカルあるいは酸
素イオン雰囲気に曝露することが必須である。従って、
層間絶縁膜には、優れた酸化耐性が要求される。しかし
、前記したポリメチルシルセスキオキサンは、400℃
以上の酸素雰囲気下では、酸化劣化に起因したクラック
が生じ易くなる。
In the multilayer wiring process of semiconductor devices, in many cases, after coating the silicone resin as described above, the heating temperature is 400°C.
It is essential to be exposed to the above oxygen atmosphere, or to a high concentration oxygen radical or oxygen ion atmosphere. Therefore,
Interlayer insulating films are required to have excellent oxidation resistance. However, the polymethylsilsesquioxane described above is heated at 400°C.
In the above oxygen atmosphere, cracks are likely to occur due to oxidative deterioration.

一方、ポリフェニルシルセスキオキサンやポリジメチル
シルフェニレンジシロキサンのように、分子中にアリー
ル基を有する有機ケイ素樹脂もまた公知である。これら
の樹脂は、酸化温度が向上し、400℃程度の酸素雰囲
気下では酸化しにくくなる。しかし、かかる樹脂の場合
、膜強度は減少する傾向にあり、単独で眉間絶縁膜とし
て用いた場合、アルミニウム(Aj’)などの配線材料
の熱膨張による応力の影響でクラックが生じやすくなる
ため、厚膜化が困難である。
On the other hand, organosilicon resins having an aryl group in the molecule, such as polyphenylsilsesquioxane and polydimethylsilphenylene disiloxane, are also known. These resins have an improved oxidation temperature and are less likely to be oxidized in an oxygen atmosphere of about 400°C. However, in the case of such resins, the film strength tends to decrease, and when used alone as an insulating film between the eyebrows, cracks are likely to occur due to stress caused by thermal expansion of wiring materials such as aluminum (Aj'). It is difficult to thicken the film.

本発明の目的はこれらの欠点を解消することにあり、凹
凸を有する下地を平坦にでき、しかも、後続の工程にお
ける熱処理等に原因してクラックを生じて破損すること
のない層間絶縁膜を提供することを目的とする。
The purpose of the present invention is to eliminate these drawbacks, and provide an interlayer insulating film that can flatten an uneven base and does not cause cracks and damage due to heat treatment in subsequent steps. The purpose is to

〔課題を解決するための手段〕[Means to solve the problem]

上記した目的は、本発明によれば、含まれる眉間絶縁膜
が二層構造を有していて、下層の絶縁膜が下地段差を平
坦化可能な有機ケイ素重合体からなり、かつ上層の絶縁
膜が耐酸化性を保有しているアリール基含有有機ケイ素
重合体からなる、多層配線構造をもった半導体装置によ
って達成することができる。
According to the present invention, the glabellar insulating film included has a two-layer structure, the lower insulating film is made of an organosilicon polymer capable of flattening the underlying step, and the upper insulating film This can be achieved by a semiconductor device with a multilayer wiring structure made of an aryl group-containing organosilicon polymer that has oxidation resistance.

本発明の半導体装置において、含まれる二層構造層間絶
縁膜の下層は、上記した通り、下地段差を平坦化可能な
有機ケイ素重合体からなる。そもそも、二層のうちの下
層に用いられる樹脂は、配線等によって生じる凹凸を平
坦化しつつ、加熱の際に下地材料の熱膨張により生じる
応力に耐え、亀裂を生じたり、剥離を起こさない膜を形
成できればいかなるものでもよいが、後続の工程との適
合性を鑑みて、有機ケイ素重合体が好ましい。
In the semiconductor device of the present invention, the lower layer of the two-layer interlayer insulating film is made of an organosilicon polymer capable of flattening the underlying step, as described above. In the first place, the resin used for the lower of the two layers is designed to flatten unevenness caused by wiring, etc., and to withstand stress caused by thermal expansion of the base material during heating, creating a film that does not crack or peel. Any material may be used as long as it can be formed, but organosilicon polymers are preferred in view of compatibility with subsequent steps.

下層絶縁膜として有用な有機ケイ素重合体は、より具体
的に述べるならば、次の一般式(1)により表わされる
ポリオルガノシルセスキオキサンを構造単位として有し
てなる高分子化合物である:CL  5tO3z2〕n
      ・・・(I)(上式において、RIは、水
素、ヒドロキシル基、例えばメチル基、エチル基、n−
プロピル基、i−プロビル基等のアルキル基又は例えば
メトキシ基、エトキシ基、n−プロポキシ基、i−プロ
ポキシ基等のアルコキシ基を表わし、そしてnは10〜
50.000の整数を表わす)。この一般式(I)によ
り表わされるポリオルガノシルセスキオキサンを構造式
で示すと、次の通りである: (式中のR1は同一もしくは異なっていてもよく、前記
定義に同じであり、そしてnは前記定義に同じである)
More specifically, the organosilicon polymer useful as the lower insulating film is a polymer compound having a polyorganosilsesquioxane as a structural unit represented by the following general formula (1): CL 5tO3z2]n
...(I) (In the above formula, RI is hydrogen, a hydroxyl group, such as a methyl group, an ethyl group, n-
represents an alkyl group such as propyl group, i-propyl group, or an alkoxy group such as methoxy group, ethoxy group, n-propoxy group, i-propoxy group, and n is 10 to
50.000). The structural formula of the polyorganosilsesquioxane represented by the general formula (I) is as follows: (R1 in the formula may be the same or different and is the same as the above definition, and n is the same as defined above)
.

下層絶縁膜として有用な有機ケイ素重合体のその他の例
は、次の一般式(n)により表わされるポリジオルガノ
シルアルキレンジシロキサンを構造単位として有してな
る高分子化合物である:(R+StO□/2(R2)l
/2 ) −・・・(Il)(上式において、R1は前
記定義に同じであって、水素、ヒドロキシル基、例えば
メチル基、エチル基、n−プロピル基、1−プロピル基
等の低級アルキル基又は例えばメトキシ基、エトキシ基
、n−プロポキシ基、i−プロポキシ基等の低級アルコ
キシ基を表わし、R2は例えばメチレン基、エチレン基
等のアルキレン基を表わし、そしてnは10〜50.0
00の整数を表わす)。ここで式中のRo及びR2は、
必要に応じて置換されていてもよい。
Another example of an organosilicon polymer useful as a lower insulating film is a polymer compound having polydiorganosylalkylene disiloxane as a structural unit represented by the following general formula (n): (R+StO□/ 2(R2)l
/2) -...(Il) (In the above formula, R1 is the same as defined above, and is hydrogen, a hydroxyl group, for example, a lower alkyl group such as a methyl group, an ethyl group, an n-propyl group, a 1-propyl group, etc.) or a lower alkoxy group such as a methoxy group, an ethoxy group, an n-propoxy group, an i-propoxy group, R2 represents an alkylene group such as a methylene group or an ethylene group, and n is 10 to 50.0.
(represents an integer of 00). Here, Ro and R2 in the formula are
It may be replaced as necessary.

上記一般式(n)の有機ケイ素重合体は、好ましくは、
次の構造式(b)又は(C)の重合体あるいはこれらの
重合体の混合物である。
The organosilicon polymer of the general formula (n) above preferably has:
It is a polymer of the following structural formula (b) or (C) or a mixture of these polymers.

(式中のR,、R,及びnはそれぞれ前記定義に同じで
ある)。
(R, , R, and n in the formula are each the same as defined above).

本発明の半導体装置において、上層の絶縁膜は、耐酸化
性を保有しているアリール基含有有機ケイ素重合体から
なる。ここで、有機ケイ素重合体の分子中にアリール基
が含まれることは、満足し得る耐酸化性を保証するうえ
で必須の条件である。
In the semiconductor device of the present invention, the upper insulating film is made of an aryl group-containing organosilicon polymer that has oxidation resistance. Here, the inclusion of an aryl group in the molecule of the organosilicon polymer is an essential condition for ensuring satisfactory oxidation resistance.

なお、二層のうちの上層に用いられる樹脂は、400℃
以上の酸素雰囲気や、高濃度の酸素ラジカルあるいは酸
素イオン雰囲気中においても酸化しにくく、亀裂や剥離
をおこさない膜を形成できればいかなるものでもよいが
、後続の工程との適合性を鑑みて、有機ケイ素重合体が
好ましい。
Note that the resin used for the upper layer of the two layers is heated to 400°C.
Any material may be used as long as it can form a film that is resistant to oxidation and does not cause cracks or peeling even in the above oxygen atmospheres or in high-concentration oxygen radical or oxygen ion atmospheres, but in consideration of compatibility with subsequent processes, organic Silicon polymers are preferred.

上層絶縁膜として有用な有機ケイ素重合体は、より具体
的に述べるならば、次の一般式(n)により表わされる
ポリオルガノシルセスキオキサンを構造単位として有し
てなる高分子化合物である。
More specifically, the organosilicon polymer useful as the upper insulating film is a polymer compound having a polyorganosilsesquioxane represented by the following general formula (n) as a structural unit.

〔R,−3in、、□〕。     ・・・(III)
(上式において、R8は、例えばフェニル基、トリル基
、ナフチル基等のアリール基を表わし、そしてnは10
〜50.000の整数を表わす)。この一般式(III
)により表わされるポリオルガノシルセスキオキサンを
構造式で示すと、次の通りである=(式中のR1は同一
もしくは異なっていてもよく、前記定義に同じであり、
モしてnは前記定義に同じである)。
[R, -3in, □]. ...(III)
(In the above formula, R8 represents an aryl group such as a phenyl group, tolyl group, or naphthyl group, and n is 10
~50.000). This general formula (III
) The structural formula of the polyorganosilsesquioxane represented by
(n is the same as defined above).

上層絶縁膜として有用な有機ケイ素重合体のその他の例
は、次の一般式(rV)により表わされるポリジオルガ
ノジルアリーレンジシロキサンを構造単位として有して
なる高分子化合物である:[R,5in2.□(R4)
I/□〕7   ・・・(IV)(上式において、R1
は、前記定義に同じであって、水素、ヒドロキシル基、
低級アルキル基又は低級アルコキシ基を表わし、R1は
例えば0−+m−又はp−のフェニレン基、トリレン基
、ナフチレン基等のアリーレン基を表わし、モしてnは
10〜50.000の整数を表わす)。ここで、式中の
R1及びR1は、必要に応じて置換されていてもよい。
Another example of an organosilicon polymer useful as an upper insulating film is a polymer compound having a polydiorganosylarylene disiloxane as a structural unit represented by the following general formula (rV): [R,5in2 .. □(R4)
I/□]7...(IV) (In the above formula, R1
is the same as the above definition, hydrogen, hydroxyl group,
It represents a lower alkyl group or a lower alkoxy group, R1 represents an arylene group such as a 0-+m- or p-phenylene group, tolylene group, or naphthylene group, and n represents an integer of 10 to 50.000. ). Here, R1 and R1 in the formula may be substituted as necessary.

上記一般式(rV)の有機ケイ素重合体は、好ましくは
、次の構造式(e)又は(f)の重合体あるいはこれら
の重合体の混合物である。
The organosilicon polymer represented by the above general formula (rV) is preferably a polymer represented by the following structural formula (e) or (f), or a mixture of these polymers.

(式中のR+  、R4及びnはそれぞれ前記定義に同
じである)。
(R+, R4 and n in the formula are each the same as defined above).

本発明の実施において、二層構造をもった層間絶縁膜の
上層及び下層は、いずれも任意の手法によって形成する
ことができる。しかし、プロセスが簡便であり下地の平
坦化に有利であるという理由から、スピン塗布法を用い
ることが特に推奨される。
In carrying out the present invention, both the upper and lower layers of the interlayer insulating film having a two-layer structure can be formed by any method. However, it is particularly recommended to use the spin coating method because it is a simple process and is advantageous for flattening the underlying layer.

上層絶縁膜及び下層絶縁膜の膜厚は、それぞれ、広い範
囲で変更することができる。しかし、上層絶縁膜は、酸
素が透過し得ない厚さであればできるかぎり薄いほうが
よく、一般に0.1〜0.57−であることが好ましい
。一方、下層絶縁膜の膜厚は、下地の平坦化を考慮して
、一般に1〜2Jaであることが好ましい。
The thicknesses of the upper insulating film and the lower insulating film can be varied within a wide range. However, the upper insulating film should be as thin as possible as long as it does not allow oxygen to pass through, and is generally preferably from 0.1 to 0.57. On the other hand, the thickness of the lower insulating film is generally preferably 1 to 2 Ja in consideration of planarization of the underlying layer.

また、絶縁膜の上層及び下層の組み合わせは、各々の密
着性が良好であればいかなる組み合わせで用いてもかま
わない。また、この二層構造よりなる層間絶縁膜は、こ
れを単独で層間絶縁膜として使用しても、あるいは、二
酸化珪素、窒化珪素、燐ガラス(P S G)等の無機
膜と併用して層間絶縁膜として使用してもいずれであっ
てもよい。
Moreover, any combination of the upper layer and lower layer of the insulating film may be used as long as the adhesion of each layer is good. In addition, the interlayer insulating film having this two-layer structure can be used alone as an interlayer insulating film, or in combination with an inorganic film such as silicon dioxide, silicon nitride, or phosphorous glass (PSG) to form an interlayer insulating film. Either may be used as an insulating film.

〔作 用〕[For production]

本発明に係わる二層構造よりなる層間絶縁膜は、凹凸表
面を有する半導体基板表面を平坦化でき、かつ、400
℃以上の酸素雰囲気、高濃度の酸素ラジカルや酸素イオ
ン雰囲気中に曝されても亀裂や剥離を起こさず、その膜
質を保持できる。そのため十分な絶縁性が期待でき、半
導体集積回路の層間絶縁膜としての使用に適している。
The interlayer insulating film having a two-layer structure according to the present invention can flatten the surface of a semiconductor substrate having an uneven surface, and
Even when exposed to an oxygen atmosphere at temperatures above ℃ or a high concentration of oxygen radicals or oxygen ions, it does not crack or peel, and can maintain its film quality. Therefore, it can be expected to have sufficient insulation properties and is suitable for use as an interlayer insulating film for semiconductor integrated circuits.

〔実施例〕〔Example〕

以下、本発明を実施例により説明する。 The present invention will be explained below with reference to Examples.

例 1 (調製例) 1.2−ビス(メチルジクロロシリル)エタン5gをテ
トラヒドロフラン50ccに溶解し、メチルイソブチル
ケトン100cc、メチルセロソルブアセテ−)50c
c、トリエチルアミン15cc及びイオン交換水30c
cの混合系に滴下し、75℃で3時間撹拌した。冷却後
静置して水層を除き、さらに、十分な水洗いを施した。
Example 1 (Preparation example) 1. Dissolve 5 g of 2-bis(methyldichlorosilyl)ethane in 50 cc of tetrahydrofuran, 100 cc of methyl isobutyl ketone, and 50 c of methyl cellosolve acetate.
c, triethylamine 15cc and ion exchange water 30c
It was added dropwise to the mixed system of c and stirred at 75°C for 3 hours. After cooling, the mixture was allowed to stand to remove the aqueous layer, and then thoroughly washed with water.

得られた反応溶液を乾固し、残った樹脂を1.4−ジオ
キサンに再び溶解し、凍結乾燥した。2.8gのポリジ
メチルシルエチレンジシロキサン粉末が回収できた。
The resulting reaction solution was dried and the remaining resin was dissolved again in 1,4-dioxane and freeze-dried. 2.8g of polydimethylsilethylenedisiloxane powder was recovered.

例2 前記例1により得た粉末を酢酸イソアミルに溶解し、半
導体素子を形成し第−層アルミ配線を施したシリコン基
板上(アルミの厚さは1−1最小線幅は1−1最小線間
隔は1.57−)に1.04191.にスピン塗布した
。塗布後、80℃で20分間溶剤乾燥、続いて窒素中、
420℃、1時間の熱処理を施した。熱処理後の基板表
面の段差は、約0,2Isaであり、アルミ配線により
生じた段差は平坦化されていた。続いて、末端トリメチ
ルシリル化を施したポリジメチル−p−シルフェニレン
ジシロキサン粉末を酢酸イソアミルに溶解し、上記の方
法により形成した膜上に0.7μ厚に塗布した。塗布後
、80℃で20分間溶剤乾燥、続いて大気中、420℃
、15m1nの熱処理を施した。処理後の塗布膜には亀
裂、剥離等は見られなかった。続いて、スルーホールを
形成し二層目のアルミ配線を行い、保護層として1.2
−のSiO□膜を形成した後、電極取り出し用窓開けを
行って半導体装置を得た。この装置は、大気中420℃
で1時間の加熱試験、−65℃→150℃の10回の熱
衝撃試験後も全く不良はみられなかった。
Example 2 The powder obtained in Example 1 was dissolved in isoamyl acetate, a semiconductor element was formed, and a first layer of aluminum wiring was applied on a silicon substrate (thickness of aluminum is 1-1, minimum line width is 1-1, minimum line width is 1-1). The interval is 1.57-) to 1.04191. spin coated on. After coating, the solvent was dried at 80°C for 20 minutes, followed by drying in nitrogen.
Heat treatment was performed at 420°C for 1 hour. The level difference on the substrate surface after the heat treatment was approximately 0.2Isa, and the level difference caused by the aluminum wiring had been flattened. Subsequently, polydimethyl-p-silphenylene disiloxane powder subjected to terminal trimethylsilylation was dissolved in isoamyl acetate and applied to a thickness of 0.7 μm on the film formed by the above method. After application, solvent drying at 80°C for 20 minutes, followed by drying at 420°C in air.
, 15 m1n of heat treatment was performed. No cracks, peeling, etc. were observed in the coated film after treatment. Next, through holes are formed and a second layer of aluminum wiring is formed, and a protective layer of 1.2
After forming a - SiO□ film, a window for taking out an electrode was opened to obtain a semiconductor device. This device operates at 420℃ in the atmosphere.
No defects were observed even after a 1-hour heating test at 100°C and 10 thermal shock tests from -65°C to 150°C.

例3 前記例2と同様の方法で二層構造膜を形成したのち、さ
らにPSG膜を0.3p常圧CVD法で形成した。この
膜は、下地段差を約0.2pmに平坦化していた。その
後は前記例2と同様に半導体装置を製造して試験したと
ころ、全く不良は見られなかった。
Example 3 After forming a two-layer structure film in the same manner as in Example 2, a PSG film was further formed using a 0.3p normal pressure CVD method. This film flattened the underlying level difference to about 0.2 pm. Thereafter, a semiconductor device was manufactured and tested in the same manner as in Example 2, and no defects were found.

比較例1 前記例2と同様に下層のポリジメチルシルエチレンジシ
ロキサン膜を1.0趨形成した後、大気中、420℃、
15m1nの熱処理を施した。処理後の膜には、全面に
移しい亀裂が生じ、その後、半導体装置を製造すること
はできなかった。
Comparative Example 1 After forming the lower layer polydimethylsilethylene disiloxane film in the same manner as in Example 2, it was heated at 420°C in the atmosphere.
A heat treatment of 15 ml was performed. Severe cracks appeared on the entire surface of the film after the treatment, and it was no longer possible to manufacture a semiconductor device thereafter.

比較例2 前記例2と同様に下層のポリジメチルシルエチレンジシ
ロキサン膜を1.Ojs形成した後、窒素中、420℃
、1時間の熱処理を施した。その後PSG膜を0.3烏
常圧CVD法で形成したところ、膜全面に亀裂が生じ、
その後の半導体装置製造を行うことはできなかった。
Comparative Example 2 In the same manner as in Example 2, the lower polydimethylsilethylene disiloxane film was coated with 1. After forming Ojs, 420℃ in nitrogen
, heat treatment was performed for 1 hour. After that, when a PSG film was formed using the 0.3mm atmospheric pressure CVD method, cracks appeared on the entire surface of the film.
It was not possible to manufacture semiconductor devices thereafter.

〔発明の効果〕〔Effect of the invention〕

本発明は、半導体集積回路の多層配線形成工程において
、層間絶縁膜として、下地段差を平坦化する樹脂層を下
層に、酸化耐性に優れた樹脂層を上層に用いた二層構造
よりなる層間絶縁膜を用いることを特徴とする。本発明
によれば、記載の層間絶縁膜を用いることにより、配線
工程において生じる高段差を完全に平坦化することが可
能であり、また、従来のシリコーン樹脂に見られていた
高温酸素雰囲気中での亀裂や剥離の発生を防止できる。
The present invention is an interlayer insulating film used in the process of forming multilayer wiring for semiconductor integrated circuits, which has a two-layer structure in which a resin layer for flattening the underlying step is used as a lower layer, and a resin layer with excellent oxidation resistance is used as an upper layer. It is characterized by using a membrane. According to the present invention, by using the interlayer insulating film described above, it is possible to completely flatten the high level difference that occurs in the wiring process, and it is also possible to completely flatten the high-level difference that occurs in the wiring process, and it is also possible to completely flatten the high-level difference that occurs in the wiring process. can prevent cracking and peeling.

したがって、配線の断線や絶縁不良を起こすことなく信
頼性の高い多層配線を形成可能になる。
Therefore, it is possible to form highly reliable multilayer wiring without causing wire breakage or insulation failure.

Claims (1)

【特許請求の範囲】[Claims] 1、含まれる層間絶縁膜が二層構造を有していて、下層
の絶縁膜が下地段差を平坦化可能な有機ケイ素重合体か
らなり、かつ上層の絶縁膜が耐酸化性を保有しているア
リール基含有有機ケイ素重合体からなる、多層配線構造
をもった半導体装置。
1. The interlayer insulating film included has a two-layer structure, the lower insulating film is made of an organosilicon polymer that can flatten the underlying step, and the upper insulating film has oxidation resistance. A semiconductor device with a multilayer wiring structure made of an aryl group-containing organosilicon polymer.
JP14484188A 1988-06-14 1988-06-14 Semiconductor device Pending JPH01313942A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14484188A JPH01313942A (en) 1988-06-14 1988-06-14 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14484188A JPH01313942A (en) 1988-06-14 1988-06-14 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH01313942A true JPH01313942A (en) 1989-12-19

Family

ID=15371676

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14484188A Pending JPH01313942A (en) 1988-06-14 1988-06-14 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH01313942A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04233732A (en) * 1990-08-16 1992-08-21 Motorola Inc Spin on derivative used in manufacturing process of semiconductor
JP2017092457A (en) * 2015-10-23 2017-05-25 三星エスディアイ株式会社Samsung SDI Co., Ltd. Film structure manufacturing method, and pattern formation method
WO2017145808A1 (en) * 2016-02-24 2017-08-31 日産化学工業株式会社 Planarization method for semiconductor substrates using silicon-containing composition

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04233732A (en) * 1990-08-16 1992-08-21 Motorola Inc Spin on derivative used in manufacturing process of semiconductor
JP2017092457A (en) * 2015-10-23 2017-05-25 三星エスディアイ株式会社Samsung SDI Co., Ltd. Film structure manufacturing method, and pattern formation method
WO2017145808A1 (en) * 2016-02-24 2017-08-31 日産化学工業株式会社 Planarization method for semiconductor substrates using silicon-containing composition
CN108885997A (en) * 2016-02-24 2018-11-23 日产化学株式会社 The flattening method of the semiconductor substrate containing silicon composition is used
JPWO2017145808A1 (en) * 2016-02-24 2018-12-13 日産化学株式会社 Method of planarizing a semiconductor substrate using a silicon-containing composition
US20190051518A1 (en) * 2016-02-24 2019-02-14 Nissan Chemical Corporation Planarization method for a semiconductor substrate using a silicon-containing composition
US10910220B2 (en) 2016-02-24 2021-02-02 Nissan Chemical Corporation Planarization method for a semiconductor substrate using a silicon-containing composition
CN108885997B (en) * 2016-02-24 2023-06-02 日产化学株式会社 Planarization method for semiconductor substrate using silicon-containing composition

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