JPH01307091A - Multiport memory - Google Patents

Abstract

PURPOSE:To apply a freedom degree to the aspect ratio of a layout, to reduce the number of rows, to facilitate the layout of a circuit, to shorten the length of a bit line, and to reduce energy consumption by constituting the title memory so as to divide and activate the word line. CONSTITUTION:Data to be written are inputted from input terminals DI0 to DI3. A column decoder 2e decodes the memory cell group selecting data from an input terminal WA3, and sets one of memory cell group selecting lines 6a and 6b at 1. Thus, the write bit lines to be driven at '0' or '1' according to the input data from the outside by means of writing circuits 3a-3d go to 13a-13d or 13e-13h, and the write bit lines to be charged and discharged are reduced by half. A row decoder 2c decodes the write row address data from an input terminal WA2 and sets one of pre-word lines 5 at 1. The logical sum of the output signal of the pre-word line 5 of the selecting lines 6a and 6b is outputted by an AND gate 7, and it is written through a gate 13a connected to the output terminal of the gate 7 to have produced 1 to a memory cell 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multi-port memory in which data can be simultaneously written to or read from a plurality of ports in an array of one set of memory cells.

[Conventional technology]

FIG. 2 is a layout/wiring diagram of memory cells and peripheral circuits of a conventional multi-port memory having a 4 word x 4 bit configuration. In the figure, 1 is a memory cell that holds 1-bit data, and here it is arranged in an array of 4 rows and 4 columns.

This array is hereinafter referred to as a memory cell array. 2a,
2b is a decoder. Decoder 2a has input terminal WA
Write address data is input from O and WAI, and a write word line 15 is connected to the output terminal of the decoder 2a. Read address data is input to the decoder 2b from input terminals RAQ and RAl, and a read word line 9 is connected to the output terminal of the decoder 2b. 3 is a write circuit, into which data to be written is input from data input terminals D■0 to DI3 (hereinafter collectively or commonly referred to as data input terminals DIJ), and each output terminal is connected to one write bit line. It is connected to 13. 4 is a sense amplifier, and its input terminals are each connected with one successive bit cotton 14, and data output terminals DOO to DO.
3 (Hereinafter, generally or commonly, [data output terminal DO
The read data is output to the J. The write word line 15 and the read word line 9 pass through the memory cell array in the row direction, and each is connected to the memory cells 1 in all columns on the corresponding row. write bit line 13,
The read bit lines 14 pass through the memory cell array in the column direction, and each read bit line 14 is connected to the memory cells 1 in all rows on the corresponding column.

In addition, input terminals WAO, WA1. Write bit line 13.
Write word line 15. Data input terminals D■0 to DI3.
The decoder 2a and the write circuit 3 constitute a write port,
Input terminals RAO, RAI.

Read bit line 14. Read word line 9. Data output terminals DOO to DO3, decoder 2b, and sense amplifier 4 constitute a read balk.

FIG. 3 is a circuit diagram showing the circuit of the memory cell 1 and the connection state between the memory cell 1 and each bit line and word line. The input terminal of the inverter circuit 16a and the output terminal of the inverter circuit 16b are connected to form a terminal A as a data holding node, and similarly the output terminal of the inverter circuit 16a and the input terminal of the inverter circuit 16b are connected to form a data holding node. Terminal B is formed. In addition,
Terminal A is an access gate (transmission gate)
It is connected to the write bit line 13 through 18a. 17
is a transmission inverter which receives the signal on terminal B as an input, and output terminal C is connected to read bit line 14 through access gate 18b. The gate input of access gate 18b is the input from read word 19.

As is clear from FIG. 2, one data input terminal D1 and one data output terminal Do correspond to each of the write bit line 13 and read bit line 14.

FIG. 4 shows an example of the write circuit 3, which consists of two stages of inverters.

FIG. 5 shows an example of the sense amplifier 4, which consists of a two-stage inverter and an input capable gate.

FIG. 6 shows another example of the sense amplifier 4, which is of a current sense type.

Next, the operation will be explained. Data is written using the write port. The data to be written is the data input terminal D.
The write bit line 13 is set to “1” or “0” by the write circuit 3 according to the value given to IO-DI3 from the outside.
is driven by. The word to be written among the four words is specified by write address data from input terminals WAO and WA1. The decoder 2a decodes it and sets one of the write word lines 15 to "1" and the other three to "0" according to the combination of input data values. therefore,"
The access gate lea of the memory cell 1 connected to the write word line 15 which has become "1" becomes conductive, and the write bit line 13 and the terminal A are electrically connected. Since the sum of the output resistance of the write circuit 3 and the on-resistance of the access gate 18a is set to be smaller than the output resistance of the impark 16b, as long as the access gate 18a becomes conductive, regardless of the initial values of the terminals A and H. , the value of terminal A becomes the same as the value of write bit line 13 driven by the data to be written from data input terminals 010 to D13. Writing is now complete. On the other hand, when the write word line 15 is set to "0", the write bit line 13 and terminal A are electrically disconnected, and the write word line 15 is changed from "1" to "0" by a flip-flop consisting of inverters 16a and 16b. The values of terminals A and H immediately before are held. Therefore, the write word line 1 becomes "0" due to the action of the decoder 2a.
New data is not written to memory cell l connected to cell 5.

Data reading is performed at the read port. The word to be read out of the four words is specified by read address data from input terminals RAO and RA1.

The decoder 2b decodes it and selects one of the read words 'fIA9' according to the combination of values of the manual data.
1" and the other three as "0". Therefore, the access gate 18b in the memory cell 1 connected to the read word line 9 which has become "1" becomes conductive, and the read bit line 1
4 and terminal B are the transfer inverter 17. access gate 18
electrically connected via b. The read bit 114 is thereby driven to the inversion of the value at terminal B, that is, the value at terminal A, and this value is sensed and amplified by sense amplifier 4 and output to data output terminals DOO-DO3.

Since the input impedance of the transfer inverter 17 viewed from the B terminal side is extremely high, the initial value of the read bit line 14 is not transferred to the terminal B via the terminal C.

Therefore, the values of terminals A and H held in the flip-flops made up of inverters 16a and 16b are not inverted by the read operation.

[Problem to be solved by the invention]

Since the conventional multi-port memory is configured as described above, when the write word line becomes "1", data is written to the memory cells in all columns of the corresponding row in the memory cell array. For this reason, one word corresponds to one line, and one
It was necessary to correspond one bit to a column.

As a result, there is no degree of freedom in the matrix ratio of the memory cell array.
The width of the write circuit and sense amplifier arranged corresponding to one bit is narrow, making layout difficult, and the height increases, increasing the area, and all memory cells connected to one word line are activated. As a result, current flows from the power supply into memory cells in all columns of one row, and as the number of columns increases, current consumption due to bit line charging and discharging increases.

The present invention has been made in view of these points, and its purpose is to provide a memory self-reflection array with n (2
A multi-port that can be divided into memory cell arrays (a natural number of 2 or more), make m (a natural number of 2 or more) columns of one memory cell array correspond to 1 bit, and activate memory cell groups of 1 / n columns of all columns. It's about getting memory.

[Means to solve the problem]

In order to achieve such an object, the multi-port memory according to the present invention has multiple columns of a memory cell array in which memory cells each having a data holding node and holding one bit of data are arranged in a matrix to a natural number n of 2 or more. a group of n memory cells arranged in a divided manner; first and second column decoders for decoding information for selecting the group of n memory cells;
First and second memory cell group selection lines connected to the output terminals of the first and second column decoders to select a specific one from each memory cell group, and row address information of the memory cell group to be accessed. a word line connected to the output terminal of the first row decoder and arranged across a plurality of memory cell groups, and a selection signal of a memory cell group selection line and a preword line. a write word line activated based on the output signal of the memory cell group and arranged within the memory cell group; a read word line connected to the output terminal of the second row decoder; and a data input for inputting data to be written. a terminal, a data output terminal that outputs read data, and first and second bit lines that penetrate in the column direction of the memory cell, the first bit line responding to input data from the data input terminal. the first bit line, the preword line, the write word line, the first memory by being driven to a value and the write word line controlling the electrical logical connection between the first bit line and the data retention node. The cell group selection line and the data input terminal form a first port, and the driving or non-driving of the second bit line to a value depending on the value of the data holding node by the memory cell is controlled by the read word line. By outputting a value corresponding to the value of the bit line from the output terminal, the second bit line, read word line, second memory cell group selection line, and data output terminal form a second port. This is what I did.

[Effect]

In the multi-port memory according to the present invention, only the write word line of the memory cell group in column 1/n of all the columns in one row of the memory cell array becomes "1", and data from outside the memory is transferred to the memory cell of the memory cell group. will be written to.

〔Example〕

An embodiment of the multiport memory according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block system diagram showing an embodiment of a multiport memory according to the present invention, and shows an n-2, 4 word x 4 bit configuration, and a total of 2 ports, a write port and a read port.

In FIG. 1, memory cells 1 are arranged in two rows and eight columns, forming a memory cell array divided into two memory cell groups in units of columns. 2c and 2d are row decoders, and 2e and 2f are column decoders. Write row address data is input to the row decoder 2C from an input terminal WA2, and a front word line 5 penetrating in the row direction is connected to its output terminal. Read row address data is input to the row decoder 2d from an input terminal RA2, and the read word line 9 is connected to its output terminal. The read word line 9 penetrates in the row direction, and is connected to each of the eight memory cells 1 in all columns of the corresponding pad.

Memory cell group selection data is input to the column decoder 2e from an input terminal WA3, and first memory cell group selection lines 6a and 6b are connected to its output terminal. Column decoder 2f similarly receives memory cell group selection data from input terminal RA3, and has its output terminal connected to second memory cell group selection lines 10a and 1Qb. 7 is the output signal of the front word line 5 and the memory cell group selection lines 6a, 6b.
This is a two-manual AND gate that takes a logical product with a selection signal of , and its output terminal is connected to a write word line 8 that activates only one row in one memory cell group.

The write word line 8 passes through the memory cell group parallel to the rows, and is connected to all four column memory cells 1 in the memory cell group at respective corresponding jumps. lla to llh are transmission gates of NMO3, one terminal of which is connected to write bit lines 13a to 1 as first bit lines, respectively.
3h, and the other terminal is connected to the output terminal of one of the write circuits 33 to 3d together with the terminals of the two transmission gates. That is, both terminals of transmission gates lla and lie are connected to the output terminal of write circuit 3a, similarly, other transmission gates llb and llf are connected to write circuit 3b, and transmission gates 11C and l1g are connected to write circuit 3C1.
Transmission gates 11d and llh are connected to the output terminal of write circuit 3d.

Transmission gates) 12a to 12h are similarly connected, one terminal is connected to each read bit line 14a to 14h as a second bit line, and the other terminal is connected to the terminals of the two transmission gates and connected to one of the sense amplifiers. Connected to one input terminal. That is, both terminals of transmission gates 12a and 12e are connected to the input terminal of sense amplifier 4a, and similarly, other transmission gates 12b and 12f are connected to sense amplifier 4b1.
The transmission gates 12c and 12g are connected to the input terminal of the sense amplifier 4C1, and the transmission gates 12d and 12h are connected to the input terminal of the sense amplifier 4d. In addition,
Gate inputs of transmission gates 11a to lid are selection signals of memory cell group selection line 6a. The same goes for the others, and the transmission gates l1g to llh are the memory cell group selection line 6b1 and the transmission gate 12a.
~12d are memory cell group selection lines 10a, and transmission gates 12e~12h are memory cell group selection lines 10b.
receive a signal from. In addition, write bit lines 13a to 13
h. The read bit lines 14a to 14h are connected to the memory cell 1 in the same manner as in the conventional example. - Next, the operation of the above embodiment will be explained. First, the write port will be explained. As in the conventional example, data to be written is externally applied to data input terminals DIO-DI3. The column decoder 2e decodes the memory cell group selection data from the input terminal WA3 and outputs the memory cell group selection data to the memory cell group selection line 6a.
, 6b to rlJ. From this, the write bit and bit lines driven to "0" or rlJ by the write circuits 33 to 3d according to external input data are 13a to 13d or 13e to 13h, and are not charged or discharged. The number of write bit lines used is halved. The row decoder 2c decodes the write row address data from the input terminal WA2, and sets one of the prefix word lines 5 to "1". The output terminal of the two-man AND gate outputs the only "1" as a result of outputting the logical product of the selection signals of the memory cell group selection lines 5a and 5b and the output signal of the prefix word line 5 by the two-man power AND gate 7. The write word line connected to the write word line is activated, and the access gate 1 connected to the write word line is activated.
Input data is written into memory cell l through 8a.

Next, the read port will be explained. Column decoder 2f
decodes the memory cell group selection data from the input terminal RA3 and sets either the memory cell group selection line 10a or lQb to "1", and the row decoder 2d decodes the memory cell group selection data from the input terminal RA2.
The read row address data from the read word line 9 is decoded, and one of the read word lines 9 is set to "1". Data from four memory cells 1 in a row in a memory cell group consisting of selection signals on memory cell group selection lines 10a and lQb and output signals on read word line 9 is sensed and amplified by sense amplifiers 43 to 4d, and the data is It is output to output terminals DOO to DO3.

Note that the data writing and reading procedures in the memory cell 1 are the same as in the conventional example.

In the above embodiment, only the write word line is divided, but as shown in FIG. 7, the invention can also be applied to successive word lines. In FIG. 7, 7a and 7b are AND gates. By doing so, the power consumption due to bit line charging and discharging during continuous output can be halved.

Furthermore, although the transmission gate is attached to the write bit line in the above embodiment, since the memory cell group is selected by the write word line, it may be removed as shown in FIG. However, although the area is somewhat smaller, the driving force of the write circuit is burdened, and the delay time may increase.

Further, although the input and output terminals are arranged alternately in the above embodiment, the input terminals and the output terminals may be arranged together as shown in FIG. 9.

In addition, in the above embodiment, an explanation was given of a 4-word x 4-bit configuration with two ports, a write port and a read port, divided into two, but these numbers can be generalized by using natural numbers i, j, and n. It is. That is, i words x j bits, at least 1 write port or read/write shared port.
The memory cell array is divided into n ports and n ports, and so on.

Further, as shown in FIG. 10, if the pre-word line enable signal WE is manually input to the row decoder 2c, if the signal WE is "1", it will operate as a normal decoder, and if the signal WE is "O", it will operate as a normal decoder. If all prefix word lines are "0",
Data in all memory cells is retained.

The method described above can also be applied to multi-port memories with ports other than 2. FIG. 11 shows a memory cell circuit in the case of a total of 3 ports, 1 write port and 2 read ports. In the same figure, 9a.

9b is a read word line, 13 is a write bit line, 14a
, 14b is a read bit line, 15a, 15b are write word lines, 16ap, 16an and 16bp, 16bn
17 is an inverter, and 18a, 18ba, and 18bb are transmission gates.

Multi-port memory itself may be integrated into a single LSI, but as shown in Figure 12, it is
It often forms the data bus of a microprocessor together with an ithmetic logic unit and a shifter. In general, an ALU or a shifter requires a width 50 to 100 times the manufacturing wafer process design rule per bit, whereas the width of one column of a memory cell array is only 15 to 30 times the design rule. Therefore, the number of memory cell array columns per 1 bit of ALU or shifter is 2 to 4.
By doing so, it becomes possible to make the width per bit the same between the multiport memory and the ALU or shifter without any unnecessary gaps.

FIG. 13 shows an example of a layout in which these are placed in close contact with each other. In the figure, 20 is a decoder, 21 is a control circuit, 22 is a multiport memory, and 23 is an ALU.

24 is a shifter, and the area delimited by broken lines corresponds to 1 bit width.

Furthermore, although the memory cell 1 of the conventional example and the embodiment is shown as having a flip-flop consisting of two inverters 16a and 16b (see FIGS. 3 and 11), the first
As shown in FIG. 4, a dynamic type may be used in which the data value is determined based on the presence or absence of charge stored in the charge storage capacitor 25. In this case, since the value output to the read bit line 14 is the inversion of the value previously written from the write bit line 13, it is necessary to invert the data again by the write circuit 3 or sense amplifier 4.

[Effects of the Invention] As explained above, the multiport memory according to the present invention has the following effects by dividing and activating the word line.

■More freedom in the aspect ratio of the memory cell array layout, the number of rows can be reduced, and the number of columns per bit increases.
The layout of peripheral circuits such as a write circuit and a sense amplifier becomes easier and the height becomes lower.

■By shortening the length of the write bit line and read bit line and by performing row selection hierarchically, the number of columns with DC power supply paths can be reduced, reducing the delay time required for bit line charging and discharging and the power consumption. becomes smaller.

(2) The data bus layout by combining ALU etc. becomes easier and the area becomes smaller.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of a multi-port memory according to the present invention, FIG. 2 is a block diagram showing a conventional multi-port memory, FIG. 3 is a circuit diagram of a memory cell, and FIG. are the circuit diagrams of the write circuit, Figures 5 and 6.
FIG. 7 is a circuit diagram of a sense amplifier, FIGS. 7 to 9 are block diagrams showing second to fourth embodiments of a multi-port memory according to the present invention, FIG. 1θ is a circuit diagram of a row decoder for writing, Figure 11 is a circuit diagram of a memory cell of a 3-port memory.
FIGS. 12 and 13 are block diagrams and layout diagrams showing an example in which a multi-port memory according to the present invention is integrated into a data bus, and FIG. 14 is a circuit diagram of a dynamic memory cell. 1...Memory cell, 2c-2f...Decoder, 3a
~3d... Write circuit, 4a-4d... Sense amplifier, 5... Front word line, 6a, 6b... First memory cell group selection line, 7... AND gate, 8... ...Write word line, 9...Read word line, 10a, 10
b...Second memory cell group selection line, lla to llh,
12a-12h...transmission game), 13
a to 13h...first bit line, 14a to 14h...
- Second bit line, WA2. WA3. RA2. RA3・
...input terminal, DIO to DI3...data input terminal,
DOO~DO3...Data output terminals.

Claims (1)

[Claims] A group of n memory cells arranged by dividing a plurality of columns of a memory cell array in which memory cells each having a data holding node and holding one bit of data in a matrix, and dividing the memory cells into a natural number n of 2 or more, and first and second column decoders for decoding information for selecting a group of memory cells;
first and second memory cell group selection lines that are connected to the output terminal of the column decoder and select a specific one of each memory cell group; and a first and second memory cell group selection line that decodes row address information of the memory cell group to be accessed. a second row decoder, a pre-word line connected to the output terminal of the first row decoder and arranged over a plurality of memory cell groups, a selection signal of the memory cell group selection line and a pre-word line connected to the output terminal of the first row decoder; a write word line activated based on an output signal and arranged within the memory cell group; a read word line connected to the output terminal of the second row decoder; and data inputting data to be written. an input terminal, a data output terminal that outputs read data, and a first terminal that penetrates in the column direction of the memory cell.
and a second bit line, the first bit line is driven to a value according to input data from the data input terminal, and the write word line connects the first bit line and the data holding node. By controlling the electrical and logical connections of the first bit line, the front word line, the write word line, the first memory cell group selection line, and the data input terminal, the first port and the driving or non-driving of the second bit line by the memory cell to a value responsive to the value of the data retention node is controlled by the read word line to a value responsive to the value of the second bit line. is output from the output terminal, so that the second bit line, the read word line, the second memory cell group selection line, and the data output terminal form a second port.