JPH0129874Y2 - - Google Patents

Description

[Detailed Description of the Invention] (Field of Industrial Application) The present invention relates to a call sign display device for receiving Hagelberger encoded data including call sign data and displaying the call sign in an amateur radio communication device.

(Background of the invention) In an amateur wireless communication device, data including at least empty channel frequency data and call sign data is Hagelberg encoded, a frame synchronization signal is added, and the transmitted signal is received.
It has been proposed to pull the receiver into an empty channel frequency and allow it to communicate.

(Purpose of the invention) The object of the invention is to provide a call sign display device for amateur radio communication equipment as described above, which can display the call sign of the other party each time a radio wave containing call sign data is received. .

(Structure of the idea) The present invention will be explained below with reference to examples.

Figures 1a and 1b are a wiring diagram and an external view of the main parts showing the configuration of an embodiment of the present invention.

1 and 2 are amateur radio communication devices, the reception output of which is supplied to a call sign display device 3. The call sign display device 3 includes a changeover switch 4 that receives the received outputs from the amateur radio communication devices 1 and 2 and selectively directs the received outputs of either one to the call sign display device main body 5. One input terminal of the changeover switch 4 is configured to be connected to the output terminal and the speaker 7 of the amateur wireless communication device 1, and the other input terminal of the changeover switch 4 is configured to be connected to the output terminal and the speaker 8 of the amateur wireless communication device 2. be. For example, as shown in FIG. 1b, plugs _1-1 and 2-1 are connected to the output terminals of amateur wireless communication devices 1 and 2, respectively, _and plugs 7-1 are connected to speakers 7 and _8, respectively. ，
_8-1 is inserted into jacks _1-2 , _2-2 , _7-2 and _8-2 provided on the call sign display device 3 for connection.

Therefore, the received sounds of the amateur wireless communication devices 1 and 2 can be heard simultaneously on the speakers 7 and 8, and the call sign in the received data from one of the amateur wireless communication devices 1 or 2 selected with the changeover switch 4 will be described later. It can be displayed as shown.

Next, the call sign display device main body 5 will be explained.

FIG. 2 is a block diagram showing an example of the main body of the call sign display device.

First, prior to explaining the call sign display device main body 5, a format showing an example of the structure of data to be transmitted will be explained.

FIG. 3 shows the format of the data to be transmitted. Digital code BCD 5 digits (20 bits) corresponding to bit synchronization data (50 bits), frame synchronization data (15 bits), group code data, etc.
Empty channel frequency data BCD 6 digits (24 bits),
It consists of command (8 bits), call sign data, 6 characters of ASCII code (48 bits), and the 100 bits from the digital code to the call sign data are Hagelberger encoded, resulting in a total of check bits and check bits as shown in Figure 4. It is transmitted as 212-bit data in which data bits appear alternately. For example, this data is MSK (minimum shift keying) with a data transmission rate of 1200B.PS.
Transmit as a signal.

The call sign display device main body 3 shown in FIG.
This shows the case where the call sign in the data explained above is displayed.

The transmitted data is demodulated by an amateur radio communication device in accordance with the transmission modulation, and
The MSK signal is demodulated and supplied from the reception side external speaker terminals of the amateur radio communication devices 1 and 2 via the changeover switch 4. The supplied data is amplified by an amplifier 11 and supplied to a waveform shaping circuit 13 via a low-pass filter 12 for waveform shaping. The waveform-shaped data is passed through a delay circuit _14-1 that delays the time of one bit of data, and a delay circuit 1.
_4-1 and the output of the waveform shaping circuit 13 are supplied to a delay detection circuit 14 consisting of an exclusive OR circuit (-) _14-2 , which receives the outputs of the waveform shaping circuit 13 and performs delay detection. The output of the delay detection circuit 14 is supplied via a low-pass filter 15 to a waveform shaping circuit 16 for waveform shaping. The output of the waveform shaping circuit 16 is supplied to a latch circuit 17 that latches the output of the waveform shaping circuit 16, and the output of the waveform shaping circuit 16 is supplied to a latch circuit 17 that is phase-synchronized with the data transmission speed.
It is supplied to a clock pulse generation circuit 18 which generates a clock pulse of Hz, and the output clock pulse of the clock pulse generation circuit 18 is supplied to a data latch circuit 17 as a strobe pulse.

The latch output of the data latch circuit 17 is a 15-bit shift register _18-1 , a shift register 18
- Exclusive OR circuits (-) _18-2 to _18-16 each having each bit of ₁ as one input, AND gate 18-17 having one input as the output of the exclusive OR circuits _18-2 to _{18-16 .} and and gate 18-
Flip-flop circuit 1 set with ₁₇ outputs
Frame synchronization data detection circuit 1 consisting of _8-18
It is supplied to 8. Here, exclusive OR circuit 18-
₂ to _18-5 and _18-8 to _18-13 , the +V voltage is applied to the exclusive OR circuits _18-6 and 18.
_-7 , _18-14 to _18-16 , a voltage of O potential is applied as the other input, and it goes without saying that this corresponds to the bit pattern of the frame synchronization data.

The latch output of the data latch circuit 17 is “212”
It is supplied to a bit shift register 19. On the other hand, the output clock pulse of the clock pulse generation circuit 18 is supplied as an input to one of the AND gates _20-1 and _20-2 .
_-1 is supplied with the output of the flip-flop _18-18 via the inverter _20-3 as the other input, and the AND gate _20-2 is supplied with the output of the flip-flop _18-18 as the other input; The output of the AND gate _20-1 is supplied as a shift pulse to the shift register _18-1 .
The output of the AND gate _20-2 is supplied as a clock pulse to the "212" counter 21, and is also supplied via the clock switching circuit 22 to the shift register 19 as a shift pulse.

The count-up output of the counter 21 is supplied to the clock switching circuit 22 as a switching signal, and the switching signal shifts the output pulse of the clock pulse generator 23 to the shift register 19 instead of the output of the AND gate _20-2 . It is supplied as. Here, the frequency of the output pulse of the clock pulse generator 23 is equal to the frequency of the output pulse of the clock pulse generator 23.
The frequency is set higher than the frequency of the output clock pulse of No.8.

24 is a “424” counter;
counts shift pulses to the shift register 19 based on the count-up output of the counter 21. The shift pulse to the shift register 19 is supplied to the AND gate 26 via the frequency divider 25 with a frequency division ratio of 2, and the same shift pulse is supplied directly to the AND gate 27. The output of the counter 24 indicating that there is a
Gates 6 and 27 are opened and closed. Further, the output of the counter 24, which indicates that the counter 24 has not counted up "424", is sent via an inverter 28 to an AND gate _34-15 , which will be described later.
It is supplied to

On the other hand, the Hagelberger decoding circuit 29 consists of exclusive OR circuits (-) _29-1 and _29-2 , exclusive OR circuits (EX-OR) _29-3 , _29-5 , and an AND gate _29-6 , and The output of the circuit _29-5 is written to the 14th bit of the shift register 19, and the error correction is performed using the output of the AND gate 26.

The output of the shift register 19 is supplied to a “212” bit shift register 30, and
Output data of 0 is supplied to the data latch circuit 31 and latched. The output of the AND gate 27 is supplied as a shift pulse to the shift register 30,
Further, the output of the AND gate 27 is supplied to the data latch circuit 31 as a strobe pulse via a frequency divider 32 with a frequency division ratio of 2.

The latch output of the data latch circuit 31 is supplied to a 100-bit shift register 33, and the output pulse of the frequency divider 32 is supplied to the shift register 33 as a shift pulse. shift register 33
The upper 4 bits of the upper 52 bits are 0 to 9.
BCD comparison circuit _34-1 to detect whether it is BCD
_34-13 , and the lower 48 of shift register 33
Each 8 bits are ASCII code 0-9,
ASCII comparison circuit 35 that detects whether it is A to Z
_-1 to _35-6 , and each output is supplied to AND gate _34-14 , and the shift register 33
Detects that the data stored in is BCD data and ASCII data. and gate 3
The output of _4-14 is supplied to AND gate _34-15 .

The lower 48 bits of the shift register 33 are supplied to a data latch circuit 36 for latching, and the output of the data latch circuit 36 is supplied to a display means 37 for display. In addition, and gate _34-15
The output of is supplied to the data latch circuit 36 as a strobe pulse.

The data received by the amateur radio communication device and demodulated in MSK is in the format shown in FIG. 3 described above.

This data is passed through amplifier 11 and low pass filter 1.
2. The waveform is shaped and detected by the waveform shaping circuit 13 and the delay detection circuit 14, the waveform is shaped by the low pass filter 15 and the waveform shaping circuit 16, and the signal is supplied to the data latch circuit 17.

On the other hand, the data output from the waveform shaping circuit 16 is supplied to the clock pulse generation circuit 18, and the clock pulse generation circuit 18 outputs a 1200 Hz clock pulse that is phase synchronized with the data transmission speed, and is supplied to the latch circuit 17 as a strobe pulse. Ru. Therefore, the supplied data is latched by the data latch circuit 17. Furthermore, since the gate of the AND gate _20-1 is controlled to be open, the output clock pulse from the clock pulse generation circuit 18 is supplied as a shift pulse to the shift register _18-1 , and the latch output of the data latch circuit 17 is sequentially shifted. It is transferred to the register.

When the frame synchronization pulse is stored in the shift register _18-1 , the exclusive OR circuit _18-2 ~
The output of gate _18-16 goes high, the output of AND gate _18-17 goes high, and flip-flop _18-18 is set. As a result, the gate of AND gate _20-1 is controlled to be closed, and the supply of shift pulses to shift register _18-1 is cut off. On the other hand, since the flip-flop _18-18 is set, the gate of the AND gate _20-2 is controlled to be open, and the clock pulse from the clock pulse generation circuit 18 is supplied as a shift pulse to the shift register 19 via the clock switching circuit 22. The latch output of the data latch circuit 17 is sequentially transferred to the shift register 19.
Therefore, the data appearing subsequent to the frame synchronization data, that is, the digital code, is transferred to the shift register 19. The shift pulses of the shift register 19 are counted by a counter 21, and when the counter 21 counts "212", the output of the counter 21 causes the clock switching circuit 22 to generate a clock pulse supplied via the AND gate _20-2. The clock pulses from circuit 18 are switched to clock pulses from clock pulse generator 23. Also, when the counter 21 counts "212", the shift register 19 has all 212 bits added with the check bits shown in FIG.
Bits (digital code, empty channel frequency data, commands, call sign data and check bits) are stored.

By switching the clock switching circuit 18 to the clock pulse generator 23 side, the output clock pulse from the clock pulse generator 23 is supplied to the shift register 19 as a shift pulse.
At the same time, the counter 24 counts. At the same time, the frequency is divided by two by the frequency divider 25.

In this case, if the counter 24 has not counted up yet, the AND gates 26 and 27 are controlled to be open, and the output pulse of the clock pulse generator 23 whose frequency has been divided by 2 by the frequency divider 25 is applied. Synchronously, the output of the Hagelberger decoding circuit 29 is written to the 14th bit of the shift register 19, and any errors are corrected. However, this write is in shift register 19.
Since this is performed using a pulse obtained by dividing the frequency of the shift pulse by 2, it is performed only on the data bits among the "212" bits, and this operation is performed 106 times. As a result, the data bits in the data stored in the shift register 19 are corrected, the corrected 212 bits are stored in the shift register 8, and the count value of the counter 24 is "212".

The contents of the shift register 30 are sequentially transferred to the data latch circuit 3 by the output clock pulse of the clock pulse generator 23 via the AND gate 27.
1. On the other hand, the data latch circuit 31 is supplied with the output pulse of the frequency divider 32, which is obtained by dividing the output clock pulse of the clock pulse generator 23 by two through the AND gate 27, as a strobe pulse.
In this case, the check bit stored in the shift register 30 is not latched, but only the data bit is latched and transferred to the shift register 33. As a result, the shift register 33 has the second
In the figure, the digital code, empty channel frequency data, command, and call sign data are sequentially stored from the right side, and when the storage is completed, the count value of the counter 24 becomes "424".

As a result, the AND gates 26 and 27 are controlled to be closed, and the shift register 33 stores 100 bits of digital code, empty channel frequency data, command, and call sign data. Note that here 212/2=106
There are 106 data bits, but the first 6 bits are for correction.
It is taken out of the shift register 33.

The digital data stored in the shift register 33, empty channel frequency data, and commands are
Supplied to BCD comparison circuits _34-1 to _34-13
It is checked whether the command is BCD (0 to 9) and whether the command is "00", and the call sign data is supplied to the ASCII comparison circuits _35-1 to _35-6 , and the call sign data is checked if the ASCII code is 0.
~9, A to Z is checked. When everything is satisfied by this check, the output of the AND gate _34-14 becomes a high potential. On the other hand, at this time, the counter 24 has a count value of "424".
has reached the count-up of and gate 3
_4-15 has its gate controlled to be open,
AND gate 34 via AND gate _34-15
-14 output, the lower 48 bits of the shift register 33 are latched by the data latch circuit 36 and supplied to the display means 37.

The latch output from the data latch circuit 36 is decoded by a decoder in the display means 37, and the call sign is displayed on the display means 37.

After that, each circuit is initialized to prepare for reception of the next data. Therefore, a call sign will be displayed each time data is received.

(Effects of the Invention) As explained above, according to the present invention, it is possible to connect with two systems of amateur wireless communication devices, and to reproduce the received sound from the two systems of amateur wireless communication devices with a speaker. Furthermore, a call sign can be displayed by selecting one of the data output from the two systems of amateur wireless communication devices. Furthermore, there is no need to modify existing amateur radio communication equipment.

[Brief explanation of the drawing]

FIGS. 1a and 1b are a wiring diagram and an external view of main parts showing the configuration of an embodiment of the present invention. FIG. 2 is a block diagram showing an example of the main body of a call sign display device according to an embodiment of the present invention. FIG. 3 is a diagram showing the data format. FIG. 4 is an explanatory diagram showing the bit structure of transmission data. 1 and 2...amateur wireless communication device, 3...
Call sign display device, 4...Switch switch, 5
...The main body of the call sign display device.

Claims (1)

[Scope of utility model registration request] A call sign display device main body receives Hagelberger encoded data including at least call sign data and displays a call sign, and one input terminal is supplied with a reception signal from a first amateur wireless communication device. The first speaker is connected, and the other input terminal is supplied with a reception signal from the second amateur wireless communication device, and the second speaker is connected, and the output terminal is connected to the input terminal of the call sign display device main body. A call sign display device comprising a changeover switch connected to the call sign display device.