JPH01295528A - Dynamic frequency divider - Google Patents

Abstract

PURPOSE:To obtain a value except 2<n> as a frequency division ratio by connecting plural (n) pairs each consisting of an inverter circuit and a switch circuit in cascade and feeding back an output of the switch circuit of the final stage to the input of the 1st stage inverter circuit. CONSTITUTION:An inverter circuit 22 and a switch circuit 31 are used as a pair and plural pairs are connected in cascade. The switch circuits 31, 32, 33 are conductive when each control input is at a high level and opened when its control input is at a low level. The operation of the inverter circuits 21, 22, 23 is delayed and the output is inverted to the input after an operation delay time td after the input is inverted. Every time the voltage at the terminal 1 goes to a high level, the output voltage of each inverter circuit is given as the input voltage of the inverter circuit of the next stage. Thus, the voltage level at an output terminal 4 is inverted by three times of changes in the voltage at the terminal 1 and the voltage level at the output terminal 4 is restored to the original level again by the next 3 changes and the frequency division ratio reaches 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is suitable for use in a frequency synthesizer in the microwave frequency band.

The present invention provides a dynamic frequency divider in which an inverter circuit and a switch circuit connected to the output thereof are one element, and by cascading these elements in multiple stages, 2"
This realizes a frequency division ratio other than the above.

[Conventional technology]

FIG. 5 shows a conventional dynamic frequency divider.

This circuit was published in the June 1983 issue of the IEEE journal sc (M., Rocchi et al., “GaAs
digital dynamic ICs for ap
applications up to 10GHz”,
IFiBFi Journalof 5olid-3t
ate C1rcuits, vow, 5C-18,
No, 3. P, 371゜June 1983.
), one inverter circuit 2 and a switch circuit 3 connected to this output, the output of this switch circuit 3 is connected back to the human power of the inverter circuit 2, and the switch circuit 3 is Control human power input terminal 1
The output of this switch circuit 3 is connected to the output terminal 4.

FIG. 6 shows an operation time chart of this circuit.

That is, in this circuit, when the voltage V+ of the input terminal 1 is at the /'% level, the switch circuit 3 becomes conductive, and the output voltage V3 of the inverter circuit 2 is outputted to the output terminal 4 as the output voltage V2, and the inverter circuit 2 will be returned to human power. When the inverter circuit 2 changes its input terminal,
Its operation delay time t.

After , the output voltage is inverted.

As shown in FIG. 6, at time t=Q, when the human power V2 of the inverter circuit 2 is at a low level and its output V is at a low level, when the voltage V1 at the input terminal 1 becomes a 7'i level, the switch circuit 3 conducts, and the input V of the inverter circuit 2
2 is reversed. As a result, the output V3 of the inverter circuit 2 is inverted after an operation delay time t (t=2). At this time, input terminal 1 (7) voltage 1lEVI has returned to low level, so even if voltage V3 becomes low level, voltage 2 remains at NO1 level, and this is maintained until the next conduction state. Ru. Next, at time t=3, when the voltage at the input terminal 1 becomes high level, the switch circuit 3 becomes conductive again, and the input voltage V2 of the inverter circuit 2 is inverted to a low level equal to the output voltage V3. After a time period of 1 d, the output voltage V3 is inverted (t=5).

At this time, the voltage V1 of the input terminal 1 has already returned to the low level, so even if the voltage V3 becomes high level, the voltage V2 remains at the low level, and this is maintained until the next conduction state. By repeating this, the signal period at terminal 4 becomes twice that of the signal period at terminal 1.

This dynamic frequency divider has a simpler configuration than a static frequency divider using a flip-flop circuit, and is capable of high-speed frequency division operation.

This dynamic frequency divider has a frequency division ratio of 2 (the period of the output signal at the output terminal 4 relative to the period of the human input signal at the input terminal 1), and by connecting this dynamic frequency divider in multiple stages, the frequency division ratio can be set to 2. ” can be realized.

[Problem that the invention seeks to solve]

However, since this dynamic frequency divider cannot realize a frequency division ratio other than 2r', it lacks versatility in frequency synthesizers and other application circuits.

The present invention is an improvement on this, and aims to provide a circuit that can realize a value other than 2'' as a frequency division ratio by taking advantage of the characteristics of a dynamic frequency divider.

[Means for solving problems]

The present invention uses an inverter circuit and a switch circuit connected to the output of the inverter circuit as one element, and a plurality of these elements are connected in series in one stage, and the output of the switch circuit in the final stage is connected to the output terminal. The present invention is characterized in that it includes a circuit that is feedback-connected to the human power of the first-stage inverter circuit, and in which control signals for the switch circuits of the respective elements are commonly connected to an input terminal.

Here, "inverter circuit" refers to a circuit that sends out an output signal with an inverted phase relative to an input signal, and phase inversion type amplifiers, NAND circuits, NOR circuits, EXOR circuits, etc. are included in the inverter circuit referred to here. .

The inverter circuit is selected so that its operation delay time t is longer than the time during which the switch circuit becomes conductive within one cycle of the signal at the input terminal, and smaller than one cycle of the signal at the input terminal.

In the above configuration, if the outputs of the plurality of inverter circuits are in a specific combination and the frequency divider may operate in an undesired mode in that case, a logic circuit is provided to detect the specific combination, By forcibly changing the output level of some of the plurality of inverter circuits in accordance with the detection output of this logic circuit, operation in an undesired mode can be avoided.

[Effect]

The voltage level applied to the input of the inverter circuit is inverted and appears at the output after the operation delay time t of the inverter circuit has elapsed. The level of this output is transmitted to the next stage by a switch circuit that becomes conductive in synchronization with the signal at the input terminal. Therefore, in a circuit in which the above elements are cascaded in one stage, when a pulse is applied to the input terminal once, the voltage level at the output terminal is reversed, and when a pulse is input to the input terminal once, the voltage level at the output terminal returns to the original level. Return to

In other words, one output pulse is sent out for every 2n input pulses, resulting in a frequency divider with a frequency division ratio of 2n.

With the above connection, a practically useful circuit with a frequency division ratio of 6 or 10 can be realized. Using this, a dual modulus pulse swallow counter can be realized, and by using this, the degree of freedom in designing a frequency synthesizer can be greatly improved.

〔Example〕

FIG. 1 is a block diagram of a circuit according to an embodiment of the present invention. This circuit has an inverter circuit 22 and a switch circuit 31 as a set of elements, and is a circuit in which three sets are connected in cascade so that the output of each set is connected to the human power of the next stage. The output of the switch circuit 33 is connected back to the human power of the first stage inverter circuit 21. In addition, each switch circuit 31
．． 32.330 control inputs are connected in common and connected to input terminal 1, and the output of the switch circuit 33 of the third stage frame is connected to output terminal 4.

Each switch circuit 31, 32, 33 is in a conductive state when its control input is at a high level, and is in an open state when its control input is at a low level. Also each inverter circuit 21.22.23
There is an operation delay, and after an operation delay time td after the human power is reversed, the output is reversed to the level opposite to that of the human power.

The overall operation of the circuit shown in FIG.
When the voltage changes three times, the voltage level of output terminal 4 is reversed,
The voltage level of the output terminal 4 returns to the original level again in the next three times. In other words, when input terminal 1 is pulsed 6 times, output terminal 4 is
This means that one pulse will be generated. In other words, the division ratio is 6
become.

Further details of the operation will be explained using the time chart shown in FIG. ■, is the voltage of input terminal 1, V21, V2
2. Vzalt is the input voltage of the I'/heart circuit 21, 22, 23, V 31, V 32, V 33 is the input voltage of each switch circuit 31, 32, 330.

Focusing on the inverter circuit 21, t= when its input terminal V21 is at low level and the output voltage V31 is at high level.
3, when the voltage at input terminal l becomes high level,
Each switch circuit 31, 32, 33 becomes conductive at the same time, and the voltage V 21 is set to a high level equal to the voltage V 33 of the previous stage. After the operation delay time t of the inverter circuit 21 has elapsed, the voltage V 31 will change to the input terminal V
21 to the opposite level, that is, to the low level (t=
5). At this time, the voltage v1 of the input terminal has already returned to the low level and each switch circuit 33 is in an open state, so the input voltage V21 is maintained at the high level.
This is maintained until time t=12 when the voltage V33 then becomes low level and the switch circuit 33 becomes conductive.

Similar operations are performed at the next stage of inverter circuit 22 and the next stage of inverter circuit 23 at sequentially shifted times. Then, when six pulses are input to input terminal 1, all inverter circuits 21 and 22
．． 23 returns to its initial state.

That is, one pulse is sent from the output terminal 4 for every six pulses from the input terminal 1, and the device operates as a frequency divider with a frequency division ratio of 6.

Here, considering the operation delay time t of the inverter circuit, it is preferable to use a time corresponding to the input signal period of the input terminal 10 as the operation delay time t. More specifically, under ideal conditions as shown in the time chart shown above, the operation delay time is 1. is required to be larger than the time width during which the switch circuit is in a conductive state (corresponding to the pulse width of the input signal) and smaller than the period of the input signal.

However, the switch circuit also has an operation delay time, and
In a practical circuit, the operating waveform has a slope with respect to the time axis, so it is desirable to select and design the characteristics of each element with a margin corresponding to the desired operating cycle.

Solution 3 FIG. 3 is a block diagram of a circuit according to a second embodiment of the present invention. This operation time chart is shown in FIG. This circuit has an inverter circuit and a switch circuit connected to its output as a set of elements, and these elements are connected in cascade in five stages. The control human power of each switch circuit is commonly connected to the input terminal 1, and the switch circuits are operated in unison. Further, the output of the final stage switch circuit is feedback-connected to the input of the first stage inverter circuit, and the output of this final stage switch circuit is connected to the output terminal 4.

In this second embodiment circuit, the input voltage of each inverter circuit is inverted, and the operation delay time t of each inverter circuit is
will later appear in its output. The voltage appearing at the output is transmitted to the next stage by each switch circuit which becomes conductive in accordance with the signal at input terminal 1, each time it becomes conductive.

Therefore, the voltage at output terminal 4 will be in an inverted state when a pulse is applied to input terminal 1 five times, and
When a pulse is applied five times to , it returns to its original state. That is, an output pulse is sent out once every 10 times an input pulse is applied, resulting in a frequency divider with a frequency division ratio of 10.

Since the operation time chart shown in FIG. 4 can be similarly understood, detailed explanation will be omitted.

FIG. 7 is a block diagram of a circuit according to a third embodiment of the present invention. This circuit is obtained by adding a mode setting circuit to the circuit of the first embodiment described in FIG. 1 and improving its operation.

The mode setting circuit connects the output terminal of each inverter circuit to the input of one AND circuit 6, and connects the output of this AND circuit 6 to the signal feedback-connected to the first stage inverter circuit via an OR circuit. It is something.

The first embodiment circuit explained in FIG. 1 operates as a frequency divider with a frequency division ratio of 6, but under some conditions the outputs of all inverter circuits become uniformly high or low level. and operate in a different mode. This is shown in FIG. 8 as a time chart of the undesired mode. That is, in this undesired mode, the output voltages V31, V32, and V33 of each inverter circuit are all at a high level at time 1=0, and when the frequency divider is operated from this point, its frequency division ratio is 2. becomes.

The third embodiment circuit shown in FIG. 7 has a mode setting circuit added to prevent the frequency divider from falling into an undesired mode. That is, the output of each inverter circuit is connected to the input of one AND circuit 6, and when this AND circuit 6 has an output, that is, when the outputs of all the inverter circuits match, the first stage inverter Force the circuit to reverse. With this mode setting circuit, even if the circuit falls into an undesired mode at startup or due to other conditions, it can be forcibly returned to the desired mode. When this circuit is in the desired mode, the voltage levels of the AND circuits 6 do not all match, so the addition of this mode setting circuit does not interfere with the operation in the desired mode.

The example shown in FIG. 7 describes a case where the number of cascaded circuits is 3 and the frequency division ratio is 6, and the outputs of the three inverter circuits are at the same level. For dynamic frequency dividers with various frequency division ratios, undesired modes may occur under different conditions, and in these cases, a logic circuit that similarly detects the conditions that result in the undesired mode is required. By forcibly inverting the output level of some of the inverter circuits according to the detection output of this logic circuit, it is possible to realize a configuration that avoids operating in the undesired mode.

No. 9ml is a block diagram of a circuit according to a fourth embodiment of the present invention. This circuit is an example of an applied circuit of the present invention. That is, in FIG. 9, the frequency divider 41 is the first embodiment circuit with a frequency division ratio of 6 shown in FIG. This is an example circuit. The two frequency dividers 41 and 42 are operated in parallel, and their outputs are led to the output terminal 4 via a switching circuit. The switching circuit is configured such that either the switching circuit 51 or 52 becomes conductive according to the signal from the switching control input terminal 5.

By using the circuit shown in FIG. 9, it is possible to realize a frequency division ratio of 6 or 10 by switching with a 1-bit switching signal, which is extremely useful in a frequency synthesizer.

〔Effect of the invention〕

As explained above, according to the present invention, it operates stably as a dynamic frequency divider up to an extremely high frequency, and while maintaining the three excellent characteristics of simple circuit configuration, It is possible to realize a peripheral device.

Furthermore, the configuration in which a mode setting circuit is added has the effect of reliably avoiding the inconvenience of the circuit falling into an undesired mode and operating at a frequency division ratio other than the desired frequency division ratio.

INDUSTRIAL APPLICABILITY The present invention can be applied to a frequency synthesizer using microwave frequencies to improve the degree of freedom in its design and to significantly simplify its configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of the present invention. Figure 2 is an operation time chart. FIG. 3 is a block diagram of a second embodiment of the present invention. Figure 4 is an operation time chart. FIG. 5 is a block diagram of a conventional circuit. Figure 6 is an operation time chart. FIG. 7 is a block diagram of a circuit according to a third embodiment of the present invention to which a mode setting circuit is added. FIG. 8 is a time chart explaining an undesired mode. FIG. 9 is a block configuration diagram of a fourth embodiment circuit showing an application example of the present invention. 1... Input terminal into which the signal to be divided is input, 4...
Output terminal to which the frequency-divided signal is sent out, 5... Terminal to which the switching control signal is input, 6... AND circuit, 7...
OR circuit. Patent Applicant Nippon Telegraph and Telephone Corporation Agent Patent Attorney Naotaka Ide; ; 1-;>:; Ta 5 Ta 5

Claims (1)

[Claims] 1. An inverter circuit and a switch circuit connected to the output of the inverter circuit are one element, and these elements are connected in series in multiple stages, and the output of the switch circuit in the final stage is connected to the output terminal. What is claimed is: 1. A dynamic frequency divider comprising: a circuit which is connected and feedback-connected to the input of a first-stage inverter circuit, and in which control signals of the switch circuits of the respective elements are commonly connected to an input terminal. 2. The dynamic frequency divider according to claim 1, further comprising: a logic circuit for detecting that the outputs of the plurality of inverter circuits become a specific combination that operates in an undesired mode; and circuit means for forcibly inverting a part of the output of the dynamic frequency divider.