JPH01291217A - Active matrix substrate - Google Patents

Active matrix substrate

Info

Publication number
JPH01291217A
JPH01291217A JP63121557A JP12155788A JPH01291217A JP H01291217 A JPH01291217 A JP H01291217A JP 63121557 A JP63121557 A JP 63121557A JP 12155788 A JP12155788 A JP 12155788A JP H01291217 A JPH01291217 A JP H01291217A
Authority
JP
Japan
Prior art keywords
lines
line
scanning
active matrix
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63121557A
Other languages
Japanese (ja)
Inventor
Yoichi Kondo
洋一 近藤
Kimio Katayama
片山 乾雄
Hirohisa Tanaka
田仲 広久
Hiroshi Morimoto
弘 森本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP63121557A priority Critical patent/JPH01291217A/en
Publication of JPH01291217A publication Critical patent/JPH01291217A/en
Pending legal-status Critical Current

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Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136259Repairing; Defects
    • G02F1/136263Line defects

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Liquid Crystal (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)

Abstract

PURPOSE:To suppress the generation of wire-shaped defects, etc., at the time of active matrix display by providing bypass lines which are electrically connected at both ends to at least either wiring of respective scanning lines and data lines and intersect with the other wiring in an insulated state. CONSTITUTION:The respective ends of the bypass lines 51 are connected to the respective scanning lines 50 in such a manner as to intersect in the insulated state with the respective data lines 40 intersecting with the scanning lines 50. In addition, the bypass lines 41 are wired between the intersected parts of the respective data lines 40 and the scanning lines 50 to the data lines 40. Both ends of the bypass lines 41 are electrically connected to the data lines 40 between the intersected parts of the data lines 40 and the scanning lines 50 and are constituted of ITO films. Then, even if a disconnection arises between the intersected parts of at least either of the data lines and the scanning lines, said wiring is electrically connected by the bypass lines and, therefore, the generation of the wire-shaped defect is suppressed.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、多数の薄膜トランジスタ(Thin Fil
mTransistor)が絶縁性基板上にマ) IJ
クス状に形成され、液晶等と組み合わせて、アクティブ
マトリクス表示等を構成するアクティブマトリクス基板
に関する。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention is directed to a large number of thin film transistors (Thin Film Transistors).
mTransistor) is mounted on an insulating substrate.
The present invention relates to an active matrix substrate that is formed into a box shape and is used in combination with a liquid crystal or the like to form an active matrix display or the like.

(従来の技術) 近時、液晶等を用いた大容量表示装置に、多数の薄膜ト
ランジスタ(以下TPTと略称する)を用いたアクティ
ブマトリクス基板が使用されている。該アクティブマト
リクス基板は、第7図に示すように、液晶表示セルを構
成する絶縁性基板に。
(Prior Art) Recently, active matrix substrates using a large number of thin film transistors (hereinafter abbreviated as TPT) have been used in large-capacity display devices using liquid crystals or the like. The active matrix substrate is an insulating substrate constituting a liquid crystal display cell, as shown in FIG.

多数の絵素電極81.81.・・・がマトリクス状に配
設されており、また、各絵素電極81に隣接して多数の
T F Te3.82.・・・が、マトリクス状に配設
されている。各TFT82のドレイン電極は各絵素電極
 □81に電気的に接続されており、各TFT82は各
絵素電極81のスイッチング素子として機能する。
A large number of picture element electrodes 81.81. ... are arranged in a matrix, and a large number of T F Te3.82 . ...are arranged in a matrix. The drain electrode of each TFT 82 is electrically connected to each picture element electrode □81, and each TFT 82 functions as a switching element for each picture element electrode 81.

絶縁性基板上には、一方向に列をなす各TFT82のゲ
ート電極に電気的に接続されるように、複数の走査線8
3.83.・・・が平行に配線されている。
A plurality of scanning lines 8 are provided on the insulating substrate so as to be electrically connected to the gate electrodes of the TFTs 82 arranged in one direction.
3.83. ... are wired in parallel.

また、絶縁性基板上には、各走査線83とは絶縁状態で
直交するように、複数のデータ線84.84.・・・が
平行に配線されている。各データ線84は、各データ線
84方向に列をなす各TFT82のソース電極に電気的
に接続されている。
Further, on the insulating substrate, a plurality of data lines 84, 84 . . . 84 . ... are wired in parallel. Each data line 84 is electrically connected to the source electrode of each TFT 82 arranged in a column in the direction of each data line 84 .

このようなアクティブマトリクス基板は2例えば液晶層
が積層されて、液晶表示装置として使用される。この場
合、該アクティブマトリクス基板の各TPTは線順次方
式にて駆動され、各走査線83には走査信号が入力され
ると共に、各データ線84にはデータ信号が入力される
。そして、走査信号とデータ信号の両者が入力されたT
FT82が動作して該TFT82に接続された絵素電極
81に電圧が印加される。これにより、液晶層における
該絵素電極81に対向する部分が電気光学的に動作して
一所定のマトリクス表示が得られる。
Such an active matrix substrate is used as a liquid crystal display device by laminating two, for example, liquid crystal layers. In this case, each TPT of the active matrix substrate is driven in a line sequential manner, and each scanning line 83 receives a scanning signal, and each data line 84 receives a data signal. Then, T to which both the scanning signal and the data signal are input.
The FT 82 operates and a voltage is applied to the picture element electrode 81 connected to the TFT 82 . As a result, the portion of the liquid crystal layer facing the picture element electrode 81 operates electro-optically to obtain a predetermined matrix display.

(発明が解決しようとする課題) このようなアクティブマトリクス基板では2通常、走査
線83およびデータ線84は、絶縁性基板上 □に積層
された導電性金属膜にて構成される。そして、走査線8
3とデータ線84との各交点に対応して配設された各T
FT82は、前述のように線順次方式で駆動されるため
、各走査線83と各データ線84とのリークを防止する
ために、相互に絶縁状態とされている。
(Problems to be Solved by the Invention) In such an active matrix substrate, the scanning line 83 and the data line 84 are usually formed of a conductive metal film laminated on an insulating substrate. And scan line 8
3 and the data line 84.
Since the FT 82 is driven in a line sequential manner as described above, each scanning line 83 and each data line 84 are insulated from each other in order to prevent leakage.

走査線83およびデータ線84は2通常、絶縁性基板上
に積層された導電性金属膜により構成されている。この
ため、走査線83およびデータ線84は。
The scanning line 83 and the data line 84 are usually composed of conductive metal films laminated on an insulating substrate. Therefore, the scanning line 83 and the data line 84.

絶縁性基板から剥離しやす(、走査線83およびデータ
線84が断線するおそれがある。
It is easy to peel off from the insulating substrate (and the scanning line 83 and data line 84 may be disconnected).

また、走査線83とデータ線84との交差部において2
両者がショートすることを防止するために。
Furthermore, at the intersection of the scanning line 83 and the data line 84, two
To prevent both from shorting out.

各交差部には、アモルファスシリコン(以下a−3iと
略称する)半導体膜と保護絶縁膜を介在させて、走査線
83とデータ線84との間を確実に絶縁している。a−
3t半導体膜および保護絶縁膜は。
At each intersection, an amorphous silicon (hereinafter abbreviated as a-3i) semiconductor film and a protective insulating film are interposed to reliably insulate the scanning line 83 and data line 84. a-
3t semiconductor film and protective insulating film.

絶縁性基板上に形成された金属膜製のデータ線84にお
ける走査線83との交差部上に順次積層され。
They are sequentially laminated on the intersections with the scanning lines 83 in the data lines 84 made of metal film formed on the insulating substrate.

その保護絶縁膜上に例えば金属膜製の走査線83が積層
されている。従って、走査線83は、データ線84との
交差部がa−8i膜および保護絶縁膜の膜厚骨だけ盛り
上がった状態となり、この交差部を除いた部分とは段差
が形成される。そして、この段差部にて走査線83を構
成する導電性金属膜が剥がれて断線するおそれがある。
A scanning line 83 made of, for example, a metal film is laminated on the protective insulating film. Therefore, the scanning line 83 is raised at the intersection with the data line 84 by the thickness of the a-8i film and the protective insulating film, and a step is formed from the part other than the intersection. Then, there is a risk that the conductive metal film constituting the scanning line 83 may peel off at this stepped portion, resulting in disconnection.

このような断線を防止するために、絶縁性基板上に走査
線83やデータ線84を構成する金属膜、およびa−3
t膜、保護絶縁膜を形成する際に9種々の工夫がなされ
ている。しかし、走査線83およびデータ線84の断線
を完全に防止することができない。そして、このような
断線は、アクティブマトリクス表示の際に表示部に線状
欠陥として表れ。
In order to prevent such disconnection, the metal film constituting the scanning line 83 and the data line 84 and the a-3
Nine different approaches have been taken when forming the t film and the protective insulating film. However, disconnection of the scanning line 83 and data line 84 cannot be completely prevented. Such a disconnection appears as a linear defect on the display section during active matrix display.

表示性能を著しく低下させる。このような断線を有する
アクティブマトリクス基板は、アクティブマトリクス表
示に使用できず、該アクティブマトリクス基板の歩留り
が著しく低下する。
Significantly reduces display performance. An active matrix substrate having such a disconnection cannot be used for active matrix display, and the yield of the active matrix substrate is significantly reduced.

本発明は、上記従来の問題を解決するものであり、その
目的は、アクティブマトリクス表示する際に、線状欠陥
等の発生を極力抑制することができ、従って、アクティ
ブマトリクス表示の性能に優れたアクティブマトリクス
基板を提供することにある。
The present invention is intended to solve the above-mentioned conventional problems, and its purpose is to suppress the occurrence of linear defects as much as possible during active matrix display, and therefore to improve the performance of active matrix display. The purpose of the present invention is to provide an active matrix substrate.

(課題を解決するための手段) 本発明のアクティブマトリクス基板は、絶縁性基板上に
マトリクス状に配設された複数の絵素電極と、各絵素電
極の配設方向の一方に平行するように配線された複数の
走査線と5各走査線とは直交するように配線され、各走
査線とは絶縁状態で交差する複数のデータ線と、前記絵
素電極にそれぞれのドレイン電極が電気的に接続される
ようにマトリクス状に配設されており、それぞれのソー
ス電極が走査線に接続されると共に、それぞれのゲート
電極がデータ線に接続された複数の薄膜l・ランジスタ
と、前記各走査線、各データ線のいずれか一方の配線と
両端が電気的に接続され、他方の配線とは絶縁状態で交
差するバイパス線と、を具備してなり、そのことにより
上記目的が達成される。
(Means for Solving the Problems) The active matrix substrate of the present invention has a plurality of picture element electrodes arranged in a matrix on an insulating substrate, and a plurality of picture element electrodes arranged in parallel to one direction in which each picture element electrode is disposed. A plurality of data lines are wired to intersect perpendicularly to each of the five scan lines, and a plurality of data lines intersect with each other while being insulated from each scan line, and each drain electrode is electrically connected to the pixel electrode. A plurality of thin film transistors are arranged in a matrix so as to be connected to the scanning lines, each of which has its source electrode connected to a scanning line, and whose gate electrode is connected to a data line. The data lines are electrically connected at both ends to one of the data lines, and a bypass line intersects with the other data line in an insulated state, thereby achieving the above object.

また2本発明のアクティブマトリクス基板は。In addition, there are two active matrix substrates of the present invention.

絶縁性基板上にマトリクス状に配設された複数の絵素電
極と、各絵素電極の配設方向の一方に平行するように配
線された複数の走査線と、各走査線とは直交するように
配線され、各走査線とは絶縁状態で交差する複数のデー
タ線と、前記絵素電極にそれぞれのドレイン電極が電気
的に接続されるようにマトリクス状に配設されており、
それぞれのソース電極が走査線に接続されると共に、そ
れぞれのゲート電極がデータ線に接続された複数の薄膜
トランジスタと、前記各走査線および各データ線の交差
部の間において、いずれか一方の配線に4両端部が電気
的に接線されたバイパス線と。
A plurality of pixel electrodes are arranged in a matrix on an insulating substrate, a plurality of scanning lines are wired parallel to one direction in which each pixel electrode is arranged, and each scanning line is orthogonal to each other. A plurality of data lines intersect with each other while being insulated from each scanning line, and each drain electrode is arranged in a matrix so that each drain electrode is electrically connected to the picture element electrode.
A plurality of thin film transistors each having a source electrode connected to a scanning line and a respective gate electrode connected to a data line, and an intersection of each scanning line and each data line, to one of the wirings. 4. A bypass line with both ends electrically connected.

を具備してなり1そのことにより上記目的が達成される
1. Thereby, the above object is achieved.

(実施例) 以下に本発明を実施例について説明する。(Example) The present invention will be described below with reference to Examples.

本発明のアクティブマトリクス基板は、第1図および第
2関に示すように、透明な絶縁性のガラス基板10上に
1例えばI T O(Indium−Tin−Oxid
e)膜で形成された矩形状の多数の絵素電極30が、マ
トリクス状に配設されており、各絵素電極30の一部は
、各絵素電極の隅部近傍に配設された薄膜トランジスタ
(TPT)20のドレイン電極21を構成している。
The active matrix substrate of the present invention, as shown in FIGS.
e) A large number of rectangular picture element electrodes 30 formed of a film are arranged in a matrix, and a part of each picture element electrode 30 is arranged near the corner of each picture element electrode. It constitutes the drain electrode 21 of the thin film transistor (TPT) 20.

各TPT20は、ガラス基板10上に、各絵素電極30
のドレイン電極21を構成する部分に若干の間隙をあけ
て配設された例えばITO1lW製のソース電極22を
有する。該ソース電極22は後述のデータ線40の一部
を構成する。該ソース電極22上およびドレイン電極2
1上には、n+型のアモルファスシリコン膜(以下、a
−3i(n”)膜と略称する)23が積層されており、
該a−3i  (rr’ )膜23上。
Each TPT 20 has each picture element electrode 30 on the glass substrate 10.
A source electrode 22 made of, for example, ITO11W is disposed with a slight gap between the portion constituting the drain electrode 21. The source electrode 22 constitutes a part of a data line 40, which will be described later. on the source electrode 22 and the drain electrode 2
1, an n+ type amorphous silicon film (hereinafter referred to as a
-3i(n”) film) 23 are stacked,
on the a-3i (rr') film 23.

およびソース電極22とドレイン電極21との間のガラ
ス基板10上に真性アモルファスシリコン膜(以下、a
−3i(i)膜と略称する)24が、断面凹状に積層さ
れている。
And an intrinsic amorphous silicon film (hereinafter referred to as a
-3i (abbreviated as i) film) 24 are laminated with a concave cross section.

該a−3i  (i)膜24上には2例えば窒化シリコ
ン(Si’Nx)にて構成されたゲート絶縁膜25が積
層されている。該ゲート絶縁膜25上面には。
A gate insulating film 25 made of silicon nitride (Si'Nx), for example, is laminated on the a-3i (i) film 24. On the upper surface of the gate insulating film 25.

断面V字状の凹溝が形成されている。そして、該ゲート
絶縁膜25上にゲートメタルであるTi膜にて構成され
たゲート電極26が積層されて、TPT20が構成され
ている。
A groove having a V-shaped cross section is formed. A gate electrode 26 made of a Ti film, which is a gate metal, is laminated on the gate insulating film 25 to form the TPT 20.

各TPT20におけるITO膜のソース電極22は。The source electrode 22 of the ITO film in each TPT 20 is as follows.

ガラス基板10上に適当な間隔をあけて相互に平行に配
線されたITO膜でなる複数のデータ線40゜40、・
・・の1本にそれぞれ一体となっている。絶縁性基板1
0上には7各データ線40とはそれぞれ直交して格子状
となるように複数の走査線50が平行に配線されている
。各走査線50は、各TPT20のゲート電極26と同
様に、Ti膜にて形成されており。
A plurality of data lines 40, 40, made of ITO film are wired in parallel to each other at appropriate intervals on the glass substrate 10.
They are each integrated into one book. Insulating substrate 1
0, a plurality of scanning lines 50 are wired in parallel so as to be orthogonal to each of the seven data lines 40, forming a grid pattern. Each scanning line 50 is formed of a Ti film similarly to the gate electrode 26 of each TPT 20.

1木の走査線50は、その配線方向に並設された各TP
T20のゲート電極26にそれぞれ一体となっている。
One tree of scanning lines 50 connects each TP arranged in parallel in the wiring direction.
They are each integrated with the gate electrode 26 of T20.

各走査線50とデータ線40とのそれぞれの交差部には
、第3図に示すように、それぞれが相互に絶縁状態とな
るように、a−3t(n”″)膜61.a−3i  (
i)膜62およびSiNxの保護絶縁膜63が、データ
線40上に順次積層された状態で、介在されている。
At each intersection of each scanning line 50 and data line 40, an a-3t(n"") film 61. a-3i (
i) A film 62 and a protective insulating film 63 of SiNx are interposed in a state in which they are sequentially laminated on the data line 40.

各走査線50には、該走査線50と交差する各データ線
40とは絶縁状態で交差するように、バイパス線51の
各端部が接続されている。該バイパス線51とデータ線
40との交差部には、第3図に示す各走査線50とデー
タ線との交差部と同様に、a−3i(n゛)膜61. 
 a−31(i)膜62.およびSiNxの保護絶縁膜
63が、データ線40上に順次積層された状態で、介在
されている。
Each end of a bypass line 51 is connected to each scanning line 50 so as to intersect with each data line 40 intersecting with the scanning line 50 in an insulated state. At the intersection between the bypass line 51 and the data line 40, an a-3i(n) film 61.
a-31(i) Membrane 62. and a protective insulating film 63 of SiNx are interposed in a state in which they are sequentially laminated on the data line 40.

このような構成のアクティブマトリクス基板は。An active matrix substrate with such a configuration.

次のように製造される。透明な絶縁性ガラス基板10上
に、 1000人の膜厚のITO膜をスパッタリングに
より形成する。次いで、該ITO膜上にプラズマCVD
法により450人の膜厚のa−3t(n”)を積層した
後に、これら2層を第4図に実線で示すように、絵素電
極30.データ線40.およびTFT20のソース電極
22とドレイン電極21に相当する形状にホトリソグラ
フィ法によりパターニングする。
Manufactured as follows. An ITO film having a thickness of 1,000 wafers is formed on a transparent insulating glass substrate 10 by sputtering. Next, plasma CVD was performed on the ITO film.
After laminating a-3t(n'') with a thickness of 450 mm using the method, these two layers are connected to the picture element electrode 30, the data line 40, and the source electrode 22 of the TFT 20, as shown by solid lines in FIG. It is patterned into a shape corresponding to the drain electrode 21 by photolithography.

このような状態で、プラズマCVD法により300人の
膜厚のa−3i  (n’ ) 、 4800人の膜厚
のSiNx膜を、ガラス基板10全面上に連続的に形成
した後に、第4図に二点鎖線で示すように、TPT20
に相当する部分およびデータ線40の走査線5011 
In this state, a SiNx film having a thickness of 300 mm and a SiNx film having a thickness of 4800 mm was continuously formed on the entire surface of the glass substrate 10 by the plasma CVD method. As shown by the two-dot chain line, TPT20
and the scanning line 5011 of the data line 40
.

との交差部に相当する部分が残るように、5iNX膜、
a−3t(i)膜およびa−5t(n”)膜をエツチン
グする。その後、ガラス基板10の全面にゲートメタル
であるTi膜を3000人の膜厚で形成し、該ゲートメ
タルであるTi膜を、第4回に破線で示すように、TP
T20におけるゲート電極26および走査線50に相当
する形状にパターニングする。これにより、前述した構
成を有する本発明のアクティブマトリクス基板が製造さ
れる。
5iNX film, so that a portion corresponding to the intersection with
The a-3t(i) film and the a-5t(n") film are etched. Thereafter, a Ti film serving as a gate metal is formed on the entire surface of the glass substrate 10 to a thickness of 3000 nm. The membrane was prepared by TP as indicated by the dashed line in
Patterning is performed in a shape corresponding to the gate electrode 26 and scanning line 50 at T20. As a result, the active matrix substrate of the present invention having the above-described configuration is manufactured.

このような本発明のアクティブマトリクス基板は1例え
ば、液晶層が積層されて、液晶表示装置として使用され
る。該アクティブマトリクス基板の各TPT20は、線
順次駆動方式にて駆動され。
Such an active matrix substrate of the present invention is used as a liquid crystal display device, for example, by stacking liquid crystal layers. Each TPT 20 of the active matrix substrate is driven by a line sequential driving method.

各走査線50から入力される走査信号および各データ線
40から入力されるデータ信号にて各TPT20が動作
し、該TPT20に接続された絵素電極30に電力が印
加される。これにより、該絵素電極3oに対向する液晶
層部分が電気光学的に動作して、所定のマトリクス表示
が得られる。
Each TPT 20 is operated by a scan signal input from each scan line 50 and a data signal input from each data line 40, and power is applied to the picture element electrode 30 connected to the TPT 20. As a result, the portion of the liquid crystal layer facing the picture element electrode 3o operates electro-optically to obtain a predetermined matrix display.

第5図は本発明の他の例を示す要部断面図である。各デ
ータ線40には、各データ線40と各走査線50との交
差部の間において、バイパス線41が配線されている。
FIG. 5 is a sectional view of a main part showing another example of the present invention. A bypass line 41 is wired to each data line 40 between the intersections of each data line 40 and each scanning line 50 .

該バイパス線41は1両端部が各データ線40と各走査
線50との交差部間において各データ線40と電気的に
接続されている。該バイパス線41は、各データ線40
と同様にITO膜で構成されている。
Both ends of the bypass line 41 are electrically connected to each data line 40 between the intersections of each data line 40 and each scanning line 50 . The bypass line 41 connects each data line 40
Similarly, it is made of ITO film.

該バイパス線41は、第6図に示すように、絶縁性ガラ
ス基板上にITO膜およびa−3i膜を積層した後に、
絵素電極30.データ線40. TFT20のソース電
極22とドレイン電極21をホトリソグラフィ法により
パターニングする際に、パターニングされて形成される
。他の構成は、第1図に示すアクティブマトリクス基板
と同様である。
As shown in FIG. 6, the bypass line 41 is formed by laminating an ITO film and an a-3i film on an insulating glass substrate.
Picture element electrode 30. Data line 40. They are formed by patterning when patterning the source electrode 22 and drain electrode 21 of the TFT 20 by photolithography. The other configurations are similar to the active matrix substrate shown in FIG.

(発明の効果) 本発明のアクティブマトリクス基板は、このように、相
互に直交するように配線されたデータ線と走査線が、そ
れぞれの交差部以外に、いずれか一方の配線とは電気的
に接線されたバイパス線が他方の配線と交差しているた
め、データ線と走査線との交差部において、いずれかの
配線を構成する金属膜が剥がれて断線しても、その配線
はバイパス線により電気的に接続されている。また、デ
ータ線と走査線のいずれか一方の配線に各端部が電気的
に接続されたバイパス線が、各データ線と走査線との交
差部間に配線されているため、データ線と走査線のいず
れか一方の配線の交差部間での断線が生じてもその配線
はバイパス線により電気的に接続されている。従って9
本発明のアクティブマトリクス基板によりアクティブマ
トリクス表示する際に、線状欠陥の発生を極力抑制する
ことができ、該アクティブマトリクス基板の歩留りは著
しく向上する。
(Effects of the Invention) In the active matrix substrate of the present invention, the data lines and scanning lines wired perpendicularly to each other are electrically connected to one of the wires other than at their intersections. Since the tangential bypass line intersects with the other wiring, even if the metal film that makes up one of the wirings peels off and breaks at the intersection of the data line and the scanning line, that wiring will still be connected to the bypass line. electrically connected. In addition, a bypass line, each end of which is electrically connected to either the data line or the scanning line, is wired between the intersections of each data line and the scanning line. Even if a disconnection occurs between the intersections of either one of the lines, that line is electrically connected by the bypass line. Therefore 9
When performing active matrix display using the active matrix substrate of the present invention, the generation of linear defects can be suppressed as much as possible, and the yield of the active matrix substrate is significantly improved.

4、゛ の  なう日 第1図は本発明のアクティブマトリクス基板の要部平面
図、第2図は第1図の■−■線における断面図、第3図
は第1図の■−■における断面図。
4. Next Day Figure 1 is a plan view of the main part of the active matrix substrate of the present invention, Figure 2 is a sectional view taken along the line ■-■ in Figure 1, and Figure 3 is a cross-sectional view taken along the line ■-■ in Figure 1. A cross-sectional view.

第4図は本発明のアクティブマトリクス基板の製造工程
を説明するための要部平面図、第5図は本発明の他の例
のアクティブマトリクス基板の要部平面図、第6図はそ
の製造工程を説明するための要部平面図、第7図は従来
のアクティブマトリクス基板を模式的に示す平面図であ
る。
FIG. 4 is a plan view of the main parts for explaining the manufacturing process of the active matrix substrate of the present invention, FIG. 5 is a plan view of the main parts of an active matrix substrate of another example of the invention, and FIG. 6 is the manufacturing process thereof. FIG. 7 is a plan view schematically showing a conventional active matrix substrate.

10・・・ガラス基板、20・・・TPT、21・・・
ドレイン電極、 22・・・ソース電極、 23.61
・・・a−3i (n” )膜、 24.62−a−3
i  (+ )膜、 25−・・ゲート絶縁膜、26・
・・ゲート電極、30・・・絵素電極、40・・・デー
タ線、41・・・バイパス線、50・・・走査線、51
・・・バイパス線、63・・・保護絶縁膜。
10...Glass substrate, 20...TPT, 21...
Drain electrode, 22... Source electrode, 23.61
...a-3i (n”) film, 24.62-a-3
i (+) film, 25-... gate insulating film, 26-
... Gate electrode, 30 ... Picture element electrode, 40 ... Data line, 41 ... Bypass line, 50 ... Scanning line, 51
... Bypass line, 63... Protective insulating film.

以上that's all

Claims (1)

【特許請求の範囲】 1、絶縁性基板上にマトリクス状に配設された複数の絵
素電極と、 各絵素電極の配設方向の一方に平行するように配線され
た複数の走査線と、 各走査線とは直交するように配線され、各走査線とは絶
縁状態で交差する複数のデータ線と、前記絵素電極にそ
れぞれのドレイン電極が電気的に接続されるようにマト
リクス状に配設されており、それぞれのソース電極が走
査線に接続されると共に、それぞれのゲート電極がデー
タ線に接続された複数の薄膜トランジスタと、 前記各走査線、各データ線のいずれか一方の配線と両端
が電気的に接続され、他方の配線とは絶縁状態で交差す
るバイパス線と、 を具備することを特徴とするアクティブマトリクス基板
。 2、絶縁性基板上にマトリクス状に配設された複数の絵
素電極と、 各絵素電極の配設方向の一方に平行するように配線され
た複数の走査線と、 各走査線とは直交するように配線され、各走査線とは絶
縁状態で交差する複数のデータ線と、前記絵素電極にそ
れぞれのドレイン電極が電気的に接続されるようにマト
リクス状に配設されており、それぞれのソース電極が走
査線に接続されると共に、それぞれのゲート電極がデー
タ線に接続された複数の薄膜トランジスタと、 前記各走査線および各データ線の交差部の間において、
いずれか一方の配線に、両端部が電気的に接線されたバ
イパス線と、 を具備することを特徴とするアクティブマトリクス基板
[Claims] 1. A plurality of picture element electrodes arranged in a matrix on an insulating substrate, and a plurality of scanning lines wired parallel to one of the arrangement directions of each picture element electrode. , a plurality of data lines that are wired perpendicularly to each scanning line and intersect with each other while being insulated from each scanning line, and arranged in a matrix so that each drain electrode is electrically connected to the picture element electrode. a plurality of thin film transistors each having a source electrode connected to a scanning line and a respective gate electrode connected to a data line; and wiring for one of the scanning lines and data lines; An active matrix board comprising: a bypass line that is electrically connected at both ends and intersects with the other wiring in an insulated state. 2. A plurality of picture element electrodes arranged in a matrix on an insulating substrate, a plurality of scanning lines wired parallel to one of the arrangement directions of each picture element electrode, and what each scanning line is. A plurality of data lines are wired orthogonally and intersect with each other while being insulated from each scanning line, and each data line is arranged in a matrix so that each drain electrode is electrically connected to the picture element electrode, a plurality of thin film transistors each having a source electrode connected to a scanning line and each gate electrode connected to a data line, and between an intersection of each scanning line and each data line,
An active matrix board comprising: a bypass line having both ends electrically tangential to one of the wirings;
JP63121557A 1988-05-18 1988-05-18 Active matrix substrate Pending JPH01291217A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63121557A JPH01291217A (en) 1988-05-18 1988-05-18 Active matrix substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63121557A JPH01291217A (en) 1988-05-18 1988-05-18 Active matrix substrate

Publications (1)

Publication Number Publication Date
JPH01291217A true JPH01291217A (en) 1989-11-22

Family

ID=14814187

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63121557A Pending JPH01291217A (en) 1988-05-18 1988-05-18 Active matrix substrate

Country Status (1)

Country Link
JP (1) JPH01291217A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0572553A (en) * 1991-09-11 1993-03-26 Hitachi Ltd Liquid crystal display device and production thereof
EP0766118A2 (en) * 1995-09-28 1997-04-02 Sharp Kabushiki Kaisha Active-matrix type liquid crystal display device and method of compensating for defective pixel

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61181B2 (en) * 1980-06-17 1986-01-07 Sekisui Plastics
JPS61249078A (en) * 1985-04-27 1986-11-06 シャープ株式会社 Matrix type display unit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61181B2 (en) * 1980-06-17 1986-01-07 Sekisui Plastics
JPS61249078A (en) * 1985-04-27 1986-11-06 シャープ株式会社 Matrix type display unit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0572553A (en) * 1991-09-11 1993-03-26 Hitachi Ltd Liquid crystal display device and production thereof
EP0766118A2 (en) * 1995-09-28 1997-04-02 Sharp Kabushiki Kaisha Active-matrix type liquid crystal display device and method of compensating for defective pixel
EP0766118A3 (en) * 1995-09-28 1998-07-08 Sharp Kabushiki Kaisha Active-matrix type liquid crystal display device and method of compensating for defective pixel
US6175393B1 (en) 1995-09-28 2001-01-16 Sharp Kabushiki Kaisha Active-matrix type liquid crystal display device and method of compensating for defective pixel

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