JPH01277781A - Testing apparatus for integrated circuit - Google Patents

Abstract

PURPOSE:To give guidelines regarding a fault tracing direction, by a method wherein the theoretical depth and the direction of signal propagation of a designed wiring pattern corresponding to a pattern appearing in an image of a difference between an article to be tested and a good article are given to the designed wiring pattern and displayed. CONSTITUTION:An observation image of a sample of an integrated circuit 3 to be tested, which is obtained from an electron beam test apparatus 1, and a normal operation state image for reference which is stored beforehand in a memory circuit 5 for an image for reference are subjected to a difference processing in a fault image forming circuit 6, and a fault image is formed and displayed in a fault image display element 7. A fault search map is prepared and displayed in the following procedure. First a fault pattern discriminating circuit 70 discriminates the length of the fault pattern, the coordinates of end points thereof, etc., on an observed fault image, as form parameters. Based on the fault pattern, the result of recognition by a design wiring recognizing element 80 is stored in a memory 2. A logical depth recognizing circuit 10 reads the logical depth of a circuit network and the terminal position of a logic cell and stores them in a memory 3. The data in the memories are displayed by a display element 12.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electron beam testing device that performs fault diagnosis of integrated circuits at high speed and in detail.

[Conventional technology]

One of the methods for testing integrated circuits using electron beam testing equipment is a method that uses failure images. The failure image is an image obtained as a result of the difference between image data obtained from an integrated circuit sample under test by an electron beam tester and separately prepared image data known to be normal. Since the state of the failure can be observed at a glance on this image, the location of the failure can be conveniently and easily identified by tracking changes in the state over time.

These test methods are broadly divided into dynamic fault images (DFI: for example, T, C, May et al.
al,,”Dynamic Fault Imagi
ng of VLSI Random Logic D
ecices', 19841EEE/TRPS pp,
95-10 Ft) and a method using fault contrast images (FCl e.g. 8 fan R, 5 tivers
at al,,”Fault C.

ntrast: ＾New Voltage Contr
, ast Vl, Sr Diagnosis Techn.
ique', 1986 rEEE#RPs pp, 10
There are two methods using 9-114), the outline of which is shown in Figure 5(a).

Shown in (b). FIG. 5(a) shows the generation of a dynamic fault image, and FIG. 5(b) shows the generation of a fault contrast image. In the former method, two devices are prepared: an integrated circuit under test 51 as a device under test and a non-defective integrated circuit 52 as a non-defective device, image data is captured from both under the same operating conditions, and the difference is taken to detect a failure. An image is obtained. 53 is the same test parameter, 54 and 55 are observation images, 56 is a differential circuit, 57 is a dynamic fault image, and 58 is a fault cube.

On the other hand, the latter is applied to devices that are confirmed to operate normally under specific test parameter conditions; Observation images 514 and 515 are obtained with test parameter 1 and the other with test parameter 2 of 513 under conditions that do not operate normally, and a difference is taken by a difference circuit 516 to obtain a fault contrast image 517 as a failure image. Although this method is limited to failure modes of margin nature, it has the advantage that alignment of images and distortion correction are not required when performing image difference processing.

As a fault tracing method using DPI, there is a method using a fault cube 58 as shown in FIG. 5(a). A fault cube is a three-dimensional display of failure images lined up in the time direction, and the location of the failure can be identified by visually observing how the failure pattern expands over time and finding its starting point.

Figure 6(a) shows the fault tracing method in the case of FCT.

Shown in (b). 60 is an integrated circuit chip, and when a failure is detected through the output pad 61, the timing (t=
n), the failure pattern 63 on the integrated circuit sample is traced while moving through the observation zone 62 of the failure image (Fig. 6(a)
)). When the starting point of fault pattern propagation is reached, the test break is stopped at the previous test pattern timing (t=
n-1), manually trace the sample again to find the origin of fault propagation (Fig. 6(b)). In this way, when the timing at which the failure pattern no longer occurs is reached, the starting point of the failure reached last is determined to be the true failure part. Even in the case of DFT, this method is often adopted in the end. This is because the spread of failure patterns is not necessarily immediately obvious.
There is no guarantee that the light will diffuse neatly from the point, and it depends on the timing at which the image data is taken, but it is rather common for the change to occur in a way that is not obvious from the point of occurrence.

[Problem to be solved by the invention]

In the tracking method shown in FIG. 6, it is necessary to capture an image with such precision that the wiring pattern can be recognized, so it is difficult to make the observation zone large enough to cover the entire integrated circuit sample due to the limited number of pixels. Therefore, a fault image is captured in a local zone of, for example, 1 mm x 1 mm, and the fault pattern is tracked. It becomes necessary to check the general order.However, conventional methods merely provide a means of observing failure images, and all the work required for tracking them must be done manually. Specific tasks include correspondence between faulty wiring patterns and designed wiring patterns, correspondence between wiring patterns and circuit diagrams, and tracing of circuit diagram structures, but in addition to design knowledge, these tasks require This method requires a huge amount of time and effort, such as tracking a huge mask pattern diagram and comparing it with observed images, which is a major factor that makes it difficult to apply this method to large-scale integrated circuits.

It has been pointed out that in order to solve such problems, it is necessary to utilize design data in some way. However, in conventional design data, there is no link between the wiring pattern and the circuit diagram to refer to each other, so it is not possible to create a map for tracking, which makes tracking easier. was impossible.

The present invention aims to solve the problem that conventional test equipment does not have a means for providing guidelines regarding the direction of fault tracing, and its purpose is to speed up fault tracing and improve efficiency.

[Means for explaining the issue]

In order to achieve the above object, the integrated circuit testing apparatus of the present invention scans a certain area on an integrated circuit sample placed in an operating state with an electron beam, and images secondary electron images at one or more timings. In the integrated circuit testing apparatus, a failure is recognized by obtaining a difference image between the taken-out secondary electron image and an image obtained from a non-defective sample or the same sample under normal operating conditions or design data. means for recognizing a designed wiring pattern that opposes the pattern appearing in the difference image; means for recognizing the logical depth of the recognized designed wiring pattern; and a starting point of signal propagation of the recognized designed wiring pattern. The integrated circuit testing apparatus is characterized by comprising: means for recognizing the logical depth and the direction of signal propagation; and means for assigning and displaying the logical depth and the direction of signal propagation to the designed wiring pattern.

[For production]

Unlike conventional devices that simply observe and display failure images (Dll and FC■), the device according to the present invention can also display information that can be used as clues for determining the direction of tracking in accordance with the failure image. Because it is characterized by
In the device according to the present invention, the most efficient fault tracing procedure can be determined while always referring to a search map in the form of logic depth and signal propagation direction. Examples will be described below based on the drawings.

〔Example〕

FIG. 1 shows an embodiment of the present invention. Electron beam test device 1
An integrated circuit under test 3 is placed on the XY stage 2 of the device. An electron beam 4 is irradiated onto this surface, and a secondary electron signal generated from the surface is extracted in the form of an image. The observation zone is moved by moving the XY stage 2 indicating stage position information 2XY. The observation image of the sample of the integrated circuit under test 3 obtained from the electron beam tester W1 and the normal operating state image for reference stored in the reference image memory circuit 5 in advance are generated by the failure image generation circuit 6. Three differential processes are performed, and a fault image is generated and displayed on the fault image display section 7.

On the other hand, a corresponding failure search map is generated and displayed using the following procedure.

■) The failure pattern identification circuit 70 detects 4 on the observed failure image.
The length of the failure pattern, the coordinates of the end points, etc. are identified as shape parameters. 52) Circuit data 81 as design data, data 82 as designed wiring pattern, and cross reference 8 showing the correspondence between the two.
3 is stored in the memory circuit 1 of 8. The cross-reference 83 can be easily generated by using a design database that has a mechanism in which there is a link between the circuit diagram and the wiring pattern so that they can refer to each other (for example, uji et al., “FIN
DER: A CAD System-based E
lectron Beam TeeSter for
Fault Diagnosis of VLSI C
1rcuits”, IEEE Trans, C
AD, 8pril 1986. Vol CAD
-5, Number 2. pp-313-319).

) Based on the shape parameters of the failure pattern obtained in step 1), the wiring data of the corresponding design wiring pattern is selectively output from among the 8 memory circuits 1, and the recognition result by the design wiring recognition unit 80 is transferred to the 9 memory circuits. Accumulate in 2.

) The circuit net corresponding to this wiring is found by referring to the cross reference 83.

) The logic depth recognition circuit 10 stores the "logic depth" of the circuit net obtained in 4) and the position of the output terminal of the logic cell with respect to this net in the logic depth output terminal coordinates of the memory circuit 3 of 11. "Logic depth" is the number of stages of circuit nets that are passed through when reaching the circuit net from the -next input terminal of the entire circuit or circuit block, assuming a predetermined star path on the circuit diagram.

6) The logic depth, wiring data, and output terminal coordinates are read out from the memory circuit 2 of 9 and the memory circuit 3 of 11, and the search map is displayed on the search map display section 12.

FIGS. 2(a) to 2(c) show an embodiment in which designed wiring corresponding to a failure pattern is recognized. FIG. 2(a) is an example of a failure image 200, and 20 is an observed failure wiring pattern. The faulty wiring pattern 20 is binarized using an appropriate darkness value, and the position and line length of the end point 21 of the pattern are determined as feature parameters. The corresponding design coordinate position of one point on the wiring is determined by reading the coordinates of the XY stage, a search range is determined around this point, and the wiring pattern contained therein is found. If this search range is greater than the positioning accuracy of the XY stage, the corresponding wiring pattern should be included within this range. Figure 2(b)
is the corresponding designed wiring pattern 201 obtained in the wiring pattern search range 22 in this way. Which of these designed wiring patterns 201 corresponds to a failure pattern can be determined based on the feature parameters of the failure pattern.

As a result, the corresponding designed wiring 202 is selected as shown in FIG. 2(c).

Figure 3 (aL (b) shows an example of the search map. Figure 3 (a) shows an example 300 of the logical depth found on the circuit diagram, where the logical depth It is determined in correspondence with the number of stages of the circuit net counted from the input, and is assigned to each circuit node in the form of a number, for example, 31°, 32.33.34.

On the other hand, FIG. 3(b) is a display example 301 of a search map, in which arrows 311 of each wiring are the signal propagation directions of the wiring pattern 312, and numbers 31, 32, 33, and 34 are the circuit nets corresponding to the wiring. It represents the logic depth, and the smaller the number, the closer it is to the true failure point.

313 is a logic cell, and 314 is a signal output starting point.

FIGS. 4(a) and 4(b) show an example of a test procedure performed using the apparatus according to the present invention based on the above search map display. Figure 4(a) shows a circuit diagram of the circuit under test, with numbers 41°, 42.43, 44.4.
5 is the logical depth. Figure 4(b) shows the failure tracing process T.
, II, III, and IV, a search map 400 is shown on the left, and a failure image 401 on the integrated circuit sample is shown on the right. 402 is a failure image observation zone, 403 is a failure pattern, 411 is a signal output terminal, 412 is a designed wiring pattern, 4
13 is an observation zone. While referring to the search map 400 on the left, the search direction for the failure image on the right is determined, and tracking proceeds toward the true failure point. Normally, observations start from the pads connected to external terminals and progress to the internal circuitry.

The timing of the test pattern at which observation started is assumed to be t'=n (process 1). The designed wiring pattern corresponding to the failure pattern on the first failure image is automatically identified by the method shown in FIG. The information necessary for these identifications may be determined and input interactively by a human, or may be automatically extracted using image processing technology. The corresponding wiring identified on the search map includes
The direction of signal propagation indicated by the arrow on the wiring and the number representing the logical depth between the wirings are displayed. From these widths, the one with the smallest number representing the logical depth is selected, the search direction is determined in a direction that traces back the signal propagation direction, and the observation zone 413 is moved. Tracking such a planar failure pattern is
The process ends when nothing with a smaller logical depth appears (process ■). Such tracking can be easily performed if the field size of the observation zone is 1 mm x 1 mm. Next, the timing of the test pattern is set to go back a predetermined number of patterns, timing t=n-1 (process 2), and a failure pattern is searched for in the same manner.

Tracking is performed to find the fault pattern that minimizes the logic depth.
Find the origin of the failure at this timing t=n-1 (
Process ■). Further, the timing of the test pattern is traced back and the same process is repeated, and when the failure pattern no longer appears in the failure image, the search in the timing direction is completed, and the origin of the failure found just before is the true failure occurrence point. It is required as.

As explained above, compared to conventional devices that perform fault tracing by groping, the device according to the present invention constantly searches for a search map in the form of logic depth and signal propagation direction.
One major improvement was being able to determine the most efficient fault tracing procedure.

〔Effect of the invention〕

As explained above, the present invention has the following effects when tracing failure images by providing a means for specifying a search procedure based on design data: 1) mask pattern;
There is no need to manually refer to the circuit diagram and the relationship between the two.
The effort involved in tracking is significantly reduced.

2) Since the tracking procedure is optimized, the number of times image data is processed is minimized, significantly reducing the time required for testing.

3) Since the tracing procedure is clearly specified, the test procedure can be made routine, and even a person without knowledge of the design of the integrated circuit under test can perform the test in a short time.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the device of the present invention, and FIGS. 2(a) to (
C) is a diagram illustrating an example of recognition of a designed wiring pattern corresponding to a failure pattern, and FIG. 3(a). (b) is a diagram illustrating an example of displaying a search map, and FIG.
Figures a) and (b) are diagrams explaining an example of the test procedure in the device of the present invention, Figures 5 (a) and (b) are diagrams explaining the conventional technique, and Figure 6 is a diagram illustrating failures caused by old contrast images. The same describes the tracking method. 1... Electron beam test device, 2... XY stage,
3... Integrated circuit under test, 4... Electron beam, 5...
・Reference image memory circuit, 6... Failure image generation circuit, 7
... Failure image display section, 70 ... Failure pattern identification circuit,
8...Memory circuit 1.81...Design circuit data, 8
2... Design wiring pattern data, 83... Cross reference, 80... Design wiring recognition section, 9... Memory circuit 2.10... Logic depth recognition circuit, 11... Memory circuit 3. 12... Search map display section, 200... Fault image, 201... Design wiring pattern, 202... Selected corresponding designed wiring, 20... Fault wiring pattern, 21
...End point, 22...Wiring pattern search range, 300
...Example of logical depth, 301...Example of display of search map,
31-34.41-45...Logic depth, 311...
Signal propagation direction, 312... Wiring pattern, 313...
Logic cell, 314... Signal output starting point, 400... Search diagram, 401... Fault image on integrated circuit sample, 402...
...Failure image observation zone, 403...Failure pattern, 4
11... Signal output terminal, 412... Design wiring pattern, 413... Observation zone, 5I, 511... Integrated circuit under test, 52... Good integrated circuit, 53... Same test parameters, 54.55...Observation image, 56.51
6... Differential circuit, 57... Dynamic fault image, 58... Fault cube, 512... Test parameter 1.513... Test parameter 2.5
14,515...Observation image, 517...Photocontrast image, 60...Integrated circuit chip, 61...Output pad, 62...Failure image observation zone, 63...Failure pattern patent factory Person Nippon Telegraph and Telephone Corporation Representative Patent Attorney Tama Mushi Kugobe (2 others) JQ'? − --, 1

Claims (1)

[Claims] A fixed area on an integrated circuit sample placed in an operating state is scanned by an electron beam, a secondary electron image is taken out at one or more timings, and the secondary electron image is combined with the taken out secondary electron image. , an integrated circuit testing device that recognizes a failure by obtaining a difference image between a good sample or an image obtained from the same sample or design data under normal operating conditions, and a pattern corresponding to the pattern appearing in the difference image. means for recognizing a designed wiring pattern; means for recognizing a logical depth of the recognized designed wiring pattern; means for recognizing a starting point of signal propagation of the recognized designed wiring pattern; and the logical depth and the signal. An integrated circuit testing device comprising means for assigning and displaying the direction of propagation to the designed layout pattern.