JP4190748B2 - CAD tool for semiconductor failure analysis and semiconductor failure analysis method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention is a luminescence microscope or OBIRCH (Optical Beam Induced Resistance).
The present invention relates to a program such as a CAD tool for estimating a defect position that is a cause of a reaction from a reaction point detected by a physical analysis apparatus such as an analysis apparatus and a defect analysis method using the program.
[0002]
[Prior art]
In recent years, along with demands for high-speed and functional diversification of semiconductor devices, semiconductor elements and wirings have been miniaturized and highly integrated, and it has become difficult to manufacture the semiconductor devices without defects. In order to reduce the defects, it is necessary to perform an improvement work such as identifying a defective part from the highly integrated semiconductor device, estimating a failure mechanism of the semiconductor device, and removing the cause. Among these, in order to specify a defect location, a technique of analyzing a semiconductor device using a light emission microscope or an OBIRCH analysis device has been used.
[0003]
For example, in a light-emitting microscope, a voltage can be applied to a semiconductor device to detect abnormal light emission from a semiconductor element (transistor), and can be used as a clue to identify a defective portion. Here, the method of calculating the coordinates of the abnormal part by superimposing the coordinates of the emission points detected by the light emission microscope with the layout pattern, which is the design data, and reading the coordinates as the coordinates of the layout pattern is used. Analysis time can also be shortened.
[0004]
[Problems to be solved by the invention]
[Problem 1] There are many cases where a light emitting portion is not necessarily a defective portion. For example, when a signal wiring is short-circuited with another wiring, light may be emitted when an abnormal potential is input to a normal transistor. As described above, the position of the light-emitting transistor is not necessarily defective, and it is necessary to perform troublesome work such as sequentially tracking with an electron beam tester after the analysis with the light emission microscope.
[Problem 2] Light emission may occur simultaneously at several locations. Although it is possible to obtain the position information on the layout pattern from the individual light emission positions as described above, the current CAD tool cannot examine the relationship between them.
[Problem 3] In a semiconductor device having a fine wiring pattern, it is difficult to clearly decompose the pattern even with a high magnification microscope. A light-emitting microscope uses an objective lens with a long working distance due to the need to place a probe needle for voltage application between the objective lens and the semiconductor device, and has a low NA (= numerical aperture) and low image resolution. Thus, it has become difficult to specify up to one transistor. Similarly, in the OBIRCH analysis apparatus, it has become difficult to specify a single wiring that has caused an abnormal phenomenon.
[0005]
An object of the present invention is to specify the location of a defect with high accuracy in a short time under such circumstances.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, the present invention has the following features.
[0007]
That is, according to the present invention, when a voltage based on a plurality of types of voltage setting patterns is applied to a semiconductor device, the step of receiving the reaction information for each of the patterns acquired by the physical analysis device; Collating with the layout pattern information of the semiconductor device and extracting each upstream wiring from the transistors existing within the position indicated by the reaction information in the direction of the voltage application position by the processing means. A CAD tool for analyzing a semiconductor defect, characterized in that: a step and a step of identifying and displaying on the display means a wiring range in which the path of the upstream wiring corresponding to each transistor matches or is adjacent to each other It is.
[0008]
According to another aspect of the present invention, when a voltage based on a voltage setting pattern is applied to a semiconductor device, the step of receiving reaction information at a plurality of locations acquired by a physical analysis device; A step of collating with the layout pattern information and identifying each upstream wiring by the arithmetic processing means by going up the wiring path in the direction of the voltage application position from the transistor existing within the range of the position of the reaction information; and each transistor And a step of causing the display means to display a wiring range that matches or is adjacent to the route of the upstream wiring corresponding to the above, and executes the CAD tool for semiconductor defect analysis.
[0009]
Further, according to the present invention, when there are a plurality of transistors within the range of the position indicated by the reaction information, the calculation process is performed on the wiring upstream from the transistor located in the range of high emission intensity within the range. This is a CAD tool for semiconductor defect analysis.
[0010]
Further, the present invention is a CAD tool for analyzing a semiconductor defect, characterized in that a light-emitting microscope is used as the physical analysis device.
[0011]
Further, according to the present invention, when going up the wiring path in the direction of the voltage application position, a failure dictionary in which an intermediate potential propagation phenomenon due to a defect is modeled in advance is selected to select a wiring having a high possibility of failure. This CAD tool for semiconductor failure analysis is characterized by going up.
[0012]
Further, the present invention acquires a reaction state when a voltage based on a plurality of types of voltage setting patterns is applied to a semiconductor device as reaction information for each pattern using a light emission microscope, and each of the reaction information is acquired by the semiconductor. Collating with the layout pattern information of the device, each upstream wiring is extracted by the arithmetic processing means by going up the wiring path in the direction of the voltage application position from the transistor existing within the range of the position indicated by the reaction information, In this semiconductor defect analysis method, a range of wiring that matches or is adjacent to the path of the upstream wiring corresponding to a transistor is specified and displayed on a display means.
[0013]
Further, the present invention obtains reaction information when a voltage based on a voltage setting pattern is applied to a semiconductor device using a light emission microscope, and when there are a plurality of the reaction information, each reaction information is obtained. Collating with the layout pattern information of the semiconductor device, and specifying each upstream wiring by the arithmetic processing means by going up the wiring path from the transistor existing in the range of the position of the reaction information in the voltage application position direction, In the semiconductor defect analysis method, a range of wiring that matches or is adjacent to the path of the upstream wiring corresponding to each transistor is specified and displayed on a display unit.
[0014]
Further, according to the present invention, when there are a plurality of transistors within the range of the position indicated by the reaction information, the calculation process is performed on the wiring upstream from the transistor located in the range of high emission intensity within the range. This is a characteristic semiconductor defect analysis method.
[0015]
Further, according to the present invention, when going up the wiring path in the direction of the voltage application position, a failure dictionary in which an intermediate potential propagation phenomenon due to a defect is modeled in advance is selected to select a wiring having a high possibility of failure. It is a semiconductor failure analysis method characterized by going up.
[0016]
The present invention also includes a step of receiving input of reaction information for each of the patterns acquired by a physical analysis device when voltages based on a plurality of types of voltage setting patterns are applied to a semiconductor device, and each of the reaction information Corresponding to each pattern, a step of forming a template representing a corresponding reaction shape, a step of extracting a wiring path on the layout by an arithmetic processing means by matching the template and the layout pattern information of the semiconductor device, and And a step of displaying the wiring path on a display means. A CAD tool for analyzing a semiconductor defect.
[0017]
The present invention also includes a step of receiving input of reaction information for each of the patterns acquired by a physical analysis device when voltages based on a plurality of types of voltage setting patterns are applied to a semiconductor device, and each of the reaction information Corresponding to each pattern, a step of forming a template representing a corresponding reaction shape, a step of extracting a wiring path on the layout by an arithmetic processing means by matching the template and the layout pattern information of the semiconductor device, and And a step of displaying on the display means a dense distribution based on the degree of wiring density when the extracted wiring paths are superimposed, a CAD tool for semiconductor defect analysis.
[0018]
Further, the present invention provides a CAD for semiconductor defect analysis, characterized in that, when the wiring paths are overlapped, a density distribution as a result of calculation processing is displayed by deleting a portion where wiring paths having the same potential are dense. Is a tool.
[0019]
Further, the present invention is a CAD tool for analyzing a semiconductor defect, characterized in that an OBIRCH analysis device is used as the physical analysis device.
[0020]
Further, the present invention acquires a reaction state when a voltage based on a plurality of types of voltage setting patterns is applied to a semiconductor device as reaction information for each pattern by a physical analysis device, and a reaction corresponding to each of the reaction information A template representative of the shape is formed, and the template and the layout pattern information of the semiconductor device are matched to extract the wiring path on the layout by the arithmetic processing means, and the wiring path corresponding to each pattern is displayed. This is a semiconductor failure analysis method characterized by displaying on
[0021]
Further, the present invention acquires a reaction state when a voltage based on a plurality of types of voltage setting patterns is applied to a semiconductor device as reaction information for each pattern by a physical analysis device, and a reaction corresponding to each of the reaction information A template representing a shape is formed, the template and the layout pattern information of the semiconductor device are matched, and wiring paths on the layout are extracted by arithmetic processing means, and the extracted wiring paths corresponding to each pattern are extracted. In the semiconductor defect analysis method, a dense distribution based on the degree of the wiring density is displayed on the display means when.
[0022]
According to another aspect of the present invention, there is provided a semiconductor failure analysis method, wherein when the wiring paths are overlapped, a density distribution is displayed as a result of performing arithmetic processing by deleting a portion where wiring paths having the same potential are dense. .
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
The CAD apparatus and its system according to the first embodiment of the present invention will be described with reference to FIG. The CAD device 1 includes a data storage unit 10, a data calculation unit 11, and a program storage unit 12. The data storage unit 10 transfers the layout data 8, netlist 9, schematic (not shown), design additional information (technology file, etc., not shown), etc. stored in the design database 7 via the network 15 to a file. Is subjected to a desired pretreatment and stored. On the other hand, a sample 3 to be subjected to failure position identification is mounted on the light emitting microscope 2, and the tester 4 is driven based on a test pattern 5 programmed in advance to apply a desired voltage to the sample 3. The light emission microscope image 6 obtained at this time is stored in the data storage unit 10 via the network 15. Therefore, based on a program previously incorporated in the program storage unit 12, the data calculation unit 11 performs a failure location specifying operation using design information such as the layout data 8 and the netlist 9 and the light emission microscope image 6. (The detailed procedure will be described later). As an alternative to the network 15, data communication may be performed using a recording medium such as DAT (not shown). The input device 13 and the output device connected to the CAD device 1 enable user interface. The user may perform interlocking such as driving control of the light emitting microscope 2 by the CAD device 1 via the input device 13. Further, the calculation results (such as the coordinates of the failure position) obtained by the data calculation unit 11 may be stored in a database (not shown).
[0024]
Next, a specific failure location specifying method will be described. FIG. 1 is a diagram for explaining a failure location specifying method when a plurality of test patterns (a plurality of types of voltage setting patterns) are input. FIGS. 1A and 1B show superimposed images of the layout data 8 and the light emission microscope image 6 when the test patterns A and B are input, respectively. First, when the test pattern A is input in FIG. 1A, the light emission image 22 of the light emission point can be displayed on the layout pattern 20. At this time, the transistor 21 located in the region of the light emission image 22 is specified. Here, the transistor 21 itself may be out of order, but the transistor 21 is normal and there may be a cause of failure in the wiring path leading to it. Therefore, first, the upstream wiring path 23 obtained retroactively to the signal input side of the transistor 21 is highlighted on the layout pattern displayed on the output device 14. For this run-up, the connection information described in the netlist 9 may be used, or the graphic shape and arrangement information of the layout data 8 may be used. Further, the data storage unit 10 may store the wiring connection information of the upstream wiring path 23. Next, in FIG. 1B, the same operation as in FIG. Here, the light emission image 24 and the upstream route wiring 25 are obtained. Here, as shown in FIG. 1C, the emission image and the upstream wiring path in the test patterns A and B are superimposed. It is estimated that the overlapping wiring 26 (the thickest portion shown in the figure) of the upstream wiring paths 23 and 25 is most likely to be a failure, and the coordinate position of the overlapping wiring 26 and the wiring net shown in the net list are estimated. Specify the name of. If there is a defect in the duplicated wiring 26, the potential state can be confirmed with an electron beam tester or the like. If no defect is found here, the test pattern signal input side is further detected. It is only necessary to go up and identify the faulty wiring. Similarly, when there are a plurality of light emission locations in one test pattern, it is possible to narrow down the failure locations by superimposing the upstream path. At this time, it is effective to create a software program so that the user can set the number of stages of transistors to be moved up. Note that the condition for extracting that the failure probability is high is not limited to the case of overlapping (matching) as described above, and can be realized on the condition that the wirings are adjacent to each other. This is because there is a high possibility of short-circuiting if they are adjacent.
[0025]
Next, a method for identifying a transistor present at a light emission location based on a light emission image will be described. First, a method for assisting the user in identifying a transistor on the screen will be described. FIG. 3 is a diagram showing a method for extracting defective transistors on the screen of the CAD apparatus. After the user confirms the superimposed image of the light emitting image 22 and the layout pattern 20, the designated area frame 31 is designated by dragging with the cursor 30 using the input device 13 such as a mouse. The transistor 21 existing in the frame coordinate area is automatically extracted. This result may be output to the output device 14, or the coordinates and names of the transistors where defects are found, and the wiring net may be stored in the data storage unit. The transistor can be specified by using layout data 8, netlist 9, and schematic, or can be specified by a software program incorporated in the CAD apparatus using only layout data 8.
[0026]
In addition, a light emitting transistor can be automatically specified by a software program incorporated in a CAD apparatus. FIG. 4 is a diagram showing a method of automatically specifying a transistor from a light emission image. As shown in FIG. 4A, after superimposing the light emission image 24 on the layout pattern 20, as shown in FIG. 4B, the image of the light emitting portion is binarized with an arbitrary threshold value, and this binarization is performed. The emitted light images 40 are clustered in FIG. Clustering is for recognizing the binarized light emission image 40 as a group of light emission areas, and can be bordered as shown in FIG. Further, as shown in FIG. 4C ′, it is also possible to calculate a rectangle that surrounds the outermost peripheral pixel of the binarized emission image 40. If a light emitting region can be defined as data in FIGS. 4C and 4C ′, it is easy to define a transistor present in that region. The clustering is effective when abnormal light emission occurs at two locations simultaneously.
[0027]
Further, a method for weighting defective transistors using the light emission intensity will be described. FIG. 5 is a diagram illustrating a method of extracting defective transistors based on the emission intensity distribution. The dark portion of the luminescent image 22 is a portion with high emission intensity. The light emission phenomenon generally has an arbitrary intensity distribution as described above, and it is highly likely that the center is a place where abnormal light is generated. Here, the emission intensity increases in the order of the transistors 27 and 28. Therefore, from the viewpoint of the suspected defect, the priority order to be analyzed is the order of the transistors 27 and 28. For example, if the emission intensity distribution is expressed in a gray scale of 16 gradations, prioritization can be performed by specifying the transistors that exist in the areas having the respective gradations in order from the gradation with the highest luminance. .
(Second Embodiment)
Next, a second embodiment of the present invention will be described. Here, a failure location specifying method when an OBIRCH analyzer is used instead of the light emission microscope will be described. For the CAD apparatus and its system, the light emission microscope of FIG. 2 may be replaced with the OBIRCH analysis apparatus.
[0028]
FIG. 6 is a diagram illustrating a method of identifying a wiring that has an abnormal reaction from the OBIRCH image. After the user confirms the superimposed image of the OBIRCH image 50 and the layout pattern 20, the layout wiring overlapping the OBIRCH image is designated by the cursor 30 using the input device 13 such as a mouse. This result may be output by being highlighted on the output device 14, or the coordinates of the wiring where the abnormality is found and the wiring net name may be stored in the data storage unit. At this time, the wiring net may be specified using the layout data 8 and the net list 9, or the coordinates may be output by specifying only the layout data 8.
[0029]
Since the OBIRCH image obtained from the OBIRCH analysis device appears lower in resolution and wider than the wiring pitch, it may not be specified as a single wiring (illustrated in the bold line portion in FIG. 7). A method for solving this will be described next. FIG. 7 to FIG. 10 are diagrams showing a method of extracting wiring suspected of abnormality from the OBIRCH image. First, in a state where the layout pattern 20 and the OBIRCH image 50 are superimposed, as shown in FIG. 7, the first designated area frame 51 is designated by the input device 13 and the cursor 30 so as to surround a part of the OBIRCH image. Thereby, as shown in FIG. 8, one or more failure suspicious wirings 52 passing through this area can be specified. If it is possible to identify one wiring net, the match between the OBIRCH image 50 and the failure suspicious wiring 52 is confirmed, and the process ends. Here, when a plurality of wiring nets are output, the second designated area frame 53 is designated as shown in FIG. Here, the failure candidates can be further narrowed down by searching the wiring net under the condition that the first specified area frame 51 and the second specified area frame 53 are passed. FIG. 10 shows a case where only one faulty wiring 54 can be specified.
[0030]
Next, a method for automatically narrowing down failure candidates from the OBIRCH image will be described. FIG. 11 is a diagram illustrating a method for narrowing down a faulty wiring from an OBIRCH image. First, the OBIRCH image 50 is acquired in FIG. In FIG. 11B, the noise component of the OBIRCH image 50 is removed by image processing, and the template 55 is molded so that the shape of the wiring path can be reproduced. As shown in FIG. 11C, a wiring route that matches the template can be extracted from the layout, and the failed wiring 56 can be specified.
[0031]
A method for identifying a location where a defect exists utilizing the above-described failure wiring identification method will be described. FIG. 12 is a diagram illustrating a method of narrowing down a failure location when a plurality of test patterns are input. In FIG. 12, four types of test patterns are input in FIGS. In each test pattern, the OBIRCH reaction wirings 60 to 63 are identified using the OBIRCH fault wiring identification method as shown in FIGS. In FIG. 12E, the location of the defect 70 can be specified by overlapping the wirings 60 to 63 that have undergone the OBIRCH reaction and specifying the intersecting or dense region 64. At this time, the worker may visually determine the dense area, and it is also effective to emphasize the area in order to support this work. FIG. 13 is a diagram showing a display method of the density distribution. FIG. 13A is a diagram in which wirings 60 to 63 that have undergone an OBIRCH reaction are overlapped. As shown in FIG. 13B, if this layout is divided into orthogonal grids and the occupancy ratio of the wirings with the OBIRCH reaction corresponding to each grid area is calculated, the density distribution diagram 65 can be easily displayed. It becomes possible. Thereafter, the coordinates of the dense area or the coordinates of the center of gravity having a high degree of density can be automatically calculated to shorten the subsequent analysis work time.
[0032]
On the other hand, considering the case where a defect causes a short circuit, the accuracy of identifying a defect location can be supported by the following expression method of density distribution. FIG. 14 is a diagram illustrating a method for expressing the density of different wirings. FIG. 14A shows the result of overlaying wirings that have undergone an OBIRCH reaction. Among these, the wirings 66 and 67 that have undergone the OBIRCH reaction are densely packed with the same potential, so even if they are short-circuited, the function may not be affected unless they are short-circuited to other wirings. Therefore, in the method of simply expressing the density of wiring described in FIG. 13, a plurality of areas with the highest density (the darkest hatched part) as shown in FIG. descend. Therefore, as shown in FIG. 14C, the true critical area 69 can be specified by identifying the wiring and calculating only the density of the different kinds of wiring.
[0033]
The software program stored in the program storage unit 12 installed in the CAD device 1 will be described. FIG. 15 is a diagram showing an algorithm. Here, a typical algorithm is described, and the procedures described in the embodiments of the present invention can be appropriately incorporated. First, layout data 8, netlist 9, schematic (not shown), design additional information (technology file etc., not shown), etc. are stored in the data storage unit 10 by performing desired preprocessing (step 1). . Next, the tester 4 is driven based on the test pattern 5, and a desired voltage is applied to the sample 3 which is a semiconductor device such as a wafer (step 2). In this state, the light emission microscope 2 is driven, and the light emission microscope image 6 obtained at this time is stored in the data storage unit 10 (step 3). Here, the emission microscope image 6 and the layout data 8 are superimposed (step 4). Next, a transistor present in the light emitting region is specified (step 5). The wiring path on the input side of this transistor is run up (step 6). At this time, the number of upstream stages of the transistor may be stored in advance in a program, or an operator's input may be prompted in advance before going upstream. When inputting a plurality of test patterns, the light emission analysis is continued (step 7), and steps 2 to 6 are repeated. When the test pattern has been input, the overlapping wiring path is specified, stored and output (step 8).
(Third embodiment)
In the above embodiment, an example is shown in which a defect location is estimated by each of the light emission microscope and the OBIRCH analysis device. However, in actual analysis, it is also possible to estimate the failure location by combining both pieces of information. . One method is to collate defect candidates (for example, wiring or transistor elements) narrowed down by the OBIRCH analyzer with defect candidates obtained by going up from the light emission point detected by the light emission microscope. This is a technique for narrowing down. By doing this, it is possible to improve the accuracy of identifying the defective part, and further reduce the number of trial and error times of the analysis by the electron beam tester for narrowing down the defective part, or the FIB processing for the preparation.
(Fourth embodiment)
A method for narrowing down a defective part more accurately in a short time in the above-described defective part identification using a light emission microscope will be described. In order to describe the present embodiment, first, the light emission phenomenon of the MOS transistor due to the intermediate potential will be described with reference to FIG. This intermediate potential phenomenon is one of the causes of a typical light emission phenomenon. Consider a case where the wiring (A) 101 and the wiring (B) 102 connected to the gate of the MOS (A) 103 are short-circuited due to the short-circuit defect 104. In a certain state, when the voltage that should be originally set for the wiring (A) 101 and the wiring (B) 102 is different, this short circuit is affected by the potential of each other and becomes an intermediate potential of the setting potential of each wiring. This is called intermediate potential. When the wiring (A) 101 becomes an intermediate potential, the input potential for turning on / off the gate of the MOS (A) 103 becomes incomplete, causing a contact failure. At this stage, a transient abnormal current flows through the MOS (A) 103, which may cause light emission. Moreover, since the contact failure state of the MOS (A) 103 causes an unstable state of the gate potential of the MOS (B) 105 on the output side, a transient abnormal current flows through the MOS (B) 105. Thus, light emission is observed in the MOS (B) 105. The above is the light emission phenomenon due to the intermediate potential.
[0034]
Next, it is considered how the light emission phenomenon due to such an intermediate potential propagates in the logic circuit. FIG. 17 takes a NAND circuit, which is one of basic logic circuits, and explains an intermediate potential propagation phenomenon. FIG. 17 shows a case where any one of these terminals is set to an intermediate potential in an original state where the X terminal 110 serving as an input of the NAND circuit is at a low potential and the Y terminal 111 is at a high potential. FIG. 17A shows a case where the X terminal 110 has an intermediate potential, and FIG. 17B shows a case where the Y terminal 111 has an intermediate potential. First, since an intermediate potential is input to the pMOS 112 in FIG.
(1) The output of the pMOS 112 is in an intermediate potential or a potential state that fluctuates to High / Low.
(2) Since the pMOS 113 is turned off by the high potential of the normal Y terminal 111, the output of the pMOS 113 becomes a floating potential.
(3) The intermediate potential of the X terminal 110 causes unstable operation of the nMOS 115 and the nMOS 114 caused thereby (a potential state that fluctuates between High / Low).
[0035]
Since the entire NAND circuit is determined from the potential states of (1), (2), and (3), the potential state of the output terminal 116 eventually becomes unstable.
[0036]
On the other hand, for FIG.
(4) The pMOS 112 is turned ON and the output is High due to the low potential input of the normal X terminal 110.
(5) The operation of the pMOS 113 fluctuates to ON / OFF due to the intermediate potential of the Y terminal 111, high output when ON, and floating potential when OFF.
(6) Although the nMOS 114 fluctuates due to the intermediate potential input at the Y terminal 111, the nMOS 115 is eventually turned into a floating potential by the OFF state of the nMOS 115 due to the low potential at the X terminal 110.
[0037]
Due to the above (4), (5), and (6), the High output of the pMOS 112 becomes dominant, so that the output of the entire NAND circuit becomes High. When the NAND circuit output is at an intermediate potential and the original set voltage is Low at the X terminal and High at the Y terminal due to the above phenomenon, the cause of the failure is traced back as shown in FIG. It becomes a case, and it is only necessary to go up only the X terminal side. In this way, in the case of a basic logic circuit, if a fault dictionary (database) with intermediate potential propagation characteristics is created, the fault dictionary is referred to when going up the path (corresponding to step 6 in FIG. 15). Thus, the number of route suspicion candidates can be halved, and the failure analysis time can be shortened. Furthermore, when going up the basic logic solution over multiple stages, the failure analysis time is reduced to (1/2). ⁿ This shortening of the defect analysis TAT leads to a reduction in product development period and a reduction in resources for analyzing customer return defects.
[0038]
FIG. 18 shows an outline of a failure analysis system that goes up the path based on the intermediate potential propagation characteristics. The fault dictionary 120 stores data describing intermediate potential propagation characteristics for each cell such as various basic logic circuits and IP (Intellectual Property). This failure dictionary 120 is connected to the CAD device 1. All of the failure dictionary 120 or necessary data can be fetched into the data storage unit 10 inside the CAD apparatus 1, and calculation processing can be performed for going up while being narrowed down by the data calculation unit 11. FIG. 19 is a diagram for explaining the configuration of data registered in the failure dictionary 120. The cell name means a basic logic circuit name such as NAND or NOR or an IP name. A potential state (HIGH or LOW) is registered in the input number (input 1 to input N). Further, a file is created by associating the intermediate potential propagation output number corresponding to the output to which the intermediate potential has propagated with the upstream number indicating the input number to be upstream. In this way, if a circuit with an arbitrary cell name is in an arbitrary input potential state and an intermediate potential output number is given, it is possible to extract the most suspicious upstream number when performing the upstream operation. The failure location time can be shortened. This dictionary may define a failure model in advance and associate a simulation result of an arbitrary circuit in an arbitrary potential state, or may be based on actual data obtained from a failure analysis result of an actual product (there is some In the circuit, the intermediate potential output number from which the intermediate potential is output and the upstream input number whose cause has been confirmed are stored in correspondence with each other).
[0039]
【The invention's effect】
According to the present invention, in order to narrow down the wiring and the defective portion that are more suspected of failure, it is possible to reduce the accuracy of the failed portion and the failure portion specifying time. Thereby, it is possible to quickly analyze a defective portion of the semiconductor product, and it is possible to promptly improve the yield by estimating the mechanism.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining a failure location specifying method when a plurality of test patterns are input.
FIG. 2 is a diagram showing a CAD apparatus and its system.
FIG. 3 is a diagram showing a method for extracting defective transistors on a screen of a CAD device.
FIG. 4 is a diagram showing a method of automatically specifying a transistor from a light emission image.
FIG. 5 is a diagram showing a method for extracting defective transistors based on emission intensity distribution;
FIG. 6 is a diagram showing a method for identifying a wiring having an abnormal reaction from an OBIRCH image.
FIG. 7 is a diagram showing a method for extracting wiring suspected of abnormality from an OBIRCH image.
FIG. 8 is a diagram showing a method for extracting wiring suspected of abnormality from an OBIRCH image;
FIG. 9 is a diagram showing a method for extracting wiring suspected of abnormality from an OBIRCH image;
FIG. 10 is a diagram showing a method for extracting a wiring suspected of abnormality from an OBIRCH image.
FIG. 11 is a diagram showing a method of narrowing down faulty wiring from an OBIRCH image.
FIG. 12 is a diagram showing a method for narrowing down failure points when a plurality of test patterns are input.
FIG. 13: Display method of density distribution
FIG. 14 is a diagram showing a method of expressing the density of different wirings
FIG. 15 shows an algorithm.
FIG. 16 is a diagram showing a light emission phenomenon caused by an intermediate potential.
FIG. 17 is a diagram showing propagation characteristics of intermediate potential
FIG. 18 is a schematic diagram of a failure analysis system that moves up the path based on intermediate potential propagation characteristics.
FIG. 19 is a diagram for explaining the configuration of data registered in a failure dictionary
[Explanation of symbols]
20 ... Layout pattern, 21 ... Transistor, 22 ... Light emission image, 23 ... Upward wiring path, 24 ... Light emission image, 25 ... Upward wiring path, 26 ... Overlapping wiring

Claims (16)

When a voltage based on a plurality of types of voltage setting patterns is applied to the semiconductor device, the designated area frame surrounding the reaction site for each pattern acquired by the physical analysis device is input using a mouse or an automatic image recognition device. Receiving the reaction information obtained as a region;
Each reaction information is collated with layout pattern information of the semiconductor device, and each upstream wiring is routed up from the transistor existing in the range indicated by the reaction information in the direction of the voltage application position. Extracting by the arithmetic processing means;
A step of identifying and displaying on the display means a wiring range in which the route of the upstream wiring corresponding to each transistor matches or is adjacent;
A CAD tool for analyzing a semiconductor defect, characterized in that When a voltage based on a voltage setting pattern is applied to a semiconductor device, a designated region frame surrounding reaction points acquired by a physical analysis device can be obtained as a region by an input device using a mouse or an automatic image recognition device. Receiving the reaction information;
Each reaction information is collated with layout pattern information of the semiconductor device, and each upstream wiring is routed up from the transistor existing in the range indicated by the reaction information in the direction of the voltage application position. Extracting by the arithmetic processing means;
A step of identifying and displaying on the display means a wiring range in which the route of the upstream wiring corresponding to each transistor matches or is adjacent;
A CAD tool for analyzing a semiconductor defect, characterized in that A CAD tool for semiconductor failure analysis according to claim 1 or 2,
When there are a plurality of transistors in the range of the position indicated by the reaction information, a semiconductor failure analysis is performed by performing an upstream processing operation from a transistor located in a range of high emission intensity within the range. CAD tool for A CAD tool for semiconductor failure analysis according to claim 1 or 2,
A CAD tool for semiconductor failure analysis, wherein a light emission microscope is used as the physical analysis device. A reaction state when a voltage based on a plurality of types of voltage setting patterns is applied to a semiconductor device, an input device using a mouse for a designated area frame surrounding the reaction site for each pattern using a light emission microscope, or an automatic image recognition device Obtained as reaction information obtained as a region by
Each reaction information is collated with layout pattern information of the semiconductor device, and each upstream wiring is routed up from the transistor existing in the range indicated by the reaction information in the direction of the voltage application position. Extracted by arithmetic processing means,
A semiconductor failure analysis method, characterized in that a wiring range in which the route of the upstream wiring corresponding to each transistor matches or is adjacent is specified and displayed on a display means. Reaction information when a voltage based on a voltage setting pattern is applied to a semiconductor device, reaction information obtained as an area by an input device using a mouse or an automatic image recognition device with a designated region frame surrounding the reaction site using a light emission microscope Get
When there are a plurality of the reaction information, each of the reaction information is collated with the layout pattern information of the semiconductor device, and the wiring path is traced back from the transistor existing within the position indicated by the reaction information to the voltage application position direction. By extracting, each upstream wiring is extracted by arithmetic processing means,
A semiconductor failure analysis method, characterized in that a wiring range in which the route of the upstream wiring corresponding to each transistor matches or is adjacent is specified and displayed on a display means. A semiconductor failure analysis method according to claim 5 or 6,
When there are a plurality of transistors in the range of the position indicated by the reaction information, a semiconductor failure analysis is performed by performing an upstream processing operation from a transistor located in a range of high emission intensity within the range. Method. When applying a voltage based on a plurality of types of voltage setting patterns to the semiconductor device, receiving the input of reaction information for each of the patterns acquired by the physical analysis device;
Forming a template representing a reaction shape corresponding to each of the reaction information;
Extracting the wiring path on the layout by the arithmetic processing means by matching the template and the layout pattern information of the semiconductor device;
Displaying the wiring route corresponding to each pattern on a display means;
A CAD tool for analyzing a semiconductor defect, characterized in that When applying a voltage based on a plurality of types of voltage setting patterns to the semiconductor device, receiving the input of reaction information for each of the patterns acquired by the physical analysis device;
Forming a template representing a reaction shape corresponding to each of the reaction information;
Extracting the wiring path on the layout by the arithmetic processing means by matching the template and the layout pattern information of the semiconductor device;
A step of displaying a dense distribution based on the degree of wiring density on the display means when the extracted wiring paths corresponding to each pattern are superimposed;
A CAD tool for analyzing a semiconductor defect, characterized in that A CAD tool for semiconductor failure analysis according to claim 9,
A CAD tool for analyzing a semiconductor defect, characterized in that, when the wiring paths are superimposed, a density distribution is displayed as a result of calculation processing by deleting a portion where wiring paths with the same potential are dense. A CAD tool for semiconductor failure analysis according to claim 8 or 9,
A CAD tool for semiconductor failure analysis, wherein an OBIRCH analysis device is used as the physical analysis device. A reaction state when a voltage based on a plurality of types of voltage setting patterns is applied to the semiconductor device is obtained as reaction information for each pattern by a physical analysis device,
Forming a template representing a reaction shape corresponding to each of the reaction information;
By matching the template and the layout pattern information of the semiconductor device, the wiring path on the layout is extracted by the arithmetic processing means,
A method for analyzing a semiconductor failure, wherein the wiring path corresponding to each pattern is displayed on a display means. A reaction state when a voltage based on a plurality of types of voltage setting patterns is applied to the semiconductor device is obtained as reaction information for each pattern by a physical analysis device,
Forming a template representing a reaction shape corresponding to each of the reaction information;
By matching the template and the layout pattern information of the semiconductor device, the wiring path on the layout is extracted by the arithmetic processing means,
A semiconductor failure analysis method, wherein a dense distribution based on a degree of wiring density is displayed on a display means when the extracted wiring paths corresponding to each pattern are superimposed. The semiconductor failure analysis method according to claim 13,
A method of analyzing a semiconductor failure, wherein when the wiring paths are superimposed, a density distribution as a result of performing arithmetic processing by deleting a portion where wiring paths having the same potential are dense is displayed. A CAD tool for analyzing a semiconductor failure according to any one of claims 1 to 4,
When going up the wiring path in the direction of the voltage application position, referring to a failure dictionary in which an intermediate potential propagation phenomenon due to a defect is modeled in advance, selecting a wire having a high possibility of failure and going up CAD tool for semiconductor failure analysis. A semiconductor failure analysis method according to any one of claims 5 to 7,
When going up the wiring path in the direction of the voltage application position, referring to a failure dictionary in which an intermediate potential propagation phenomenon due to a defect is modeled in advance, selecting a wire having a high possibility of failure and going up Semiconductor failure analysis method.

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