JPH01270191A - Memory card - Google Patents
Memory cardInfo
- Publication number
- JPH01270191A JPH01270191A JP63098208A JP9820888A JPH01270191A JP H01270191 A JPH01270191 A JP H01270191A JP 63098208 A JP63098208 A JP 63098208A JP 9820888 A JP9820888 A JP 9820888A JP H01270191 A JPH01270191 A JP H01270191A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- data
- memory card
- circuit
- connector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000006870 function Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は、メモリカードに関し、特に、キーデータによ
るリードライトプロテクト機能を備えたメモリカードに
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory card, and particularly to a memory card having a read/write protection function using key data.
[従来の技術]
第2図は、従来のメモリカードのブロック図、第3図は
第2図に示すメモリカードの外観図である。なお、第3
図に示す大きさおよび形状は一般規格のものを示してい
る。[Prior Art] FIG. 2 is a block diagram of a conventional memory card, and FIG. 3 is an external view of the memory card shown in FIG. 2. In addition, the third
The sizes and shapes shown in the figures are those of general standards.
第2図において、1はカード端面に設けられたコネクタ
、2はバッファ回路、3はメモリIC14は制御回路で
ある。In FIG. 2, 1 is a connector provided on the end face of the card, 2 is a buffer circuit, and 3 is a memory IC 14 which is a control circuit.
上記構成からなるメモリカードでは、カード端面のコネ
クタlを通してデータバス信号5と、アドレスバス信号
6と、制御信号7が入出力される。In the memory card having the above configuration, a data bus signal 5, an address bus signal 6, and a control signal 7 are input and output through the connector l on the end face of the card.
そして、データバス信号5と、アドレスバス信号6は、
バッファ回路2を通してメモリIC3に印加され、制御
回′tli4のiti’制御信号7によってメモリに対
するデータリードまたはライトの動作がなされていた。The data bus signal 5 and address bus signal 6 are
The signal is applied to the memory IC 3 through the buffer circuit 2, and a data read or write operation to the memory is performed by the iti' control signal 7 of the control circuit 'tli4.
[解決すへさ問題点]
し述した従来のメモリカードは、メモリのり−ト・ライ
トを自由に行なうことができたため、l要なデータや守
秘データであっても、容易にり−ト・ライトができてし
まうという問題点があった。[Problems that need to be solved] The conventional memory cards mentioned above can be freely written to and written to the memory, so even if it is important or confidential data, it is easy to write or write to the memory. There was a problem with the light being created.
本発明は、上記問題点にかんがみてなされたもので、デ
ータをプロテクトする機能を備えたメモリカードの提供
を目的とする。The present invention was made in view of the above-mentioned problems, and an object of the present invention is to provide a memory card having a function of protecting data.
[問題点の解決手段]
一ヒ記目的を達成するため、本発明のメモリカードは、
コネクタを有するシート状筺体と、上記コネクタを通し
て入出力されるデータを記憶するメモリICと、このメ
モリICと上記コネクタとの間で入出力されるデータを
一時記憶するバッファと、このバッファを介して上記メ
モリICに入出力されるデータの暗号化と復号化を行な
う暗号化・復号化回路と、この暗号化・復号化回路と上
記メモリICを制御する制御回路とを備えた構成としで
ある。[Means for solving problems] In order to achieve the above object, the memory card of the present invention has the following features:
a sheet-like housing having a connector; a memory IC that stores data that is input and output through the connector; a buffer that temporarily stores data that is input and output between the memory IC and the connector; The configuration includes an encryption/decryption circuit that encrypts and decrypts data input to and output from the memory IC, and a control circuit that controls the encryption/decryption circuit and the memory IC.
すなわち、メモリデータの読み出し時あるいは古き込み
時に、データの暗号化と1u号化を行なう機能を■−λ
ている。In other words, the function to perform data encryption and 1u encryption when reading memory data or loading old data is
ing.
[実施例] 以下、図面にもとづいて本発明の詳細な説明する。[Example] Hereinafter, the present invention will be explained in detail based on the drawings.
第1図は、本発明の一実施例に係るメモリカードのブロ
ック図である。なお、従来例と共通または対応する部分
については同一の符号で表す。FIG. 1 is a block diagram of a memory card according to an embodiment of the present invention. Note that parts common to or corresponding to those of the conventional example are denoted by the same reference numerals.
同図において、lOは暗号化・復号化回路であり、バッ
ファ回路2とメモリIC3の間に設置されている。In the figure, IO is an encryption/decryption circuit, which is installed between the buffer circuit 2 and the memory IC 3.
上記構成において、暗号化・復号化回路lOは、制御回
路4の制御にもとづいて、データのリード時あるいはラ
イト時にデータを暗号化または復号化する。In the above configuration, the encryption/decryption circuit IO encrypts or decrypts data when reading or writing data under the control of the control circuit 4.
従って、データあるいはアドレスかこの暗号化・復号化
回路lOを通過する際、それぞれ暗号化、または復号化
されることになる。このため、データは外部に対して暗
号化される。なお、この暗号化または復号化は、キーデ
ータに従い、制御回路40制御のちとに行なわれる。Therefore, when data or addresses pass through this encryption/decryption circuit IO, they are respectively encrypted or decrypted. Therefore, the data is encrypted to the outside world. Note that this encryption or decryption is performed after the control circuit 40 controls according to the key data.
このように本実施例は、85゜6mmX54゜0 m
m X 3 、 0 m +nのシート状筺体に、所定
のメモリICとその周辺回路を内包するとともに、その
一端面には外部接続用コネクタを有するメモリカードに
おいて、メモリデータの読み出し時またはXNき込み時
に、人力されたデータの暗号化または復号化を行なう8
1能を有している。In this way, this example has a size of 85゜6mm x 54゜0m.
In a memory card that contains a predetermined memory IC and its peripheral circuits in a sheet-like housing of m x 3, 0 m + n, and has a connector for external connection on one end surface, it is used when reading memory data or writing XN. Occasionally encrypts or decrypts manually generated data8
1 ability.
なお、本発明は上記実施例に限定されるものでなく、要
旨の範囲内における種々変形例を含むものである。例え
は、上述の実施例では、一般規格の大きさのシート状筺
体を使用しているが、この大きさ、形状にとられれろも
のでないことはいうまでもない。It should be noted that the present invention is not limited to the above embodiments, but includes various modifications within the scope of the gist. For example, in the above-described embodiment, a sheet-like housing having a general standard size is used, but it goes without saying that the size and shape are not limited to this.
[発明の効果]
以上説明したように本発明は、メモリカード内に暗号化
・復号化回路を設けることにより、外部に対してデータ
が暗号化され、データを1呆謹することが可能なメモリ
カードを提供できるという効果がある。[Effects of the Invention] As explained above, the present invention provides a memory in which data is encrypted to the outside by providing an encryption/decryption circuit in the memory card, and the data can be protected from the outside. This has the effect of being able to provide cards.
第1図は本発明の一実施例に係るメモリカードの70ツ
ク図1.第2図は従来のメモリカードのブロック図、第
3図は第2図に示すメモリカードの外観図である。
1:コネクタ
2:バッフ7回路
3:メモリIC
、!l二制御回路
lO:暗号化・復号化回路FIG. 1 is a 70-piece diagram of a memory card according to an embodiment of the present invention. FIG. 2 is a block diagram of a conventional memory card, and FIG. 3 is an external view of the memory card shown in FIG. 1: Connector 2: Buffer 7 circuit 3: Memory IC,! l2 control circuit lO: encryption/decryption circuit
Claims (1)
して入出力されるデータを記憶するメモリICと、この
メモリICと上記コネクタとの間で入出力されるデータ
を一時記憶するバッフアと、このバッフアを介して上記
メモリICに入出力されるデータの暗号化と復号化を行
なう暗号化・復号化回路と、この暗号化・復号化回路と
上記メモリICを制御する制御回路とを具備することを
特徴とするメモリカード。a sheet-like housing having a connector; a memory IC that stores data input and output through the connector; a buffer that temporarily stores data that is input and output between the memory IC and the connector; It is characterized by comprising an encryption/decryption circuit that encrypts and decrypts data input/output to the memory IC, and a control circuit that controls the encryption/decryption circuit and the memory IC. Memory card.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63098208A JPH01270191A (en) | 1988-04-22 | 1988-04-22 | Memory card |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63098208A JPH01270191A (en) | 1988-04-22 | 1988-04-22 | Memory card |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01270191A true JPH01270191A (en) | 1989-10-27 |
Family
ID=14213567
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63098208A Pending JPH01270191A (en) | 1988-04-22 | 1988-04-22 | Memory card |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01270191A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006051639A1 (en) * | 2004-11-15 | 2006-05-18 | Ikuo Yamaguchi | Semiconductor memory device |
US7770027B2 (en) | 2004-11-15 | 2010-08-03 | Nintendo Co., Ltd. | Semiconductor memory device |
GB2593663A (en) * | 2020-01-24 | 2021-10-06 | Rigloo Ltd | Deployable shelter with adaptable floor |
-
1988
- 1988-04-22 JP JP63098208A patent/JPH01270191A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006051639A1 (en) * | 2004-11-15 | 2006-05-18 | Ikuo Yamaguchi | Semiconductor memory device |
CN100416518C (en) * | 2004-11-15 | 2008-09-03 | 山口育男 | Semiconductor memory device |
US7770027B2 (en) | 2004-11-15 | 2010-08-03 | Nintendo Co., Ltd. | Semiconductor memory device |
GB2593663A (en) * | 2020-01-24 | 2021-10-06 | Rigloo Ltd | Deployable shelter with adaptable floor |
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