JPH01254075A - Screen display circuit - Google Patents

Abstract

PURPOSE:To make the display position constant even if a vertical synchronizing signal and a horizontal synchronizing signal are changed by using a display position controller so as to control a character generator in response to a count output of a vertical counter and a horizontal counter counting the vertical synchronizing signal and the horizontal synchronizing signal. CONSTITUTION:An output 21 of the vertical count and an output 22 of the horizontal count being the result of counting the vertical synchronizing signal and the horizontal synchronizing signal by the vertical counter 19 and the horizontal counter 20 respectively are fed to a display position controller 23. Then the timing controller 13 is controlled in response to the frequency of the vertical synchronizing signal and the horizontal synchronizing signal by the display position controller 23. Thus, even if the standard of the received video signal is changed or the frequency of the vertical synchronizing signal and the horizontal synchronizing signal being the nonstandard signal at the outside of standards is changed, a character display device 17 is kept constant and since the display position is unchanged to the user, the picture easy to see at all times is obtained.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is capable of keeping the screen display position of a color television receiver constant even when different systems such as PAL system and NTSC system, non-standard signals, etc. are input. This invention relates to a screen display circuit that is designed to hang down.

[Conventional technology]

FIG. 2 is a block diagram showing a conventional screen display circuit.
In the figure, 1 is the video signal input (including RGB input)
, 2 is a signal processing circuit, 3 is a signal output, 6 is a CRT drive circuit, 7 is a CRT drive output, and 8 is a CRT.

Further, 4 is a synchronous signal input, 5 is a synchronous deflection circuit, and 9 is a deflection output which is applied to the CRT 8.

10 is a vertical synchronization signal separated by the synchronization deflection circuit 5 and sent to the timing controller 13.

Reference numeral 11 denotes a horizontal synchronization signal separated by the synchronization deflection circuit 5, which is output to the timing controller 13.

12 is a character command input, which is input to the timing controller 13, and this timing controller 1
3, a timing controller output 14 is sent to a character generator 17.

Data is exchanged between the character generator 17 and the character memory 15 via a character bus 16.

A display output 18 is output from the character generator 17, and is sent to the CRT drive circuit 6. Thereby, the display output 18 is superimposed on the signal output 3 of the signal processing circuit 2 in the CRT drive circuit 6.

The timing controller output 14 is the vertical synchronization signal l.
This is an output for controlling the character generator 17 in synchronization with the horizontal synchronization signal 11 and in response to the character output command 12.

Next, the operation will be explained. A video signal (including RGB signals) is input from a video signal input circuit 1, subjected to video signal processing by a signal processing circuit 2, outputted as a signal output 3, and inputted to a CRT drive circuit 6.

Further, a synchronizing signal (either a composite video signal or a signal in which only the synchronizing signal is separated) is input from the synchronizing signal input 4 to the synchronizing deflection circuit 5, and a deflection output 9 is output to the CRT 8.

A vertical synchronization signal 10 and a horizontal synchronization signal 11 output from the synchronization deflection circuit 5 are input to a timing controller 13, and are used as reference signals so that the display output 18 is synchronized with the video signal input l.

A character generator 17 is controlled by a timing controller output 14 output from a timing controller 13 in response to a character output command 12.

In addition, character data corresponding to the character output command 12 is transferred from the character memory 15 to the character bus 16.
It is manually input to the character generator 17 via .

Character bus 16 is a bidirectional bus for accessing character memory 15, such as addresses and character data. The display output 1st output from the character generator 17 is the signal output 3 from the CRT drive circuit 6.
A display output appears on the screen by being superimposed on the output signal and supplied to the CRT 8 as a CRT drive output cuff.

Here, the setting of the display position in the timing controller 13 is fixed, and when the frequencies of the vertical synchronization signal 10 and the horizontal synchronization signal 11 change (for example, when the system changes between NTSC and PAL systems, broadcasting of non-standard signals etc. (When using a signal that does not meet the standards) The display position is not constant.

[Problem to be solved by the invention]

Since the conventional screen display circuit is configured as described above, the display position setting is fixed by the timing controller, that is, the frequency of the vertical synchronization signal of the video input signal is 50 Hz, and the frequency of the horizontal synchronization signal is 50 Hz. is 15.
When the frequency is 625 KHz, the number of horizontal synchronization signals that exist within period i shown in Figure 3 and the number of pulses of the horizontal clock oscillator output within the timing controller that exist within period j are fixed so that they are displayed at a specific position. For example, when a PAL signal is changed to an NTSC signal, the display that was displayed at the top and bottom of the CRT 8 during the PAL signal is hidden.

This invention was made to solve the above-mentioned problems. For example, when the frequency of the vertical synchronization signal and horizontal synchronization signal changes due to a change from a PAL signal to an NTSC signal or from a standard signal to a non-standard signal, etc. The purpose of the present invention is to obtain a screen display circuit that can keep the screen display position of characters, etc. constant even when the screen display position is constant.

[Means to solve the problem]

The screen display circuit according to the second invention includes a horizontal synchronizing signal counting circuit that counts the frequency of a horizontal synchronizing signal and a vertical synchronizing signal, a vertical synchronizing signal counting circuit, and each of the horizontal synchronizing signal counting circuit and the vertical synchronizing signal counting circuit. The character generator is provided with a display position controller that controls the character generator so that the display position is constant in response to the output of the character generator.

[For production]

In this invention, the vertical synchronization signal and the horizontal synchronization signal output from the synchronization deflection circuit are counted by the vertical synchronization signal counting circuit and the horizontal synchronization signal counting circuit, respectively, and the vertical synchronization signal and the horizontal synchronization signal outputted from the synchronization deflection circuit are counted by the vertical synchronization signal counting circuit and the horizontal synchronization signal counting circuit, respectively. A display position controller controls a character generator to maintain a constant display position even if a vertical synchronization signal and a horizontal synchronization signal change.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, numbers 1 to 18 are the same as in Figure 2,
In this FIG. 1, reference numerals 19 to 24 are newly added to the configuration of FIG. 2.
The parts shown are added.

That is, the vertical synchronization signal 10 output from the synchronization deflection circuit 5 is output to a vertical synchronization signal counting circuit 19 (hereinafter referred to as a vertical counter) and the timing controller 13; The horizontal synchronization signal 11 to be generated is processed by a horizontal synchronization signal counting circuit 20 (hereinafter referred to as a horizontal counter) and a timing controller 13.
It is now output to .

Vertical counter output 21 output from vertical counter 19
and the horizontal counter output 2 output from the horizontal counter 20.
2 are adapted to be output to the display position controller 13, respectively. A display position controller output 24 output from the display position controller 13 is sent to the timing controller 13. Other parts are the same as in FIG.

Next, the operation will be explained. Vertical synchronization signal 10 output from the synchronization deflection circuit 5. The horizontal synchronizing signal 11 is sent to the vertical counter 19 . horizontal counter 20 and vertical counter 19 . Each frequency is counted by a horizontal counter 20.

A vertical counter output 21 (for example, rv (Hz)) from the vertical counter 19 is input to the display position controller 23, and a horizontal counter output 22 (for example, L+(Hz)) from the horizontal counter 20 is input to the display position controller 23.

The display position controller 23 receives these vertical counter outputs 21 . After the horizontal counter output 22 is manually subjected to arithmetic processing, which will be described later, a display position controller output 24 is input to the timing controller 13 in order to control the screen display position to be constant. Operations other than the above are the same as in FIG. 2.

Here, the operation of the display position controller 23 will be explained in more detail with reference to FIG. FIG. 3 illustrates the relationship among the screen display position, the effective screen on the CRTB, the horizontal synchronization signal, and the vertical synchronization signal.

As shown in FIG. 3, a virtual position A determined by the trailing edge (rising edge) of the vertical synchronizing signal V and the trailing edge (rising edge) of the horizontal synchronizing signal H will be referred to as the reference position for display.

It is assumed that the start and end positions of the effective signal period (the signal period displayed on the CR7 screen) in the horizontal and vertical directions with respect to the reference position 11fA of this display are always kept constant.

That is, the length of the period from the trailing edge of the horizontal synchronizing signal H to the next leading edge is b, the length from the trailing edge of the vertical synchronizing signal ■ to the next leading edge is a, and the length from the reference position A of the display is The length of the period to the start of the valid signal period in the horizontal direction is 01 The length of the period from the reference position A to the start of the valid signal period in the vertical direction is d, and the length of the valid signal period of the horizontal synchronization signal H Let e be the length of the effective signal period of the vertical synchronization signal V, and it is assumed that fce a'a'b' b is kept constant.

In addition, the length of the horizontal synchronizing pulse is g, the length of the vertical synchronizing pulse is h, the period from the display reference position WA to the horizontal display start position is j, and the vertical display start position from the display reference position A is i, the timing controller 13
Let the horizontal clock oscillation frequency within the range be kHz.

The display start position in the horizontal direction is determined by counting the number of horizontal synchronizing pulses from the trailing edge of the vertical synchronizing signal ■ (vertical synchronizing signal 10 in FIG. 1), and then counting the number of horizontal synchronizing pulses from the trailing edge of the vertical synchronizing signal H (horizontal synchronizing signal
) is determined by counting the output of the horizontal clock oscillator in the timing controller 13 from the trailing edge of .

At this time, if the number of horizontal synchronization pulses indicating the display start position and the number of output pulses of the horizontal clock oscillator are fixed, when the frequencies of the horizontal synchronization signal H and the vertical synchronization signal ■ change, the display on the CRT8. The display position in the horizontal and vertical directions on the effective screen changes.

Therefore, when the horizontal counter output 22 of the horizontal counter 20 that counts the frequency of the horizontal synchronization signal H1l and the vertical body symbol V10 is fH, and when the vertical counter output 21 of the vertical counter 19 is rv, -1- is In order to control b + g to be constant, it is the horizontal clock oscillator output in period j, and in the vertical direction, to control +5 to be constant, it is the horizontal synchronization pulse in period i. The number is −mu×□
Make it into a book.

fya+h By sending the vertical counter output 21 and horizontal counter output 22 to the display position controller 23 and performing the above-mentioned control with the display position controller, the display position on the CRTB can be kept constant.

In the above embodiment, the vertical counter 9. Horizontal counter 203 display position controller 23. Although each program such as the timing controller 13 can be implemented individually using hardware, the portion surrounded by dotted lines in FIG. 1 can also be implemented using a one-chip microprocessor.

Implementation using this microprocessor has the advantage that the device can be made inexpensive.

〔Effect of the invention〕

As described above, according to the present invention, the vertical count output and the horizontal count output obtained by counting the vertical synchronization signal and the horizontal synchronization signal by the vertical counter and the horizontal counter, respectively, are added to the display position controller, and the display position controller performs horizontal synchronization. Since the timing controller is configured to be controlled according to the frequency of the signal and the vertical synchronization signal, for example, if the standard of the received video signal changes,
Even if the frequency of the horizontal synchronization signal and vertical synchronization signal changes, such as non-standard signals, the character display device can be kept constant and the display position does not change for the user, making it extremely easy to see. effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a screen display circuit according to an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional screen display circuit, and FIG. 3 is a block diagram for explaining the present invention and the conventional screen display circuit. This is an explanatory picture showing the relationship between an effective screen on a CRT, a horizontal synchronization signal, and a vertical synchronization signal. 5 is a synchronous deflection circuit, 6 is a CRT drive circuit, 8 is a CR
T, 13 is a timing controller, 17 is a character generator, 19 is a vertical counter (vertical synchronous signal counting circuit), 20 is a horizontal counter (horizontal synchronous signal counting circuit)
, 23 is a display position controller. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] A synchronous deflection circuit that outputs a vertical synchronous signal and a horizontal synchronous signal from a synchronous signal, a vertical synchronous signal counting circuit that counts the vertical synchronous signal and outputs a vertical count output, and a synchronous deflection circuit that outputs a vertical synchronous signal and a horizontal synchronous signal from the synchronous signal; a horizontal synchronization signal counting circuit that counts and outputs a horizontal count output; a display position controller that performs arithmetic processing on the vertical count output and the horizontal count output to output a display position controller output; and the vertical synchronization signal and the horizontal synchronization signal. a timing controller that outputs a timing control output in response to a display output command input in synchronization with the display position controller, and the timing control output is controlled by the display position controller output; a character generator that is controlled by a character generator and outputs a display output so as to always maintain a constant character display position on a CRT even if the frequency of at least one of the vertical synchronization signal and the horizontal synchronization signal changes;
A screen display circuit comprising: a CRT drive circuit that drives the CRT by superimposing the display output as a reference signal on a signal-processed video signal.