JPH01236343A - Data transfer equipment - Google Patents

Abstract

PURPOSE:To efficiently use a bus when difference between time required for producing data and the period of data transfer is large by reading out data corresponding to a transferred address out of the data accumulated in a data accumulating means. CONSTITUTION:When the time required for producing data is shorter than the time required for generating an address, namely, the time required for actually transferring the data, data produced in a short time are transferred independently from the address by a high-speed data transferring means 1 at high speed and accumulated in a data accumulating means 2. On the other hand, the address is transferred at timing which is independent from the data transfer timing by means of an address transfer means 3. An accumulated data reading-out means 4 reads out data corresponding to transferred addresses out of the data accumulated in the data accumulating means 2 every time when the addresses are transferred.

Description

[Detailed Description of the Invention] [Summary] Regarding a data transfer device using random access, when there is a large difference between the time required to generate data and the actual data transfer cycle, a bus for transferring data is efficiently used. A high-speed data transfer means for transferring data at high speed, a data accumulation means for accumulating the transferred data, an address transfer means for transferring an address to which the data is transferred, and the data accumulation means. and stored data reading means for reading data corresponding to the transferred address from among the data stored in the storage device.

[Industrial application field]

The present invention relates to a data transfer device using random access.

Conventionally, in a data transfer device that performs data transfer by random access in which each piece of data is transferred to a random address, the time required to generate the data to be transferred or the time required to generate the address, When the difference between the time required to complete one data transfer procedure and the time required to complete one data transfer procedure is large, there is a problem in that the usage efficiency of the bus used for transfer decreases.

Therefore, there has been a demand for technology that enables efficient use of buses in data transfer devices using random access.

[Prior art and problems to be solved by the invention]

Data transfer may be performed by sequential access, in which a series of data is sequentially transferred to consecutive address areas, or by random access, in which individual pieces of data are transferred to random addresses.

In the case of the latter random access, it is necessary to send to the transfer destination the address for transferring the data at the same time as each piece of data.

However, since the above-mentioned data and address for -i are each obtained by calculation or the like, the time required to generate the data and address to be sent next differs.

Furthermore, there may be cases where it is required to perform some kind of processing on these data and addresses at the destination where they are transferred. One data transfer is completed only after generation of these data and addresses and processing at the transfer destination are all completed.

Therefore, the period for transmitting the data and address is determined by the time required to complete one data transfer. Therefore, even if the above-mentioned data or address can be generated in a short time, it is necessary to wait until the above-mentioned one data transfer is completed. This means that the bus used for data or address transfers is monopolized, at least intermittently, for a longer period of time than necessary, and especially when the bus used for data transfers is In a system in which other devices are also connected and the bus is also used by the other devices, there is a problem in that the bus usage efficiency is reduced.

The present invention has been made in view of the above problems, and is intended to efficiently utilize a bus for transferring data or addresses when there is a large difference between the time required to generate data or addresses and the actual data transfer cycle. The purpose is to provide a data transfer device.

[Means to solve the problem]

FIG. 1 is a basic configuration diagram of a first embodiment of the present invention. In this figure, 1 is a data high-speed transfer means, 2 is a data storage means, 3 is an address transfer means, and 4 is a stored data reading means.

The high-speed data transfer means 1 transfers data at high speed.

The data storage means 2 stores the transferred data.

The address transfer means 3 transfers the address to which the data is to be transferred.

The stored data reading means 4 reads out data stored in the data storage means 2 that corresponds to the transferred address.

FIG. 2 is a basic configuration diagram of a second embodiment of the present invention. In this figure, 5 is address high-speed transfer means, 6 is address storage means, 7 is data transfer means, and 8 is stored address reading means.

The high-speed address transfer means 5 transfers addresses at high speed.

The address storage means 6 stores the transferred address.

The data transfer means 7 transfers data corresponding to the address.

The stored address reading means 8 reads out the addresses stored in the address storage means 7 that correspond to the transferred data.

FIG. 3 is a basic configuration diagram of a third embodiment of the present invention. In this figure, 1 is a data high-speed transfer means, 2 is a data storage means, 5 is an address high-speed transfer means, 6 is an address storage means, and 9 is a stored address/data processing means.

The data high-speed transfer means 1 transfers data at high speed.

The data storage means 2 stores the transferred data.

The high-speed address transfer means 5 transfers addresses at high speed.

The address storage means 6 stores the transferred address.

The stored address/data processing means 9 reads addresses and data from the address storage means 6 and the data storage means 2 in the order in which they were stored first, and performs predetermined processing.

[For production]

In a first aspect of the present invention, the time required to generate data is
less than the time required to generate the address, so
It is used when the time required for actual data transfer is shorter, and data generated in a short time is transferred at high speed by the data high speed transfer means 1 independently of the address. Then, the data is stored in the data storage means 2.

On the other hand, the address transfer means 3 transfers the address at a timing independent of the data. Every time an address is transferred, the stored data reading means 4 reads out data stored in the data storage means 2 that corresponds to the transferred address.

Therefore, on the bus that transfers data, data is transferred without waiting for the generation of an address, so the data transfer is completed in a short time, and the bus that transfers the data is monopolized in a short time. There is more margin for use by other devices. In other words, the usage efficiency of the bus for transferring data is improved.

A second aspect of the invention is that the time required to generate the address is less than the time required to generate the data;
This is applied when the time required for actual data transfer is shorter, and addresses generated in a short time are transferred at high speed by the address high speed transfer means 5 independently of data. Then, it is stored in the address storage means 6.

On the other hand, data is transferred by the data transfer means 7 at a timing independent of the address. Every time data is transferred, the stored address reading means 4 reads out the addresses stored in the address storage means 2 that correspond to the transferred data.

Therefore, on a bus that transfers addresses, addresses are transferred without waiting for data to occur, which increases the margin for use of the bus that transfers addresses by other devices. In other words, the efficiency of using the bus for transferring addresses is improved.

A third aspect of the present invention is the time required to generate an address;
The time required to generate the data and data is shorter than the processing time from receiving the previous data and address at the destination of the data to being in a state where the next data and address can be received, respectively. Therefore, the actual data This is applied when the period is shorter than the transfer cycle, and addresses and data generated in a short time are transferred at high speed by the high-speed address transfer means 5 and the high-speed data transfer means 1, respectively, independently of each other. And, respectively,
It is stored in the address storage means 6 and the data storage means 2.

When the stored address/data processing means 9 finishes processing the previously read address and data, the stored address/data processing means 9 receives the next address and data from the address storage means 6 and the data storage means 2, respectively, after the previously read address and data. The stored addresses and data are read out and predetermined processing is performed on them.

Therefore, without waiting for the completion of processing at the address and data transfer destinations on each of the bus that transfers addresses and the bus that transfers data,
As the next address and data are transferred, the bus that transfers the address and the bus that transfers the data have more margin for use by other devices, respectively. In other words, the usage efficiency of the bus for transferring addresses and the bus for transferring data is improved.

〔Example〕

FIG. 4 shows an example of the present invention in which a vector drawing data generation section 100 that generates vector drawing data and a drawing address is connected to an image memory section 20 in an image processing apparatus.
0 shows a configuration for transferring the vector drawing data and drawing address and writing the vector drawing data corresponding to the bitmap.

When writing image data to the image memory, if the data of all pixels in a rectangular area is transferred and written by raster scanning, if the first address is given first, subsequent addresses will be written to the image memory by a simple increment operation. Therefore, data can be transferred one after another in synchronization with a clock using a synchronous bus, and high-speed data transfer is possible.

However, when vector drawing is performed, the image data of each pixel is transferred by random access to the image memory, so it is necessary to transfer the drawing address of each pixel, and it takes time to calculate the address. Furthermore, for example, if the data for each pixel is represented by a length of 1 byte and the data is transferred in a width of 32 bits, then data for 4 pixels is transferred at a time, so of these 4 pixels, Also, time is required for processing (read-modify-write) for writing only the data of pixels that are actually desired to be accessed into the image memory. That is, the time required to access each pixel in the image memory becomes longer. Therefore, there was a problem in that it was not possible to take advantage of the advantages of high-speed data transfer using the synchronous bus as described above.

FIG. 6 is a diagram showing the timing of transferring vector drawing data to an image memory using a conventional synchronous bus. Due to the long access times mentioned above, data cannot be transferred every clock period.

In the configuration shown in FIG. 4, 100 is the vector drawing data generation section, 200 is an image memory section, 10 is a data synchronous bus, and 30 is an address asynchronous bus.

The data synchronization bus 10 is a bus for transferring vector drawing data of each pixel from the vector drawing data generating section 100 to the image data section 200 in synchronization with a clock.

An address asynchronous bus 30 transfers the address of each pixel from the vector drawing data generation section 100 to the image data section 2.
This is a bus for transferring data without synchronizing with the 00 hex clock.

The vector drawing data generation section 100 includes the data generation section 60
, address generation circuit 70, bus control circuits 11 and 31
, length counters 12 and 32.

The data generating section 60 is a section that generates data for each pixel for performing vector drawing as described above.

The address generation circuit 70 is a part that calculates and generates an address corresponding to a bitmap on the image memory to which data of each pixel is to be transferred.

The length counter 12 counts the number of data transferred via the data synchronization bus. First, the length of vector drawing data is set by the data generation section 60, and thereafter, the length of the vector drawing data is set every time data is transferred. The countdown is performed by the control circuit 1211.

The bus control circuit 11 is a part that performs control for transferring data via the data transfer bus 10, and exchanges control signals with the bus control circuit 13 of the image memory section 200, which will be described later. . When the count of the length counter 12 reaches O, the bus control circuit 11
A data end signal, which will be described later, is output on a control signal line (not shown) of the data synchronous bus 10, and the data synchronous bus 10
to open.

The length counter 32 counts the number of addresses transferred via the address asynchronous bus 30. First, the length of vector drawing data is set by the address generation circuit 70, and thereafter, each time an address is transferred, The bus control circuit 31 counts down.

Bus system? 11 circuit 31 is a part that performs control for transferring addresses via the address asynchronous bus 30,
Control signals are exchanged with a bus control circuit 33 of the image memory section 200, which will be described later. The bus control circuit 31 is configured so that the count of the length counter 32 is O.
When this happens, all processing ends.

The image memory section 200 includes a FIFO memory circuit 20,
It includes an image memory 50, a memory control circuit 40, an address buffer 34, and the bus control circuits 13 and 33.

The FIFO memory circuit 20 corresponds to the data storage means 2 in the configuration shown in FIG. Under the control of 40, the data stored first are read out in order.

The bus control circuit 13 is a part that exchanges control signals with the bus control circuit 11 of the vector drawing data generation section 100 to control data transfer.

If the capacity of the FIFO memory circuit 20 becomes full, the bus control circuit 13 stops data transfer.

The bus control circuit 33 is a part that exchanges control signals with the bus control circuit 31 of the vector drawing data generation section 100 to control address transfer.

The address buffer 34 includes an address asynchronous bus 30.
Temporarily hold the address transferred via .

The image memory 50 is a bitmap compatible memory into which vector drawing data is written.

The memory control circuit 40 corresponds to the stored data reading means 4 in the configuration shown in FIG.
4, among the data stored in the FIFO memory 20, the first input data, that is, the data corresponding to the address, is read out and stored in the location specified by the address in the image memory 50. Write.

The timing of the operation with the above configuration is shown in FIG.

At time t1, the bus control circuit 11 connects the data synchronous bus 1.
When the control of 0 is obtained, the BUZY signal becomes valid (rises). Then, at the next falling edge of the clock, time t2, data starts to be output onto the data synchronization bus 10 in synchronization with the clock. At this time, the bus control circuit 11 makes the data enable signal valid.

The bus control circuit 13 in FIG. 4 detects the above-mentioned valid data enable signal, recognizes data transfer, and transfers the data outputted onto the data synchronous bus 10 to the FIFO memory circuit 20 in synchronization with the above-mentioned clock. input.

On the other hand, the bus system fff! ! The circuit 31 outputs the address corresponding to the first data (0) onto the address asynchronous bus 30 at time t. At this time, the bus control circuit 31
Also enables the address enable signal.

Simultaneously with inputting the above address to the address buffer 34 at time t, the bus control circuit 31 makes the address ACK signal valid. When the bus control circuit 13 detects the valid address ACK signal, it stops outputting the address corresponding to the first data (0) and the valid address enable signal at time t.

At time t, when it is detected that the length counter 12 has transferred data equal to the length of the vector drawing data set, the data end signal is enabled. When the bus control circuit 13 detects the valid data end signal, it stops inputting data to the FIFO memory circuit 20.

At time t7, when all of the vector drawing data has been output, the lotus control circuit 11 stops outputting the valid data enable signal and also stops outputting the valid UZY signal. Stop.

At time t8, the address generation circuit 70 completes calculation of the address for the second data (1) and outputs the address, and the hash control circuit 31 outputs a valid address enable signal.

When the above address is entered into the address buffer 34 at time t, the bus control circuit 31 outputs the address ACK.
Enable the signal. When the bus control circuit 13 detects the valid address ACK signal, it stops outputting the address corresponding to the second data (1) and the valid address enable signal at time tlG.

As described above, according to the configuration shown in FIG. 4, vector drawing data is transferred at high speed in synchronization with the clock by the synchronous bus, regardless of the time required to generate an address or the processing time at the transfer destination. When the transfer of data of a predetermined length is completed, the synchronous bus that transferred the data is released and can be used by other devices connected to the synchronous bus. Therefore, the synchronous bus can be used effectively.

The configuration shown in FIG. 4 described above shows an example of the first embodiment of the present invention.

Regarding the embodiment of the second embodiment of the present invention described above,
In the configuration shown in FIG. 4, the address buffer 34 is replaced with a FIFO memory circuit, the FIFO memory circuit 20 is replaced with a data buffer circuit, and the roles of the bus control circuits 11 and 13 described above and the bus control circuit are This is realized by replacing the roles of 31 and 33, respectively, replacing the data synchronous bus 10 with an asynchronous bus, and replacing the address asynchronous bus 30 with a synchronous bus.

In this way, the address of the vector drawing data can be transferred at high speed in synchronization with the clock by the synchronous bus, regardless of the time required to generate the data or the processing time at the transfer destination. When the transfer of the address corresponding to the data of a predetermined length is completed, the synchronous bus to which the address was transferred is released and can be used by other devices connected to the synchronous bus. Therefore, the synchronous bus can be used effectively.

Further, regarding the embodiment of the third form of the present invention described above,
In the configuration shown in FIG. 4, for example, in the case where the memory control circuit 40 is specified to perform special processing that requires processing time on the transferred address or data, , replace the address buffer 34 with a FIFO memory circuit, and use the bus system described above. This is realized by replacing the 21 circuits 31 and 33 with ones that play the same role as the bus control circuits 11 and 13, and further replacing the address asynchronous bus 30 with a synchronous bus.

In this way, the address of the vector drawing data will be
Regardless of the time required to generate data or the processing time at the transfer destination, data is transferred at high speed in synchronization with a clock using a synchronous bus. When the transfer of the address corresponding to the data of a predetermined length is completed, the synchronous bus to which the address was transferred is released and can be used by other devices connected to the synchronous bus. Further, vector drawing data is transferred at high speed in synchronization with a clock by a synchronous bus, regardless of the time required to generate an address or the processing time at a transfer destination. When the transfer of data of a predetermined length is completed, the synchronous lotus to which the data was transferred is released and can be used by other devices connected to the synchronous lotus. Therefore, each of these synchronous buses can be used effectively.

〔Effect of the invention〕

According to the present invention, there is provided a data transfer device that efficiently utilizes a bus for transferring data or addresses when there is a large difference between the time required to generate data or addresses and the actual data transfer interval. be able to.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram of the first embodiment of the present invention, FIG. 2 is a basic configuration diagram of the second embodiment of the invention, and FIG. 3 is a basic configuration diagram of the second embodiment of the invention.
4 is a configuration diagram of an embodiment of the first embodiment of the present invention, FIG. 5 is a timing diagram of the configuration of FIG. 4,
FIG. 6 is a timing diagram of conventional vector drawing data transfer. [Description of symbols] 1... Data high speed transfer means, 2... Data storage means, 3... Address transfer means, 4... Accumulated data reading means, 5... Address high speed transfer means, 6. ...Address storage means, 7.Data transfer means, 8.Stored address reading means, 9.Stored address/data processing means, 10.Data synchronization bus, 11.13.31.33. ...Bus control circuit, 12.3
2... Length counter, 20... FIFO memory circuit, 30... Address asynchronous bus, 34... Address buffer, 40... Memory control circuit, 50... Image memory, 60. ...Data generation section, 70...Address generation circuit, 100...Vector drawing data generation section, 200...
Image memory section.

Claims (1)

[Claims] 1. High-speed data transfer means (1) for transferring data at high speed
and a data storage means (2) for storing the transferred data.
and address transfer means (3) for transferring the address of the data transfer destination; and among the data accumulated in the data accumulation means (2),
A data transfer device comprising: stored data reading means (4) for reading data corresponding to the transferred address. 2. Address high-speed transfer means (
5) and address storage means (
6); a data transfer means (7) for transferring data corresponding to the address; and a storage address readout for reading out an address corresponding to the transferred data from among the addresses stored in the address storage means (7). A data transfer device comprising means (8). 3. High-speed data transfer means for transferring data at high speed (1)
and high-speed address transfer means for transferring addresses at high speed (5)
and a data storage means (2) for storing the transferred data.
and address storage means for storing the transferred addresses (
6), and stored address/data processing means (9) for reading addresses and data from the address storage means (6) and the data storage means (2) in the order in which they were stored first and performing predetermined processing. A data transfer device comprising: