JPH01208081A - Plural-pictures displaying processor - Google Patents

Abstract

PURPOSE:To obtain a video signal of PIP(Picture In Picture) in which a direct current level is coincident by adding the bias of the potential of the prescribed period of a first video signal after the direct current component of a second video signal is once removed. CONSTITUTION:A second video signal (a) from a terminal 5 is inputted through a synchronizing signal detecting circuit 6 to an A/D converting circuit 8, converted by a clock (b) from a writing side signal generating circuit 7 and written to a memory 9. A first video signal (g) from a terminal 1 is inputted through a synchronizing signal detecting circuit 2 to a switching circuit 4 and a direct current reproducing circuit 11. At the circuit 1, while a pulse (h) is a high potential, a switch SW361 is turned on and the signal (g) is added to a capacitor C371. For a signal (e), a direct current is removed by a C372, the C372 is charged up to the emitter potential of a transistor TR38, during the period except it, the SW362 is turned off and the signal without the direct current component for the emitter potential of a TR38 is superimposed. Consequently, the direct current level of respective first and second video signals can be made coincident.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention inserts a plurality of different pictures into one picture (Picture In Picture: P
The present invention relates to a multi-screen display processing device [abbreviated as P].

[Conventional technology]

FIG. 4 is a conceptual diagram of PIP, and in the figure, 41 is a video display device, 42 is a first video signal portion, and 43 is a portion into which the second video signal is reduced and inserted.

In this specification, an example will be described in which the second video signal is reduced to 173 in both the vertical and horizontal directions and inserted.

In this case, one out of every three scanning lines is extracted from the unreduced second video signal 51 shown in FIG. By inserting it into the PIP 52 as shown in FIG. 5, it is possible to realize the PIP52.

In FIG. 5, scanning lines (1) to (2) indicate the correspondence between the scanning lines of the second video signal before and after reduction.

FIG. 6 is a block diagram of a conventional multi-screen display processing device. In this FIG. 6, 1 is the first video signal input terminal;
2 is a first synchronization signal detection circuit that detects a synchronization signal of the first video signal; 3a is a conversion circuit of a D/A (digital/analog) converter 10 that converts a read clock of the memory 9 and a digital signal into an analog signal; a readout side signal generation circuit that generates a clock and a switching signal for a switching circuit 4 that switches between the first video signal and the reduced second video signal; 5 is a second video signal input terminal; 6 is a second video signal; This is a second synchronization signal detection circuit that detects a synchronization signal of a signal.

In addition, 7 is A that converts analog signals into digital signals.
/D (digital/analog) A write-side signal generation circuit that generates a conversion clock for the converter 8 and a write clock for the memory 9, 12 is a video signal output terminal, 61 is a capacitor, 62 and 63 are a power supply potential and a ground potential. This is a resistor that divides the potential difference between the two and provides a bias potential.

Next, the operation shown in FIG. 6 will be explained using the timing chart shown in FIG. The second video signal a shown in FIG. 7(a) inputted from the second video signal input terminal 5 is inputted to the second synchronization signal detection circuit 6, where the synchronization signal and the video signal are detected. Among them, the synchronization signal is generated by the write side signal generation circuit 7.
The video signal is input to the A/D converter 8.

FIG. 7(b) output from the write side signal generation circuit 7
The second video signal a is digitized and written into the memory 9 by the clock b shown in FIG.

On the other hand, as shown in FIG.
The first video signal f shown in f) is input to the first synchronization signal detection circuit 2, where the synchronization signal and video signal are detected,
Of these, the synchronizing signal is input to the read-side signal generating circuit 3a, and the video signal is input to the switching circuit 4.

The read side signal generating circuit 3a outputs a read clock of the memory 9 shown in FIG. 7(C), a conversion clock of the D/A converter 10, and a switching control signal to the switching circuit 4 shown in FIG. 7(dl).

By generating the clock C at a fixed position from the synchronization signal of the first video signal at three times the speed of the clock b, the reduced second video signal e is generated as shown in FIG. 7(e). obtain.

After the DC component is removed from the second video signal e by a capacitor 61, a bias potential 1 determined by a resistor 62 and a resistor 63 is added thereto, and the signal is input to the switching circuit 4.

In the switching circuit 4, the switching control signal d causes the second video signal to be output only during the period when the reduced second video signal is being output, and to output the first video signal in other cases. Therefore, at the video signal output terminal 12, the seventh
As shown in the figure (80), the second video signal is reduced and the first
is inserted into the video signal.

[Problem to be solved by the invention]

Since the conventional multi-screen display processing device is configured as described above, the DC level of the second video signal does not follow the fluctuation of the DC level of the first video signal, so the DC level of both signals changes. There was a problem that they did not match.

This invention was made in order to solve the above-mentioned problems, and an object of the present invention is to obtain a multi-screen display processing device in which the DC level of the second video signal matches the DC level of the first video signal. do.

[Means to solve the problem]

The multi-screen display processing device according to the present invention includes a readout side signal generation circuit that detects the DC level of the first video signal for a predetermined period of the first video signal, and is controlled by the output of the readout side signal generation circuit. and a DC reproducing circuit that makes the DC level of the second video signal match the DC level of the first video signal during a period when the second video signal is not inserted into the first video signal.

[Function] The read-out signal generation circuit of the present invention detects the DC level of the first video signal for a predetermined period of the first video signal, and the DC regeneration circuit detects the DC level of the first video signal and the second video signal. In order to match the DC levels of the video signals, after once removing the DC component of the second video signal, a potential bias for a predetermined period of the first video signal is added.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 is a first video signal input terminal, and 2 is a first synchronization signal detection circuit that detects a synchronization signal of the first video signal.

3 is the read clock of the memory 9 and the D/A converter 1
0 conversion clock, a pulse h that becomes a pulse for detecting the DC level of the first video signal, and a pulse that becomes a signal indicating the period in which the reduced second video signal is to be inserted. This is a readout image signal generation circuit that generates d.

Reference numeral 4 denotes a switching circuit which switches and outputs the first video signal and the video signal f whose DC level after reduction matches the DC level of the first video signal using a pulse d.

On the other hand, 5 is a second video signal input terminal, and 6 is a second synchronization signal detection circuit that detects a synchronization signal of the second video signal.

Reference numeral 7 denotes a write image signal generation circuit that generates a clock b which becomes a conversion clock for the A/D converter 8 and a write clock for the memory 9.

Further, 11 is a DC reproducing circuit which obtains a video signal f by using pulses h and pulses d with respect to the output signal e of the D/A converter 10, and 12 is a video signal output terminal.

That is, in this FIG. 1, as is clear even when compared with FIG. 6, a DC regeneration circuit 11 is newly added to the configuration of FIG.
．． 63 is omitted.

This DC regeneration circuit 11 is constructed as shown in FIG. In this Figure 3, 31 to 34 are the first
These are input terminals for the video signal g, the output signal e of the D/A converter 10, the pulse d, and the pulse h, and 35 is an output terminal for the video signal r.

38 is a transistor that operates as an emitter follower, its emitter is grounded via a resistor 39, its collector is connected to the power supply, the base is grounded via a capacitor 371, and the above input terminal is connected via a switch 361. 31.

The emitter of transistor 38 is connected to input terminal 32 via switch 362 and capacitor 372. The switch 361 is made conductive when the pulse h is at a high potential, and the switch 362 is similarly made conductive when the pulse d is at a high potential.

Next, the operation will be explained using the timing diagram of FIG. 2 and FIG. 3. The second video signal a shown in FIG. 2(a) input from the second video signal input terminal 5 is input to the second synchronization signal detection circuit 6, where the synchronization signal and the second video signal a are combined. is detected, the synchronizing signal is input to the write image signal generation circuit 7, and the second video signal a is input to the A/D converter 8.

When the included signal is input to the write image signal generation circuit 7, the lock b is sent from the write image signal generation circuit 7 to the A/D converter 8 and the memory 9 as shown in FIG. be done.

Further, the second video signal a is input to the A/D converter 8,
This second video signal a is digitized by an A/D converter 8 at a clock b, and is written into a memory 9 in accordance with a clock b.

On the other hand, as shown in FIG.
The first video signal g shown in FIG.
The synchronizing signal and the first video signal g are detected there, and the synchronizing signal is inputted to the readout image signal generation circuit 3, and the first video signal ε is inputted to the switching circuit 4 and the DC reproduction circuit. 11.

When a synchronizing signal is input to the readout image signal generation circuit 3, if the pulse h is a pulse that generates only the synchronizing signal portion of the first video signal g, as shown in FIG. The circuit 11 detects the potential VO (shown in FIG. 2(g)) of the first video signal g when the pulse h is generated.

Furthermore, as shown in FIG. 2(C), by generating the clock C from the readout image signal generation circuit 3 at a constant position from the synchronization signal of the first video signal g at a speed three times that of the clock b. As shown in FIG. 2(e), the reduced second video signal e is read out from the second video signal a stored in the memory 9 and inputted to the D/A converter 10, where it is converted into an analog signal. Then, a second video signal e as shown in FIG. 2(e) is supplied to the DC reproduction circuit 11.

Furthermore, by applying the pulse d shown in FIG. 2(d) from the read-side signal generation circuit 3 to the DC regeneration circuit 11,
In this DC reproduction circuit 11, the period when the second video signal e is not inserted into the first video signal g, that is, the period in which the second video signal e is not inserted into the first video signal g,
), processing is performed so that the potential during the period indicated by the arrow becomes vo. This processed signal is designated as signal f, and Fig. 2(f)
Shown below.

The switching circuit 4 switches between the second video signal g and the signal f by the pulse d.
The second video signal shown in FIG. 2(i) is reduced and the signal inserted into the first video signal g is output to the video signal output terminal 12.

Here, the operation of the DC regeneration circuit 11 will be explained in more detail with reference to FIG. During the high potential of the pulse h shown in FIG. 2(c), the switch 361 is turned on and 1. capacitor 371
A first video signal g (see FIG. 2 (darkened)) is applied from the input terminal 31 to the capacitor 371, and the potential of this capacitor 371 is charged and held until it reaches the mark (■) shown in FIG.

On the other hand, the DC component of the second video signal e is removed by the capacitor 372 and is shown by the arrow in FIG. 2(e)! During the period between U+, the switch 362 is turned on by the pulse d, and the capacitor 372 is charged to the emitter potential of the transistor 38 and supplied to the output terminal 35. During other periods, the switch 362 is turned off and the emitter potential of the transistor 38 is Since a signal without a DC component is superimposed on the signal f, a signal f shown in FIG. 2(f) is obtained at the output terminal 35.

In the above embodiment, the DC level of the first video signal is the part of the synchronization signal of the first video signal, but the DC level of the first video signal is the part of the synchronization signal of the first video signal. It may also be a partial, ie blanking level.

Further, in the above embodiment, a case has been described in which the second video signal is reduced and inserted into the first video signal, but the present invention is not limited to this, and the second video signal is not reduced or is enlarged. The present invention can also be applied to cases where the second video signal is inserted into the first video signal.

〔Effect of the invention〕

According to the present invention, as shown in FIG. Since the DC level of the first video signal and the DC level of the second video signal are configured to match, P
An IF video signal can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a multi-screen display processing device according to an embodiment of the present invention, Fig. 2 is a timing diagram for explaining the operation of the above embodiment, and Fig. 3 is a diagram of a DC regeneration circuit in the above embodiment. A circuit diagram showing a specific configuration, Fig. 4 2 is P
A conceptual diagram of IF, Fig. 5 is an explanatory diagram showing the correspondence of scanning lines of video signals before and after reduction, Fig. 6 is a block diagram showing a conventional multi-screen display processing device, Fig. 7 is a conventional multi-screen display FIG. 3 is a timing chart for explaining the operation of the processing device. 3...Reading side signal generation circuit, 4...Switching circuit,
11...DC regeneration circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] In a signal processing device that inserts one or more second video signals into a first video signal, a readout side signal generation means for detecting the DC level of the first video signal, and an output of the readout side signal generation means. After once removing the DC component of the second video signal based on the above, a potential bias for a predetermined period of the first video signal is added to change the DC level of the first video signal and the second video signal. a DC reproducing circuit that regenerates the second video signal using direct current by matching the DC levels; and a DC reproducing circuit that regenerates the second video signal with DC levels, and switches the first video signal and the output of the DC reproducing circuit to convert the first video signal into the second video signal. A multi-screen display processing device characterized by comprising a switching circuit for inserting a signal.