JPH0120586B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clamp circuit for television signals, and particularly a feedback circuit for restoring a television video signal whose polarity has been inverted using a pseudo-random code (abbreviated as PN code) or the like in units of horizontal scanning periods and regenerating the DC component. This invention relates to a compression type television signal clamp circuit.

In order to equalize the spectrum of frequency modulated waves when transmitting television video signals using frequency modulation methods using microwaves, etc., or for the purpose of secrecy in pay television etc., according to PN codes determined by certain standards, The polarity of the video signal is inverted and transmitted in units of horizontal scanning lines. It goes without saying that the conventional feedback compression type clamp circuit cannot be used as is for signals in which the polarity of the signal including the horizontal synchronization signal is not constant for each horizontal scanning line, but even if the polarity is reversed, Even when applied to restored video signals, there is a problem in that low frequency fluctuation components cannot be removed and complete DC component reproduction cannot be performed, as will be described later.

An object of the present invention is to provide a television signal clamp circuit that restores the above-mentioned polarity-inverted video signal and reproduces the direct current component including the low frequency fluctuation component, thereby making it possible to reproduce the correct video signal. .

The television signal clamp circuit of the present invention amplifies a video input signal whose polarity has been inverted according to a predetermined code pattern using a horizontal scanning period as a unit, and controls a DC voltage component by a feedback voltage.
a differential amplifier, an inverting and non-inverting amplifier connected in parallel to the output of the first differential amplifier, and an output terminal whose output signal is switched by a switching control signal. a first switch connected to the inverting and non-inverting amplifiers, and a first switch that maintains the peak value or pedestal level of the synchronizing pulses of the same polarity of the output signals of the inverting and non-inverting amplifiers, respectively;
and a second sample and hold circuit, a second differential amplifier that amplifies the difference between the output voltages of the first and second sample and hold circuits, and a second differential amplifier that is connected to the output of the second differential amplifier and that amplifies the high frequency component. a low-pass filter that removes and generates the feedback voltage; a sync signal separation circuit that separates a sync signal component from the video signal and generates a sampling sync pulse for the sample-and-hold circuit; and a sync signal separation circuit that switches the output of the sync signal separation circuit. a second switch that switches and connects to the first or second sample and hold circuit according to a control signal;
and a control circuit that generates the switching control signal corresponding to the predetermined code pattern used to invert the polarity of the video input signal.

Next, the present invention will be explained in detail with reference to the drawings.

Figure 1 is a block diagram of a conventional feedback compression type clamp circuit, in which the output of a differential amplifier 1 is branched, a slicing type sync signal separation circuit 2 generates a sampling sync pulse for a sample and hold circuit 3, and the sync pulse is By feeding back the peak envelope to the differential amplifier 1 via the low-pass filter 4, the peak value of the synchronizing pulse is clamped to a constant value.

FIG. 2 is a block diagram of an embodiment of the present invention, in which an inverted video input signal applied to an input terminal 100 is amplified by a first differential amplifier 5, divided into two, and then divided into two by an inverting amplifier 6. and non-inverting amplifier 7
added to. The output is switched by the first switch 8 in synchronization with the polarity reversal of the video input signal, and the video signal restored to the same polarity is sent to the output terminal 101 via the amplifier 9. The feedback circuit for clamping the synchronization pulse includes a synchronization signal separation circuit 10 similar to that shown in FIG. differential amplifier 13,
It is composed of a low-pass filter 14 and a second switch 15 that switches the sampling synchronization pulse of the synchronization signal separation circuit 10 to the sample hold circuit 11 or 12. It is switched in synchronization with the polarity reversal of the signal. Control circuit 16 is the same as the transmitter side
It includes a PN code generator, a horizontal synchronization signal oscillator of, for example, 15.734 KHz, and a vertical synchronization signal separation circuit, and is configured to generate a switching control signal similar to that on the transmitting side in synchronization with the vertical synchronization signal.

When the video input signal contains low frequency fluctuations, the input to the differential amplifier 5 changes as shown in Figure 3a, and the synchronization pulse envelope is as shown by the solid line A,
Denoted by A′. Feedback voltage 103 of differential amplifier 5
When constant, the inverting amplifier 6 and the non-inverting amplifier 7
The synchronized pulse envelope of the output becomes the broken lines B, B' and the solid lines C, C' in Figure 3b, and the output waveform of the switch 8 restored by inverting the + polarity part in Figure 3a is as shown in Figure 3b. becomes. When this is controlled by a feedback circuit having one sample and hold circuit similar to the conventional circuit shown in FIG. 1, the detected synchronous pulse envelope becomes as shown by the thick solid line D and broken line D' in FIG. The solid line portion D is in phase with the low frequency fluctuation included in the input, that is, A and A' in Fig. 3a,
The broken line portion D' has the opposite phase to A and A'. When this is applied to the differential amplifier 5, the output waveform of the switch 8 becomes as shown in FIG. shading occurs, resulting in instability. In order to eliminate this drawback, the sign of the antiphase component D' may be inverted. In the embodiment of the invention shown in FIG.
The sampling synchronization pulses of the sample and hold circuits 11 and 12 are switched by the switch 15 to the switch 8.
By switching in synchronization with the third
By generating the envelopes shown at B and C in FIG. 2B and determining the difference between the two using the differential amplifier 13, a feedback voltage with inverted polarity can be obtained. Therefore, stable negative feedback is performed, all synchronization pulse peak values are clamped to the same value, and a correct video signal is restored. The case where the video input signal contains a low frequency component has been explained above, but the same applies to the case where the video input signal contains a DC component instead of a low frequency component. It is not possible to perform control to align the peak values of the synchronization pulses. In the circuit of the present invention, various fluctuation factors such as fluctuations in the DC setting level of inverting and non-inverting amplifiers, amplitude fluctuations and DC component fluctuations of the input signal, and differences in the inversion reference level between the transmitting side and the receiving side can be avoided. ,
A clamping operation is always performed to align all synchronization pulse peak values to the same value, and a correct video signal is restored.

In the above-described embodiment, the first switch 8 is provided on the output side of the inverting amplifier 6 and the non-inverting amplifier 7, but it is also possible to provide a switch on the input side and use an adder circuit on the output side. , the amplifier 9 provided after the switch 8 may be omitted. Furthermore, although it has been explained that the control circuit 16 includes the same PN code generator and horizontal synchronization signal oscillator as the transmitting side and generates the same inversion switching control signal as the transmitting side, it does not include the PN code generator and can perform horizontal synchronization of the input signal. It is also possible to reproduce the inversion switching control signal by determining whether the pulse is inverted or non-inverted. Furthermore, sample hold circuit 1
Although the signal inputs 1 and 12 are branched from the output side of the switch 8, they may be configured to branch from the outputs of the inverting amplifier 6 and the non-inverting amplifier 7, respectively, and the synchronizing signal separation circuit 10 also has the same circuit configuration. Although it is more complicated, it is also possible to branch from the input side of the switch 8. It is clear that if the sample and hold circuit samples and holds the level of the pedestal section instead of the peak value of the synchronous pulse, it is possible to control the pedestal level to the same level, and the gain of the inverting/non-inverting amplifier can be It has the characteristic that even if there is a difference, there is little deterioration of the image.

As described above in detail, the television signal clamp circuit of the present invention receives and restores a television video signal that includes a horizontal synchronizing pulse and whose polarity is inverted according to an arbitrary predetermined code pattern in units of horizontal scanning lines. However, it has the effect of being able to reproduce a correct video signal by removing direct current and low frequency fluctuations, and the purpose of spectral uniformity or concealment can be achieved without affecting the quality of the reproduced image.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional example of a feedback compression type clamp circuit, FIG. 2 is a block diagram of an embodiment of the present invention, and FIGS. 3a to 3d are waveform diagrams for explaining the operation of FIG. 1, 5, 13... differential amplifier, 2, 10... synchronous signal separation circuit, 3, 11, 12... sample hold circuit, 4, 14... low pass filter, 6... inverting amplifier, 7, 9... non-inverting amplifier, 8, 15...Switcher,
16...Control circuit.

Claims (1)

[Claims] 1. A first differential amplifier that amplifies a video input signal whose polarity has been inverted according to a predetermined code pattern using a horizontal scanning period as a unit, and whose DC voltage component is controlled by a feedback voltage; an inverting and non-inverting amplifier connected in parallel to the output of the dynamic amplifier; a first switch that switches the output signal of either the inverting or non-inverting amplifier by a switching control signal and connects it to the output terminal; first and second sample-and-hold circuits that hold peak values or pedestal levels of synchronizing pulses of the same polarity of the output signals of the inverting and non-inverting amplifiers, respectively;
a second differential amplifier that amplifies the difference between the output voltages of the first and second sample and hold circuits; and a second differential amplifier that is connected to the output of the second differential amplifier and removes high frequency components to generate the feedback voltage. low-pass filter and
a synchronization signal separation circuit that separates a synchronization signal component from a video signal and generates a sampling synchronization pulse for the sample-and-hold circuit;
and a control circuit that generates the switching control signal corresponding to the predetermined code pattern used for polarity inversion of the video input signal. Features a TV signal clamp circuit.