JP2597650B2 - Clamp circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a clamp circuit for a television receiver.

[Conventional technology]

FIG. 5 (a) shows an example of a waveform of a television signal by the positive-polarity synchronization method in which a horizontal synchronization signal is added with the same polarity as the image signal, and FIG. 5 (c) is an enlarged view of the horizontal synchronization signal portion. Such a horizontal synchronization signal insertion method has already been proposed in the invention "Horizontal synchronization signal insertion method" disclosed in Japanese Patent Application Laid-Open No. 60-163577, for example. According to this method, it is possible to prevent the dynamic range of the image signal processing system from being narrowed due to the synchronization loss, and to perform the phase lock with high accuracy on the receiving side without increasing the period of occupying the image information of the synchronization signal due to the insertion of the burst signal. can do. FIG. 5B is an example of a frame synchronization signal waveform in the same system.

By the way, in order to separate and detect a synchronization signal from a video signal by such a positive electrode synchronization method, it is necessary to accurately perform DC reproduction clamping of an input signal.

For this reason, in the above method, as shown in FIG. 6, the median value (the value to be clamped) of the signal is
Generally, a clamp level period is inserted. FIG. 2B is an enlarged view of the clamp level period and the frame synchronization signal period shown in FIG.

FIG. 7 is a block diagram showing a configuration of a clamp circuit generally considered for this positive electrode synchronization method. In the figure, 1 is an input terminal of a video signal, 2 is a video signal 10
1 is a coupling capacitor, 3 is an adder to which the output signal 102 of the coupling capacitor is inputted, 4 is a first switch circuit to which the output 103 of the adder 3 is inputted, 5 is a reference voltage generating circuit, 6 is an output 10 of the reference voltage generating circuit 5
A subtracter for subtracting the output 104 of the switch circuit 4 from 5 is a mean value amplifying circuit to which the output 106 of the subtractor 6 is connected.

Reference numeral 8 denotes a second switch circuit which is connected so that the output 107 of the average value amplification circuit 7 is input and the output signal 108 is added to the output 102 of the coupling capacitor 2 by the adder 3. Is an A / D converter to which the output 103 of the adder 3 is input, and 10 is the most significant bit (hereinafter, referred to as MSB) signal 110 of the output video signal data 109 of the A / D converter 9.
Is an HD synchronization internal pulse generation circuit to which the output data 109 of the A / D converter 9 and the detection frame signal 111 from the frame synchronization detection circuit 10 are input.

12 is an inversion circuit for inverting the clamp level detection pulse 115 from the HD synchronization internal pulse generation circuit 11, and 13 is an input to the output 116 of the inversion circuit 12 and the frame synchronization determination signal 112 from the frame synchronization detection circuit 10. This is a NAND circuit. The output 117 of the NAND circuit 13 is connected to the switch circuit 4
Is connected to the control terminal.

Then, 113 of the internal clocks 113 and 114 generated by the HD synchronous internal pulse generation circuit 11 are supplied to the A / D converter 9 as a resampling clock.
The HD clamp pulse 118 generated by the HD synchronous internal pulse generation circuit 11 is input to the control terminal of the switch circuit 8. The video signal data 109 and the internal clock 114 synchronized with the video signal data 109 are supplied to a digital signal processing circuit at the next stage.

Next, the operation will be described. The video signal input 101 applied to the input terminal 1 is connected to the adder 3 via the coupling capacitor 2.
AC coupled. Therefore, the output 103 of the adder 3 is A / D
It is not always within the dynamic range in which the converter 9 can convert. In such a state, the frame synchronization detection circuit 10
, The output 117 of the NAND circuit 13 becomes “H”, and the switch circuit 4 is closed. As a result, the video signal 103 is guided to the subtractor 6 via the switch circuit 4 and is subtracted from the output 105 of the reference voltage generation circuit 5 to obtain a difference signal 106. The reference voltage generation circuit 5
Is set to a voltage to be clamped within the dynamic range of the A / D converter 9.

The difference signal 106 from the reference voltage is input to the average value amplifying circuit 7, after which unnecessary high frequency components are removed, amplified and input to the switch circuit 8. The switch circuit 8 is opened and closed by an HD clamp pulse 118 generated by an HD synchronous internal pulse generation circuit 11. However, when the frame synchronization and the HD synchronization are not in phase lock, the HD waveform position with respect to the input video signal 101 is not determined. Accordingly, the average value of the AC-coupled video signal 102 approaches the potential to be clamped within the dynamic range of the A / D converter 9 by the clamp control signal 108 randomly added to the HD cycle.

As shown in FIG. 5 (b), the frame synchronizing signal is inserted as a pulse having an input signal level of 100%, and if the video signal 103 falls within the dynamic range in which the A / D converter 9 can convert. By the frame synchronization detection circuit 10, the A / D
The output can be easily detected by the frame synchronization detection circuit 10 using only the MSB 110 of the output data of the converter 9. The HD synchronization internal pulse generation circuit 11 is reset by the detected frame synchronization signal 111, and the frame is synchronized with the input signal 101.

When the frame synchronization detection circuit 10 stably detects the frame synchronization signal, the frame synchronization determination signal 11
2 is set to "H", the switch circuit 4 is closed only during the period when the clamp level detection pulse 115 generated by the HD synchronous internal pulse generation circuit 11 is "H", and the voltage during the clamp level period shown in FIG. And control the loop of the clamp circuit. The state of the above operation is shown in FIG.

FIG. 8A shows a state in which the input signal is not within the dynamic range of the A / D converter. The control signal 118 of the SW circuit 8 is an HD periodic pulse generated by the internal pulse generation circuit 11, Here, it is assumed that the SW circuit 8 is closed at “H”, but is asynchronous with respect to the input signal when the frame synchronization signal is not detected.

Next, FIG. 8B shows a state immediately after the detection of the frame synchronization signal. The SW circuit 4 is closed by the control signal 117 so as to sample the level during the clamp level detection period. In this state, HD sync is not locked and
The SW4 control signal 117 and the HD clamp pulse 118 have a phase jitter with respect to the input signal.

FIG. 9C shows a state in which the clamp level period has been drawn into the clamp level of the dynamic range of the A / D converter through the above process. The phase of the SW4 control signal 117 and the HD clamp pulse 118 is determined by the phase synchronization of the HD synchronous internal pulse generation circuit 11 with respect to the input signal, and the shift with respect to the clamp level during the clamp level period is set to the HD level.
Addition is performed by the adder 3 during the synchronization period (the waveform average value is the same as the clamp level period), and the clamp operation can be stably performed.

[Problems to be solved by the invention]

Since the conventional clamp circuit is configured as described above, when the HD phase is not locked to the input signal such as when the power is turned on, the feedback clamp addition voltage is not always added correctly during the HD period. However, there is a problem that a long time is required for the clamp operation or the clamp operation becomes difficult depending on the input signal waveform.

The present invention has been made in order to solve the above-described problems of the related art, and it is possible to quickly detect a frame synchronization signal even in a state where the HD phase is not locked, and perform a stable clamping operation later. An object of the present invention is to obtain a clamp circuit that can be used.

[Means for solving the problem]

The clamp circuit according to the present invention forms a loop for feeding back the average value of the input signal over the entire period at the time when the frame synchronization signal cannot be detected, such as when the power is turned on, and then detects the frame synchronization signal and performs HD phase lock. At the time when it is not, the clamp which feeds back the level such as the clamp level period and HD period during the same period is performed, and then when the HD phase lock is completed, the clamp which detects the level of the clamp level period and feeds it back to the HD period It is configured to switch.

[Action]

According to the present invention, since the clamp operation of the input signal synchronized with the positive electrode is divided into three stages and the detection operation of each detection signal is completed before the next operation, the present invention provides a stable operation. And reliable operation becomes possible.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a clamp circuit according to one embodiment of the present invention. In the figure, reference numerals 1 to 11 are the same as those in the related art. 14 is a clamp pulse control circuit, and the frame synchronization detection circuit
10, the frame synchronization determination signal 112, the HD synchronization determination signal 120 from the HD synchronization internal pulse generation circuit 11, the clamp level detection pulse 115, and the HD clamp pulse 118 are supplied. It is connected to the circuit 8 as control signals 117 and 120, respectively.

FIG. 2 is a circuit diagram showing the configuration of the clamp pulse control circuit 14. Reference numeral 15 denotes a NOT circuit to which the HD synchronization determination signal 120 is input, and reference numeral 16 denotes an input of the NOT circuit 15 and a clamp level detection pulse 115. AND circuit 17 is the NOT circuit 1
AND with which the output of 5 and the HD clamp pulse 118 are input
The circuit 18 is connected to the clamp level detection pulse 115 and the AND
The NOR circuit to which the output of the circuit 17 is input, 19 is a NAND circuit to which the frame synchronization determination signal 112 and the output of the NOR circuit 18 are input, and 20 is the HD clamp pulse 118 and the output of the AND circuit 16. The NOR circuit 21 receives the frame synchronization determination signal 112 and the output of the NOR circuit 20.
ND circuit. The outputs of the NAND circuits 19 and 21 are SW4
The control pulse 117 and the SW8 control pulse 119 are connected to the control terminals of the SW circuits 4 and 8, respectively.

Next, the operation will be described. The basic operation in FIG. 1 is the same as that of the conventional circuit described above, except that a clamp pulse control circuit 14 for controlling the SW circuits 4 and 8 is added. The frame synchronization detection circuit 10 outputs “L” as the frame synchronization determination signal 112 during a period in which frame synchronization is not established, such as when power is turned on, as indicated by A in FIG. At this time, the clamp pulse control circuit 14 outputs the SW4 control pulse 117 and the SW8
The control pulses are both set to “H”, and the SW circuits 4 and 8 are both closed. Thus, the output of the adder 3 is controlled so that the average value of the difference between the input signal level and the reference voltage 105 obtained by the reference voltage generating circuit 5 becomes zero. Therefore, it is not known at which potential in the dynamic range of the A / D converter 9 an arbitrary video signal portion of the waveform is located. However, a frame synchronization signal or the like whose waveform average is close to zero is an A signal required for frame synchronization pulse detection. It can be converged to the position where the median of the / D conversion dynamic range is cut off. Thus, frame synchronization is performed, and the frame synchronization detection circuit 10 sets the frame synchronization determination signal 112 to “H”. The operation in FIG. 2 is shown in FIG.

When the frame synchronization determination signal 112 becomes “H”, the third
In the state of frame synchronization and HD asynchronous shown as B in the figure, the SW circuits 4 and 8 are both controlled so as to close the clamp level detection period and the HD period. As a result, the output 103 of the adder 3 becomes the level of the reference voltage 1 during this period.
Clamped to be equal to 05. The output 109 of the A / D converter 9 obtained by this is sufficiently stable.
The HD synchronization internal pulse generation circuit 11 can perform HD synchronization, and sets the HD synchronization determination signal 120 to “H” upon completion of lock.

In the above operation, the clamp by the method of comparing and adding every HD cycle is affected by the jitter of the HD clamp pulse, the distortion of the HD waveform due to the transmission characteristics, and the like, and is weak to disturbance even if it is constantly stable. For this reason, after the HD synchronization shown as C in FIG. 3, the control is switched to the control in which the SW circuit 4 is closed only for the period of the clamp level detection pulse 115, and the clamp level transmitted in the vertical synchronization (hereinafter referred to as VD) cycle of the input video signal. It is a clamp by a method of adding the difference from the reference voltage 105 during the period to the HD clamp pulse period without updating until the next clamp level.

With the above operation, the clamp operation from the frame asynchronous state can be reliably performed.

FIG. 4 shows the A / D at the time of the circuit operation of the embodiment of the present invention.
The waveforms of the input signal 103, the SW4 control signal, and the SW8 control signals 117 and 119 are shown in the figure, (a) showing the operation when the frame is asynchronous, (b) showing the operation when the frame is synchronous and HD asynchronous, and (c) in the same figure. Shows the operation after HD synchronization.

In the above-described embodiment, the time constant of the average value filter in each operation mode in each synchronization state has been described as a value that can be compatible with each mode without changing, but this time constant is switched to a value suitable for each mode. Thereby, a further improvement effect can be obtained.

〔The invention's effect〕

As described above, according to the clamp circuit according to the present invention, the clamp operation of the input signal synchronized with the positive electrode is divided into three stages, and the detection operation is completed and the next operation is performed. There is an effect that the device operates reliably and a stable device can be obtained.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a clamp circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing a configuration of a clamp pulse control circuit according to an embodiment of the present invention, and FIG. FIG. 4 is a waveform diagram showing the operation of the clamp circuit according to one embodiment of the present invention. FIG. 5 is an explanatory diagram showing an example of a television signal and its synchronizing signal waveform according to the positive electrode synchronization system. FIG. 7 is an explanatory diagram showing an example of a television signal according to the positive electrode synchronization system, FIG. 7 is a configuration diagram showing a generally considered clamp circuit, and FIG. 8 is a waveform diagram showing the operation of a conventional clamp circuit. In the figure, 1 is an input terminal, 2 is a capacitor, 3 is an adder, 4 and 8 are first and second switch circuits, 5 is a reference voltage generating circuit, 6 is a subtractor, 7 is an average circuit, 9 is A / D conversion circuit, 10 is frame synchronization detection circuit, 11 is HD synchronization internal pulse generation circuit, 12 is NOT circuit, 13 is NAND circuit, 14 is clamp pulse control circuit, 101 is input signal, 103 is A / D conversion Input signal, 105 is a reference voltage generation circuit, 108 is a clamp addition voltage, 109 is output data, 110 is the most significant bit signal of output data, 112 is a frame synchronization determination signal, 113 is a clock pulse, 114 is various synchronization signals, 115 Is a clamp level detection pulse (clamp level detection position pulse), 117 is a SW4 control pulse, 118 is an HD clamp pulse (horizontal synchronization signal), and 119 is
SW8 control pulse, 120 is an HD synchronization determination signal. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. A feedback type in which a television signal of a positive polarity synchronization method is input, a synchronization signal included in the input signal is detected, and a DC component included in the input signal is detected using various pulses synchronized in phase with the input signal. A clamp circuit, an adder that adds a clamp voltage to an input signal, a first switch circuit that samples an output voltage of the adder, a reference voltage generation circuit that supplies a reference voltage to be clamped, A subtractor for subtracting the output voltage of the switch circuit from the reference voltage, an average circuit for smoothing the output of the subtractor, and a second circuit connected between the output of the average circuit and the addition input of the adder. 2, a horizontal synchronization signal, a clamp level detection position pulse, a signal indicating that a frame synchronization signal has been detected, and a horizontal synchronization signal with respect to the input signal. A signal indicating that the phase is locked is input. When the frames are not synchronized, control is performed so that the first and second switch circuits are both closed, and then the frames are synchronized and the horizontal synchronization is phase locked. When there is no control, both the first and second switch circuits perform control so as to close the clamp level detection position and the period of the horizontal synchronization signal, and when the horizontal synchronization is phase-locked, the first switch circuit switches the first switch circuit during the clamp level detection period. And a clamp pulse control circuit for controlling the second switch circuit to be closed during the period of the horizontal synchronization signal.