JPH01201887A - Rotary head type recording device - Google Patents

Abstract

PURPOSE:To record/reproduce a time record, which is not synchronized with a rotary head, to a recording track by providing a time code reading circuit, a latch circuit, which latches a counter resetted by a synchronization signal and time data, etc. CONSTITUTION:When a segment synchronizing signal SGSYNC is supplied to a terminal 37, the counted values of counters 35 and 39 are successively latched by latch circuits 37 and 41, and data PHN having the phase information between bit number data BTN and a bit clock BTNCK are obtained. Since the output of the counter 39 is supplied to a latch circuit 43, and the bit clock BTNCK is supplied and latched to the clock terminal of the circuit 43, data PHMAX having the number of clocks PHNCK between the BTNCKs are obtained from the circuit 43. Based on time code data TCD supplied from a reading circuit 31, the BTN, PHN and PHMAX supplied from the latch circuits 36, 41 and 43, the sub-code encoder of an R-DAT forms a time code TC*, and it is recorded on the data area of a sub-code block as the packed data.

Description

[Detailed description of the invention]

The present invention will be explained in the following order. A. Field of industrial application B. Overview of the invention C. Prior art D. Problem to be solved by the invention E. Means for solving the problem (Fig. 1) F. Effect G. Example G1. Description of recording device G2. Description of reproducing device Effects of the Invention A: Industrial Application Field The present invention relates to a rotary head type recording device. B. Summary of the Invention The present invention enables a rotary head type recording device to record a time code that is not synchronized with the rotation of the rotary head on the recording track, thereby achieving high speed recording even when the rotation period of the rotary head is special. This makes it possible to edit with precision and eliminates the need for a dedicated time code track. C Conventional technology Conventional rotating head type VTR (video tape recorder)
For editing convenience, the time code, e.g. SM
A system has been proposed in which the PTE time code is recorded in the longitudinal direction of the tape. In this case, the rotation speed of the VTR is 30
While it is rotation, S! , l P T E The time code is also 307, and there is a one-to-one correspondence between the data segment unit and the time code value. Figure 6 shows this S! , l P T E The structure of the time code is shown. S! JPTE time code is 1
The frame is 80 bits (bit number 0 to 79), so the bit frequency is 2.4k)! Of these 80 bits, 32 bits are used as a time code, 32 bits are used as empty bits for the user, and 16 bits are used as a sync word. A 32-bit time code consists of a frame code, a second code, a minute code, and a time code, which indicate what hour, minute, and second frame it is, and each has 4 bits. The data is divided into two parts, and four user bits are inserted between each part. The 16-bit sync word indicates that the tape is running in the forward direction and therefore this SMPTE
Either the time code signal is read out in the direction indicated by arrow F or the tape is running in the opposite direction and therefore this S
The state is such that it is possible to identify whether the MPTE time code signal is read out in the direction indicated by arrow R.
The code signal can be read without error when traveling in any direction. Note that this code signal is a so-called bi-phase signal in which information of "1" and "0" is expressed by a difference in inverted phase as shown in the figure. Further, a rotary head type digital tape recorder (hereinafter referred to as rR-DAT), as shown in the figure, has been proposed. FIG. 7 shows an example. In the same figure, (1) has a diameter of 39 mm and a diameter of 200 Orp.
It is a drum rotated at m. Drum (1) has 18
A pair of magnetic heads (2 people) and (
2B) is attached. 90 on the circumferential surface of the drum (1)
The magnetic tape (3) is wound diagonally at the corner. The magnetic tape (3) is attached to the reel hub (4) of the tape cassette.
A) and (4B), and the capstan (5
) and pinch roller (6), 8.15 (mm/5
The vehicle is made to travel at a speed of ec). The magnetic heads (2A) and (2B) alternately drive the magnetic tape (
3), inclined tracks (7^) and (7B) are formed on the magnetic tape (3) as shown in FIG. Tape width A of magnetic tape (3) is 3.18
'mm. The magnetic gap of one magnetic head (2A) is tilted by +α with respect to the direction perpendicular to the track, and the magnetic gap of the other magnetic head (2B) is tilted by 1α with respect to the direction perpendicular to the track. α is 20"
It is said that These magnetic heads (2A) and (2B)
The angles of the magnetic gap are referred to as +azimuth and -azimuth, respectively. The magnetic heads (2A) and (2B) are alternately selected by a head changeover switch (8), and the recording signal from terminal r of the recording/reproduction switch (9) is sent to the magnetic head via a rotary transformer (not shown). (2A) and (2B), and the reproduction signals of the magnetic heads (2A) and (2B) are taken out to the terminal p of the recording/reproduction switch (9) via a rotary transformer (not shown). The analog audio signal from the input terminal (10) is supplied to the A/D converter (12) via the low-pass filter (11) (sampling frequency: 48kHz, 1
(6-bit linear quantization) into a digital audio signal. The digital audio signal from the A/D converter (12) is supplied to a recording signal processing circuit (13). The recording signal processing circuit (13) performs error correction encoding of the digital audio signal and conversion into a recording data format as described later. In this case, an ID signal (PC
M-ID) is added. In addition, the program number of the signal to be recorded, a subcode such as a time code, and an ID signal (subcode ID) for the subcode are formed by a subcode encoder (not shown), and the terminal
4) is supplied to the recording signal processing circuit (13). From the recording signal processing circuit (13), serial recording data for each track is sent to the magnetic heads (2A) and (2B).
) occurs in synchronization with the rotation of. The recording data is supplied to the changeover switch (8) through the recording amplifier (15) and the terminal r of the recording/reproduction switch (9). The recording data is transferred to the magnetic head (2A) by the cut-off switch (8).
and (2B) alternately. Signals reproduced by the magnetic heads (2A) and (2B) are supplied to a reproduction amplifier (16) through a head changeover switch (8) and a terminal p of a recording/reproduction switch (9). The output signal of the reproducing amplifier (16) is sent to the PLL circuit (
17), and a PLL circuit (17) extracts the tarock synchronized with the reproduced signal. The reproduced signal undergoes processing such as error correction and interpolation in a reproduced signal processing circuit (18), and the reproduced digital audio signal is supplied to a D/A converter (19). A reproduced audio signal from the D/A converter (19) is taken out to an output terminal (21) via a low-pass filter (20). At the same time, the reproduced signal processing circuit (18) separates the subcode and subcode ID and outputs them to the output terminal (22). A subcode decoder is connected to the output terminal (22), and control data etc. are formed from the subcode. Control signals for controlling the head changeover switch (8) and the recording/reproduction changeover switch (9) are generated by a timing control circuit (23). Further, the timing control circuit (23) generates clock signals and timing signals required by each of the recording signal processing circuit (13) and the reproduction signal processing circuit (18). Next, the data structure of this R-DAT will be explained. The entire data recorded on one track is called one segment. FIG. 9A shows the structure of one segment of data recorded by one rotary head. When the unit amount of recording data is one block, one segment contains 196 blocks (7500 μ5ec) of data. A margin (11 blocks) is provided at each end of one segment corresponding to the end of the track. Adjacent to each of this margin are subcode 1 and subcode 2.
is recorded. The two subcodes are the same data and are double recorded. The subcode is a program number and a time code. A PLL run-in section (2 blocks) and a postamble section (1 block) are arranged on both sides of the 8-block recording area of the subcode. Also, there are interblock gaps (3) where data is not recorded.
A pilot signal for the ATF is recorded over five blocks sandwiched between the interblock gaps. A PCM signal subjected to recording processing is recorded in an area of 128 blocks in length, excluding the PLL run-in section of 2 blocks, within an area of 130 blocks in length at the center of one segment. This PCM signal is data corresponding to an audio signal during 172 rotations of the rotary head. The 20 PCM signal consists of a two-channel stereo PCM signal consisting of an L (left) channel and an R (right) channel, and parity data of an error detection/correction code. FIG. 9B shows the data structure of one block of the PCM signal. An 8-bit (1 symbol) block synchronization signal is added to the beginning of one block, followed by an 8-bit PCM-ID.
is added. An 8-bit block address is added next to the PCM-ID. Simple parity error correction encoding processing is performed on the two symbols (Wl and W2) of the PCM-ID and block address,
An 8-bit parity is added next to the block address. As shown in Figure 9, the block address consists of 7 bits excluding the most significant bit (MSB), and by setting this most significant bit to "0", it is indicated that it is a PCM block. FIG. 9C shows the data structure of one block of subcode. It has the same data structure as the PCM block described above. As shown in FIG. 9E, the most significant bit of symbol W2 of the subcode block is set to "1", indicating that it is a subcode block. The lower 4 bits of this symbol W2 are used as a block address, and the 8 bits of symbol W1 and the 3 bits excluding the MSB and block address in symbol W2 are used as a subcode ID. Simple parity error correction encoding processing is performed on the two symbols (Wl and W 2 ) of the subcode block,
8-bit parity is added. The two symbols W1 and W2 of this subcode block are constructed as shown in FIG. That is, the MSB of symbol W2 indicates whether the block is a subcode block or P CM
It is used to identify whether it is a block, and if it is a subcode block, it becomes "l" as shown in the figure. Furthermore, the lower four bits of symbol W2 are a block address, and the contents of the subcode ID differ depending on whether the LSB is "0" or "1". When the LSB of the block address is "0",
The symbol W1 consists of a 4-bit control ID and a 4-bit data ID, and the 3 bits in the symbol W2 excluding the MSB and block address are used as a format ID. When the LSB of the block address is "1", the three bits excluding the MSB and the block address in symbol W1 and symbol W2 indicate the program number. In this case, the program number is represented by a 3-digit BCD code, 3-bit PNO-ID (1) with symbol W2.
is the most significant digit, and the upper 4 bits of symbol W1 are P N O
-, ID (2) is the middle digit, the lower 4 digits) P N
O-LD(3) represents the lowest digit, and the program number is represented from (001) to [799]. In addition,

[000] indicates that the program number is not recorded, and (OAA) indicates that the program number is invalid. Four subcode blocks in which the LSB of the block address is "0" and four subcode blocks in which the LSB is "1" are recorded alternately among the eight blocks in each subcode area. Also, when the data ID is "000 units", it means that there is pack data in the subcode data area,
At that time, the format ID indicates the public publication area. When the format ID is '000 J, it indicates that there is no packed data. Figure 11 shows the pack format. As shown in the figure, it consists of a 4-bit item block and a 60-bit data and parity block. That is, it is composed of 8 symbols PC1 to PC8, the upper 4 bits of the symbol Pct are used as an item block, the symbol PC8 is used as a parity block, and the others are used as data blocks. The 4-bit item block indicates which mode the pack data is in. For example, 1f
ro001” indicates program time mode,
The pack format of this program time mode is shown in FIG. D Problems to be Solved by the Invention In such an R-DAT, for convenience of editing, a time code is used, for example, the SMPTE time code, whereas the SMPTE time code is 307, and data segments and time Since the code values do not have a one-to-one correspondence, it was necessary to record the phase difference between these two signals in order to correctly reproduce the relationship between these two signals during playback. Therefore, the present applicant has previously proposed a method for simultaneously recording both time code data and bit number data by sampling time code bit numbers (for example, 0 to 79) at the edges of segment synchronization signals. In this case, if one frame is made up of 1000 bits, for example, instead of 80 bits, the phase information will become more accurate. A high frequency clock is required. However, for systems such as R-DAT, where devices are manufactured by many manufacturers and range from inexpensive to expensive ones for professional use, it would be convenient if the clock that carries this phase information could be set to any frequency. The present invention takes these points into consideration and enables time codes that are not synchronized with the rotation of a rotary head to be recorded and reproduced well. is supplied with the time code reading circuit (31) to obtain the time code data TCD, and a clock that is reset at one cycle of the time code synchronization signal TC3YNC or a cycle of an integer fraction thereof, and whose cycle is shorter than this reset cycle. A counter (39) that counts PIINCK and this counter (39)
A first latch circuit (41
) and a second latch circuit (43) that latches the maximum value of the counter (39) within the reset period, and at least the first and second latch circuits (41) and The output data of (43) is recorded on the recording track. F Effect In the above configuration, for example, the counter (39) is reset by the bit clock BTNCK. The value of this counter (39) is the segment synchronization signal 5GSYN.
C is latched by the first latch circuit (41), and the bit clock BTNCK is latched by the second latch circuit (43).
latched to. Therefore, bit number data BT
In addition to N, the output data PHN of the first latch circuit (41) that provides phase information between the pit clocks BTNCK is also recorded, making it possible to more accurately reproduce the relationship between the data segment and the time code LTC. Also, the first
In addition to the output data PHN of the latch circuit (41), the output data P of the second latch circuit (43) has information on the number of clocks P)INcK between the pit clocks BTNCK.
If 1. Since I A It becomes possible to always reproduce the relationship correctly. G. Example Hereinafter, an example of the present invention will be described with reference to the drawings. In this example, S! is added to the R-DAT subcode. , I
This is an example of recording and reproducing PTE time codes L and TC. G1 Description of Recording Apparatus FIG. 1 shows a time code recording processing section of a recording apparatus where R=DAT. In the figure, (31) is a time code reading circuit, and the S! , I
PTE Time code LTC is supplied. "Hour""Minute""Second" obtained from this reading circuit (31)
Time code data TCD such as “frame” is available at terminal (3
3) and from this terminal (33) to the R-DAT subcode encoder (not shown in FIG. 7, the terminal (14)
) is connected to ). Further, (34) is a bit clock generator, and the time code synchronization signal TCSYNC is supplied from the reading circuit (31) at one frame period (30 Hz) to this pit clock generator (34). The generator (34) outputs, for example, 160 bit clocks BTNCK per frame. This bit clock BTNCK is supplied to the clock terminal of the counter (35), and the reset terminal R of this counter (35) is supplied with the time code synchronization signal T from the reading circuit (31).
C3YNC is supplied. And this counter (35
) is supplied to a latch circuit (36) consisting of a flip-flop, and the clock terminal of this latch circuit (36) is connected to the R-DAT magnetic heads (2A), (2B) from a terminal (37). 100/3 synchronized with the rotation of
A segment synchronization signal 5GSYNC of Hz is provided. This segment synchronization signal 5GSYNC is, for example, R-
It is formed by dividing the frequency of the DAT master clock. The output data of the latch circuit (36) is supplied to a terminal (38), and from this terminal (38) is supplied to the subcode encoder of the R-DAT as bit number data BTN. Further, the bit clock BTNCK from the pit clock generator (34) is supplied to the reset terminal R of the counter (39), and the bit clock BTNCK is supplied to the clock terminal of this counter (39) from the terminal (40) for each bit clock period. For example, 98 clocks PHNCK are supplied. The output of this counter (39) is the latch circuit (4).
1), and the clock terminal of this latch circuit (41) receives a segment synchronization signal 5GSY from the terminal (37).
NC is supplied. Output data P of the latch circuit (41)
HN is supplied to a terminal (42), and from this terminal (42) is supplied to the R-DAT subcode encoder. In addition, the output of the counter (39) is sent to the latch circuit (43).
A bit clock BTNCK from a bit clock generator (34) is supplied to a clock terminal of this latch circuit (43). And this latch circuit (
43) output data PHM A X is the terminal (44)
from this terminal (44) to the R-DAT subcode encoder. Here, it is assumed that the SMPTE time code LTC is supplied to the terminal (32) at the timing shown in FIG. 2A. In the figure, TCDI, TCD2. ...
. etc. indicate time code data of each frame, and 0 to 159 indicate bit numbers. In this case, the time code synchronization signal TC3 is supplied from the reading circuit (31) to the reset terminal R of the counter (35).
As shown in Figure B, YNC is supplied at the end of each frame, that is, in response to the sync word of the time code LTC. Also, since the number of pit clocks BTNCK supplied to the clock terminal of the counter (35) is 160 per frame, the count value of the counter (35) is 0 to 159 per frame of the time code LTC.
and changes. FIG.
5) shows the count value. Further, the pit clock BTNC is supplied to the reset terminal R of the counter (39), and the counter (39) is supplied with the pit clock BTNC.
Clock P)INc supplied to the clock terminal of 39)
Since K is 98 per one bit clock cycle, the count value of the counter (39) changes from 0 to 97 between pit clocks BTNCK. The second diagram shows the clock PHNCK, and the numerical value attached above it shows the count value of the counter (39). In this state, if the segment synchronization signal 5GSYNC is supplied to the terminal (37) at the timing shown in FIG. 2E, the counter (35) and (
The count value of 39) is the latch circuit (36) and (41)
Data PHN having phase information between bit number data BTN and pit clock BTNCK is obtained. Further, the output of the counter (39) is supplied to the latch circuit (43), and the pit clock BTNCK is supplied to the clock terminal of this latch circuit (43) and latched, so this latch circuit From (43), data P )l ? having clock PI (information on the number of NCKs (r97 in this example)) between pit clocks BTNCK? JAX is obtained. The R-DAT subcode encoder receives time code data TC, which is supplied from the reading circuit (31).
D, latch circuit (36), (41) and (43)
f'-ta BTN, PHN and P) IMA supplied from
A time code TC* is formed based on X, and this time code TC'' is recorded as pack data in the subcode data area of the subcode block at the timing shown in FIG. The format is determined using two types of undefined items, as shown in the pack format in Figure A. In Figure A, flags are bit information (drop frame flag, color frame flag, ).Bit number data BTN
is written to symbol PC3. Then, at 9 minutes and 9 seconds, frames are written to symbols PC4, PC5, PC6, and PC7, respectively. Also, in the same figure, data P HM
AX and PHN are written in symbols PC2 and PC3, respectively. Symbols PC4 to PC7 contain, for example, user bits (binary bits) of time code LTC.
group) is recorded. In addition, PHN in Figure 2 F
I. PHN2. ...etc., each segment synchronization signal 5G
It shows data PHN at the SYNC timing. Description of G2 Reproducing Apparatus FIG. 4 shows the time code reproduction processing section of the R-DAT reproducing apparatus. In the figure, the terminal (51) is supplied with time code data TCD obtained from the R-DAT sub-third decoder (not shown in FIG. 7, but connected to the terminal (22)). Time code data TCD is supplied from a terminal (51) to a time code generation circuit (52). In addition, data P H! obtained from the subcode decoder!
JAX and PHN are terminals (53) and (54) respectively.
) from the terminal (56) to the arithmetic circuit (55).
HJJAX' will be supplied. This PHMAX'
is data having information on the number of clocks PHNCK' in the reproducing device between the pit clocks BTNCK. In this arithmetic circuit (55), data PH
N is converted into data PHN' corresponding to clock PHNCK' in the reproducing device. That is, data P
HN' is the data PHN, PHMAX and P)
Using IMAX', the following formula is used. Data PHN' from this arithmetic circuit (55) is supplied to a counter (57). The clock terminal of this counter (57) is connected to the clock PHNCK from the terminal (58).
' is supplied, and the load terminal is supplied with the terminal (
59) provides a segment synchronization signal 5GSYNC. The output of this counter (57) is supplied to the comparator (60), and the data P)IN supplied from the terminal (56)
It is compared with AX'. The output of the comparator (60) is the output of the counter (57) equal to the data PHMAX.
', the output of the comparator (60) becomes high level "1" and the output of the comparator (60) is connected to the reset terminal R of the counter (57).
is supplied to Further, the output of this comparator (60) is supplied to an AND circuit (61), and this AND circuit (61) is supplied with a clock PHNCK from a terminal (58).
' is supplied. Further, bit number data BTN obtained from the subcode decoder is supplied to a counter (63) from a terminal (62). The output BCK of the AND circuit (61) is supplied to the clock terminal of this counter (63), and the segment synchronization signal 5GSYNC is supplied from the terminal (59) to its load terminal. Second counter (6
The output of 3) is supplied to a decoder (64). The output of this decoder (64) is then sent to the counter (6
3) When the output becomes r159 J, the high level “1” is reached.
”, and the output of this decoder (64) is the counter (6
3) is supplied to the reset terminal R. Further, the output of this decoder (64) is supplied to an AND circuit (65), and this AND circuit (65) is supplied with an output from the AND circuit (65).
The output BCK of 1) is supplied. The output of this AND circuit (65) is then supplied to the generation circuit (52) as the reference synchronization signal RIEFSYNC. Then, the reference synchronization signal REF is output from the generation circuit (52).
From the SYNC timing, time code data TCD
(actually one frame added) based on f:,
SMPTE time code LTC is output,
This SMPTE time code LTC has terminal (66)
is derived. Here, the time code TC is set at the timing shown in FIG. 5A.
” is played, and the subcode decoder outputs the terminal (51),
(53), (54) and (62) include time code data TCD and de9 corresponding to time code TC''.
PHMAX, PHN and l:”7
'-9BTN is supplied. In this state, if the segment synchronization signal 5GSYNC is supplied to the terminal (59) at the timing shown in FIG.
The data 63) are set equal to the data PHN' and the bit number data BTN, respectively. When data PHN' is set in the counter (57), the clock P)INcK' sequentially counts up, and the output of this counter (57) is the data P)! When it matches MAX', the comparator (6o)
A signal of higher level "1" is output. At this time, the counter (57) is reset, and from now on, every time the output of the counter (57) becomes data PHMAX', a signal of a high level "1" is output from the comparator (6o) every 1 bit clock cycle. Output. That is, by setting data PHN' in the counter (57), the clock BCK output from the AND circuit (61) has the same phase as the bit clock BTNCK and corresponds to the pit clock BTNCK. Also, bit number data BTN is displayed in the counter (63).
Once set, the counter (63) is counted up sequentially by the clock BCK, and when the output of this counter (63) reaches r159J, a high level "L" signal is output from the decoder (64). AND circuit (6
5) The reference synchronization signal REFSYNC output from the segment synchronization signal 5GSYNC is as shown in FIG.
In contrast, the time code synchronization signal TCSYNC (Fig. 2B
The phase relationship is similar to (see). Therefore, as shown in Figure 5, the generation circuit (52) generates S! in response to the segment synchronization signal 5GSYNC at the same timing as during recording. 4 PET Time code LTC is generated. As described above, according to this example, in addition to the bit number data BTN, data PHN having phase information between pit clocks BTNCK is also recorded during recording, so this data is used during playback to generate a clock corresponding to the bit clock BTNCK. BCK can be obtained and this clock B
CK is supplied to the counter (63) where the bit number data BTN is set and the reference synchronization signal REFSYN is output.
C is obtained, thereby making it possible to generate a C dedicated to the SMPTE time code. Therefore, the relationship between the time code LTC supplied during recording and the segment synchronization signal 5GSYNC (see Fig. 2 A and E), and the relationship between the time code LTC and the segment synchronization signal 5GSYNC generated during playback (Fig. 5,
B) can be almost completely matched. Further, according to this example, data PHMA having information on the number of clocks PHNC between pit clocks BTNCK
Since X is also recorded, the data PHN is the data PHN' corresponding to the clock PHNCK' in the playback device.
The playback device's clock PHNC
Even if the frequencies of K' and the clock P)INCK of the recording device are different, the relationship between the time code LTC and the data segment can always be correctly reproduced. Therefore, according to this example, since the time code LTC that is not synchronized with the rotation of the rotary head can be recorded and reproduced on the recording track well, even when the rotation of the rotary head is special or when the clock frequency is different between devices. This has the advantage of not only allowing highly accurate editing but also eliminating the need for a track dedicated to time code. Note that in the above embodiment, the bit clock BTNC
Although the example in which K is 160 per frame has been shown, the frequency of this bit clock BTNCK may be an integral multiple of the frame frequency. In the extreme, it may be equal to the frame frequency; in this case, recording of the bit number data BTN is ultimately unnecessary, and the corresponding circuit portion is also unnecessary. In addition, in the above embodiment, the segment synchronization signal 5G
An example of SYNC being 100/3 Hz has been shown, but it is sufficient as long as it has a certain phase relationship with the timing of recording and playback.
Frequencies other than 00/3 Hz are also conceivable. Furthermore, in the above embodiment, the clock PHNCK is
Although an example of 98 bits per 1 bit clock period has been shown, the present invention is not limited to this.
Unlike TNCK, it does not have to be synchronized with time code LTC. Further, in the above embodiment, the data PHN and PHM
AX is 0. 1.2. . . . This is a counted number, but other formats may be used as long as the information corresponds to this. For example, the data PHN may be the count number up to the next edge instead of the count number from the edge. In addition, these data PHN and PHMA
X is not a binary number, but a decimal number (BC
It may be expressed as D). Also, data PHN and P)! Instead of recording MAX separately, the value PH converted into a decimal number as shown in the following equation may be recorded. Naturally, in this way the data PHN, PHMA
When recording in a different X format, the time code reproduction processing section will also be changed accordingly. Further, in the above embodiment, an example of SMPTE time code was shown as the time code in the longitudinal direction, but the same applies to the case where other time codes are used. Furthermore, although the above-mentioned embodiment is an example applied to an R-DAT, the same can be considered in the case of other devices. That is, it is suitable to be applied when the recording frequency (frequency corresponding to the number of rotations of the drum in R-DAT) and the frequency of the time code LTC are not equal. Effects of the invention According to the invention described above, for example, in addition to pit number data, data having phase information between pit crosses is also recorded, making it possible to more accurately reproduce the relationship between data segments and time codes. . Furthermore, since data containing information on the number of clocks between bit-Z clocks is also recorded, even if the clock frequency of the playback device is different from the clock frequency of the recording device, the relationship between the data segment and the time code can be determined. can always be reproduced correctly. Therefore, according to the present invention, time codes that are not synchronized with the rotation of the rotary head can be recorded and reproduced in a good manner on the recording track, so even when the rotation period of the rotary head is special or when the clock frequency is different between devices. This has the advantage of enabling highly accurate editing and eliminating the need for a track dedicated to timecode.

[Brief explanation of the drawing]

1 and 4 are configuration diagrams showing one embodiment of the present invention, FIGS. 2, 3, and 5 are diagrams for explaining the same, and FIG. 6 is a configuration diagram of the SMPTE Quimcode, Figure 7 is R-D
The configuration diagrams of the AT, FIGS. 8 to 12, are diagrams for explaining the AT. (31) is a time code reading circuit, (34) is a pit crotter generator, (35) (39) (57) and (6
3) is a counter, (36) (41) and (43) are latch circuits, (52) is a time code generation circuit, (55)
is an arithmetic circuit, (60) is a comparator, (61) and (65)
is an AND circuit, and (64) is a decoder. Agent Paige Ito
Hidetoshi Matsukuma Recording of Time Code Engineer's Encouragement Whistle 1 Figure Pa/Soft Format Figure 3 R-j) AT11 Thea 7 Years Old - Mat Figure 8 Saf Code Format 1 Figure 1 Figure 10 Back Format Figure 11 Figure 12

Claims (1)

[Scope of Claims] A time code reading circuit that is supplied with a time code and obtains time code data; a first latch circuit that latches the value of this counter at a cycle of one frame of the recording signal or an integral multiple or fraction thereof; a second latch circuit that latches the maximum value, and records at least output data of the first and second latch circuits in addition to the time code data on the recording track. Device.