JPH01194537A - Synchronizing system for time division multiple transmitting device - Google Patents

Abstract

PURPOSE:To shorten the maximum leading-in time of multi-frame synchronization by respectively obtaining the multi-frame synchronization with the respective frames of a received time division multiple signal in a multiple separating device and a termination device. CONSTITUTION:A multiple separating device 5 and a termination device 6 respectively equip a CRV generating circuit, which generate code rule violation(CRV) in the time division multiple signal, and a synchronizing circuit to detect the generating position of the CRV and to execute synchronous leading-in. The CRV generating circuit generates the first CRV in the head bit of a first channel CH1 in each multi-frame and generates the second CRV in the bit corresponding to a frame number to be read from the generating position of this CRV in each frame. Since the leading-in of the multi-frame synchronization can be executed at the receiving time point of the frame, to which the second CRV is added, the multi-frame synchronization can be obtained in two frames, at least, out of one multi-frame. Thus, the maximum leading-in time of the multi- frame can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for synchronizing, for example, a demultiplexing device and a terminal device in a PCM time division multiplex transmission device.

(Prior Art) In recent years, PCM time division multiplex transmission devices have been used, for example, for interoffice communication of telephone and data.

FIG. 3 shows an example of its configuration. This device has a plurality of terminal interfaces 3 to which a plurality of terminal devices 1 are connected via low-speed lines 2, and each transmission signal introduced from these terminal interfaces 3. a multiplex demultiplexing device 5 that time-division multiplexes the signals and decomposes the received time-division multiplexed signals arriving via the high-speed digital line 4;
It is comprised of a network synchronization device 7 that supplies a synchronization clock to the multiplexing device 5 and the termination device 6. Incidentally, the frame structure of the above-mentioned time division multiplexed signal is as shown in FIGS. 4(a) and (b) when the transmission speed is, for example, 8.192 Mbps.
), the PCM signal of <128 channels is
This is adopted as one frame (125 μs), and these eight frames are further time-division multiplexed to form one multiframe.

By the way, this type of device has a multiplex decomposition device 5 and a termination device 6.
It is necessary to synchronize between the two, and conventionally this synchronization is performed as follows. That is, in the multiplexing device 5 and the terminating device 6, a code side violation CRV is generated at the frame synchronization position of the time division multiplexed signal, for example, at the first bit of the first channel CHI of each frame, and at the same time, the code side violation CRV is After inhibiting the generation of CRV at the multi-frame synchronization position, for example, the first bit of the first frame, the signal is output to the terminating device 6 and the multiplexing device 5. These multiplex decomposition device 5 and termination device 6
When the above-mentioned time division multiplexed signal arrives from , the CRV of this signal is detected and the frame synchronization is pulled in at that detection position, and after the frame synchronization in parentheses is pulled in, the CRV generation prohibition position is detected and at this position Perform multiframe synchronization pull-in. Therefore, between the multiplexing device 5 and the terminating device 6, hoom synchronization and multiframe synchronization can be reliably achieved in both the transmitting system and the receiving system.

However, in such a conventional synchronization method, multi-frame synchronization is performed every time no CRV is detected at the first bit position of the first frame.
Pulling in multiframe synchronization requires a time equivalent to one multiframe at most, and as a result, there is a problem in that the synchronization pull-in time becomes extremely long depending on the number of frames in one multiframe.

(Problems to be Solved by the Invention) As described above, the conventional method has the problem that the maximum pull-in time for multi-frame synchronization is long. The present invention aims to provide a synchronization method for time division multiplex transmission equipment that can reduce time.

[Configuration of the Invention (Means for Solving the Problems) The present invention, when configuring one multiframe, generates a first coding rule violation at the frame synchronization position for each frame, and A time division multiplexed signal in which a second coding rule violation occurs at a bit corresponding to a frame number counting from the position of occurrence of the first coding rule violation in at least two of the frames, and configured as described above. When receiving, the first coding rule violation is detected and frame synchronization is established by synchronizing with this detected position, and after the first coding rule violation is detected, the second coding rule violation is detected. The frame number of the frame is determined from the number of bits until the frame is received, and multi-frame synchronization is established.

(Operation) As a result, multi-frame synchronization can be performed at the time of receiving the frame to which the second coding rule violation has been added.
It becomes possible to achieve multiframe synchronization in at least two frames in one multiframe. Therefore, the pull-in time for multi-frame synchronization, which was required for the maximum number of frames, can be reduced by at least one frame, thereby reducing the maximum pull-in time for multi-frames.

(Example) Next, a synchronization method in an embodiment of the present invention will be described.

The present embodiment will be described by taking as an example a case where the time division multiplex transmission apparatus shown in FIG. 3 transmits a time division multiplex signal with the frame structure shown in FIG. 4.

The multiplexing device 5 and the terminating device 6 each include a CRV generation circuit that generates a coding rule violation CRV in the time division multiplexed signal, and a synchronization circuit that detects the position where the CRV is generated and performs synchronization pull-in.

First of all, the CRV generation circuit generates the first channel CHI of each frame for each multi-frame as shown in FIG.
CRV is generated at the first bit of , and for each frame, CRV is generated at the bit corresponding to the frame number counting from the CRV generation position. For example, in the first frame, CR is applied to the first bit and the next bit.
In the second frame, CRV is generated at the first bit and the second bit counting from this first bit.
to occur. For the eighth frame, CRV is generated at the first bit of the eighth frame and the first bit of the second channel CH2, which is the 8th bit counting from the first bit.

On the other hand, as shown in FIG.
A CR that detects V and outputs a detection pulse DP at that point.
It is composed of a V detection circuit 11, a frame counter 12, a CRv count circuit 13, and a multi-frame counter 14.

The frame counter 12 detects the above CRV after the start of synchronization pull-in.
It is reset by the detection pulse DPI first output from the detection circuit 11, and thereafter the above CRV is reset every frame period.
Detection pulses DP output from the detection circuit 11 are counted. The CRV count circuit 13 starts counting bit clocks at the time when the detection pulse DPI is first output from the CRV detection circuit 11.
When the next detection pulse DP is output, the count is stopped and the count value at this time is supplied to the multi-frame counter 14 as a frame number value.

The multi-frame counter 14 sets a multi-frame count value to the count value when it is supplied with the count value from the CRV count circuit 13, and thereafter sets this count value every time a count pulse is generated from the frame counter 12. Increment.

With such a configuration, when the multiplexing device 5 and the terminating device 6 output time-division multiplexed signals to the terminating device 6 and the multiplexing device 5, respectively, each frame is CRV in the first bit of each
At the same time, a CRV is generated at the bit corresponding to the frame number counting from the first bit.

Furthermore, the multiplexing device 5 and the terminating device 6 detect the CRV added to the time-division multiplexed signal by the CRV detection circuit 11 from the time-division multiplexed signal arriving from the terminating device 6 and the multiplexing device 5 at the time of synchronization pull-in. Conduct, first CR
When V is detected, the frame counter 12 is reset at this point to pull in frame synchronization. Also, the first C above
The CRV count circuit 14 starts counting pit clocks from the moment RV is detected, stops counting when the next CRV is detected, and supplies the count value at this time to the multi-frame counter 14 as a frame number value. . Then, the initial value of this multi-frame counter 14 is set to the above frame number value. Thus, multi-frame synchronization is achieved at this point.

Therefore, with the synchronization method of this embodiment, the demultiplexing device 5 and the termination device 6 can perform multiframe synchronization with each frame of the received time division multiplexed signal, and as a result, the pull-in time for multiframe synchronization is reduced. It can be shortened to within one frame period.

Note that the present invention is not limited to the above embodiments. For example, in the above embodiment, the CRV for multi-frame synchronization is generated in all frames in one multi-frame, but it may be generated only in odd-numbered frames or even-numbered frames. It may be made to occur only in 5 frames. In short, CRV for multiframe synchronization may be generated in at least two frames out of each frame in one multiframe. In addition, in the above embodiment, the CRV for multi-frame synchronization is counted from the first bit and used as the frame number bit, but the first frame is also used as the CRV for frame synchronization of the first bit, and from the second frame onwards, the first bit is used as the first bit. The 2nd bit, 3rd bit, etc. of the channel CHI may be set. In addition, the generation position of the CRV for frame synchronization and multiframe synchronization, the configuration of the synchronization circuit, the number of frames in one multiframe, etc. can be modified in various ways without departing from the gist of the present invention.

[Effects of the Invention] As described in detail above, according to the present invention, when configuring one multiframe, the first coding rule violation is generated at the frame synchronization position for each frame, and each frame is A second coding rule violation occurs in the bit corresponding to the frame number counting from the position of occurrence of the first coding rule violation in at least two of the frames, and the time division multiplexed signal configured as described above is generated. Upon reception, the first coding rule violation is detected and frame synchronization is established by synchronizing with this detected position, and after the first coding rule violation is detected, the second coding rule violation is detected. To provide a synchronization method for a time division multiplex transmission device capable of shortening the maximum pull-in time for multiframe synchronization by determining the frame number of the frame from the number of bits until the frame reaches the end of the frame and thereby establishing multiframe synchronization. Can be done.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing the CRV generation position of a synchronous method in an embodiment of the present invention, FIG. 2 is a circuit block diagram of a synchronous circuit to which the same method is applied, and FIG. 3 is a diagram of the configuration of a time division multiplex transmission device. FIG. 4 is a circuit block diagram showing an example, and is a schematic diagram showing a frame structure of a time division multiplexed signal. 1... Terminal device, 2... Low speed line, 3... Terminal interface, 4... High speed digital line, 5... Multiplexing device, 6... Terminating device, 7... Network synchronization Device,
11...CRV detection circuit, 12...Frame counter, 13...CRV count circuit, 14...Multi-frame counter. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] Time division multiplexing transmission involves time division multiplexing the transmission signals output from a terminal for each of multiple channels to form one frame, and further time division multiplexing such multiple frames to configure one multiframe and transmitting it. In the device, the above 1
When configuring a multi-frame, a first coding rule violation is generated at each frame synchronization position for each frame, and at least two of the frames are counted from the position where the first coding rule violation occurs. generates a second coding rule violation in the bit corresponding to the frame number, and when the signal with the multi-frame configuration is received, detects the first coding rule violation and synchronizes with this detected position. Frame synchronization is established, and multi-frame synchronization is established by determining the frame number of the frame from the number of bits from the detection of the first coding rule violation until the second coding rule violation is detected. A synchronization method for a time division multiplex transmission device, characterized by the following.