JPH01184930A - Connection of semiconductor device - Google Patents
Connection of semiconductor deviceInfo
- Publication number
- JPH01184930A JPH01184930A JP1110188A JP1110188A JPH01184930A JP H01184930 A JPH01184930 A JP H01184930A JP 1110188 A JP1110188 A JP 1110188A JP 1110188 A JP1110188 A JP 1110188A JP H01184930 A JPH01184930 A JP H01184930A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- wiring substrate
- alignment mark
- wiring board
- detects
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 abstract 6
- 238000010438 heat treatment Methods 0.000 abstract 1
- 238000001514 detection method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体チップと配線基板との接続方法に関し、
特にフリップチップ技術の位置合わせ方法に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method of connecting a semiconductor chip and a wiring board,
In particular, it relates to alignment methods for flip-chip technology.
従来、半導体チップの接続端子と配線基板の接続端子と
を向き合わせて熱圧着する方法すなわちフリップチップ
技術において位置合わせをするときには、それぞれの配
線パターンを検出するか、半導体チップの外形によって
位置合わせを行っていた。Conventionally, when aligning the connection terminals of a semiconductor chip and the connection terminals of a wiring board using flip-chip technology, in which the connection terminals of the semiconductor chip and the connection terminals of the wiring board face each other and are bonded by thermocompression, it is necessary to detect each wiring pattern or to perform alignment based on the external shape of the semiconductor chip. I was going.
上述した従来の位置合わせ方法の、半導体チップと配線
基板の双方の配線パターンを検出する方法ではそれぞれ
のパターンのある面が反対方向であるので検出装置が複
雑となり、半導体チップの外形を位置合わせに使うのは
精度が落ちるという欠点がある。In the conventional alignment method described above, which detects the wiring patterns on both the semiconductor chip and the wiring board, the surfaces with the respective patterns are in opposite directions, making the detection device complicated and making it difficult to align the outer shape of the semiconductor chip. The disadvantage of using this method is that the accuracy decreases.
本発明の半導体装置の接続方法においては、ウェハチッ
プ状の半導体装置は裏面に目合せパターンを有し、その
目合せパターンと配線基板の配線パターンとを検出する
位置検出部と、その検出結果により半導体チップを移動
させる位置制御部とを有している。In the method for connecting a semiconductor device of the present invention, a wafer chip-shaped semiconductor device has an alignment pattern on the back side, a position detection section detects the alignment pattern and the wiring pattern of the wiring board, and a position detection section detects the alignment pattern and the wiring pattern of the wiring board. and a position control section that moves the semiconductor chip.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例を説明する一部ブロック図で
示す斜視図である。配線基板1には半導体チップ3と接
続する接続端子2が配置され、通常はバンプが形成され
ている。半導体チップ3は表面がこれと向き合うように
下方を向き、裏面には目合せマーク4が作成されている
。位置検出器5は目合せマーク4と接続端子2の位置を
検出して位置制御部6に位置情報を送る。位置制御部6
は半導体チップ3の位置を制御し、配線基板lに圧着す
る。FIG. 1 is a perspective view showing a partial block diagram for explaining one embodiment of the present invention. Connection terminals 2 connected to semiconductor chips 3 are arranged on the wiring board 1, and usually have bumps formed thereon. The semiconductor chip 3 faces downward so that its front surface faces the semiconductor chip 3, and alignment marks 4 are formed on its back surface. The position detector 5 detects the positions of the alignment mark 4 and the connection terminal 2 and sends the position information to the position control section 6. Position control unit 6
controls the position of the semiconductor chip 3 and presses it onto the wiring board l.
最初に位置検出部5が接続端子2の位置を検出し、位置
制御部6に記憶させる。そして、半導体チップ3を吸着
し、目合せマーク4の位置を検出しながら半導体チップ
3の位置を所望の位置に合わせ、配線基板1に圧着し、
加熱して接続する。First, the position detection section 5 detects the position of the connection terminal 2 and causes the position control section 6 to store it. Then, the semiconductor chip 3 is sucked, the position of the semiconductor chip 3 is adjusted to a desired position while detecting the position of the alignment mark 4, and the semiconductor chip 3 is crimped onto the wiring board 1.
Heat and connect.
そして、半導体チップの吸着を終了させ、他に接続する
半導体チップがあれば同様の動作を順次行って配線基板
上に半導体チップを搭載していく。Then, suction of the semiconductor chip is finished, and if there are other semiconductor chips to be connected, similar operations are performed one after another to mount the semiconductor chips on the wiring board.
上記の実施例ではフリップチップ技術における位置合わ
せについて述べたが、テープ自動ポンディング(TAB
)においてもチップ表面を配線基板に向き合わせる場合
すなわち、フェースダウン接続の場合には半導体チップ
裏面の目合わせマークによる位置合わせを行うことがで
きる。Although the above embodiments described alignment in flip-chip technology, tape automatic bonding (TAB
), when the front surface of the chip faces the wiring board, that is, in the case of face-down connection, alignment can be performed using alignment marks on the back surface of the semiconductor chip.
以上説明したように本発明は、半導体チップ裏面の目合
わせマークによって配線基板との位置合わせを行うこと
により、配線基板との接続精度を容易に向上させること
ができる。As described above, the present invention can easily improve the accuracy of connection with the wiring board by aligning the semiconductor chip with the wiring board using alignment marks on the back surface of the semiconductor chip.
第1図は本発明の一実施例を説明する一部ブロック図で
示す斜視図である。
■・・・・・・配線基板、2・・・・・・接続端子、3
・・・・・・半導体チップ、4・・・・・・目合せマー
ク、5・・・・・・位置検出部、6・・・・・・位置制
御部。
代理人 弁理士 内 原 音FIG. 1 is a perspective view showing a partial block diagram for explaining one embodiment of the present invention. ■・・・Wiring board, 2・・・Connection terminal, 3
... Semiconductor chip, 4 ... Alignment mark, 5 ... Position detection section, 6 ... Position control section. Agent Patent Attorney Oto Uchihara
Claims (1)
いて、該半導体装置の裏面のマークによって位置合わせ
を行うことを特徴とする半導体装置の接続方法。1. A method for connecting a semiconductor device, characterized in that, in connecting a wafer chip-shaped semiconductor device and a wiring board, positioning is performed using marks on the back side of the semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1110188A JPH01184930A (en) | 1988-01-20 | 1988-01-20 | Connection of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1110188A JPH01184930A (en) | 1988-01-20 | 1988-01-20 | Connection of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01184930A true JPH01184930A (en) | 1989-07-24 |
Family
ID=11768618
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1110188A Pending JPH01184930A (en) | 1988-01-20 | 1988-01-20 | Connection of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01184930A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6278193B1 (en) * | 1998-12-07 | 2001-08-21 | International Business Machines Corporation | Optical sensing method to place flip chips |
-
1988
- 1988-01-20 JP JP1110188A patent/JPH01184930A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6278193B1 (en) * | 1998-12-07 | 2001-08-21 | International Business Machines Corporation | Optical sensing method to place flip chips |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20030046812A1 (en) | Chip-mounting device and method of alignment thereof | |
JPS6076189A (en) | Method of alinging integrated circuit package | |
TWI423351B (en) | Image identification installation method | |
JP3246010B2 (en) | Electrode structure of flip-chip mounting substrate | |
JPH01184930A (en) | Connection of semiconductor device | |
JP3747054B2 (en) | Bonding apparatus and bonding method | |
JP3801300B2 (en) | Manufacturing method of semiconductor device | |
JPH04102339A (en) | Semiconductor element and its mounting method | |
JPS5847704Y2 (en) | Container for semiconductor devices | |
JPH03101142A (en) | Manufacture of semiconductor device | |
JPS59128735U (en) | Semiconductor chip bonding equipment | |
JPH0212025B2 (en) | ||
WO2022158122A1 (en) | Bonding method and bonding device use method | |
JPH1012661A (en) | Semiconductor device and its manufacture | |
JPS59186334A (en) | Bonding apparatus | |
JPH06310569A (en) | Face-down bonding method of semiconductor element | |
JP4402810B2 (en) | Electronic component mounting machine | |
JP2659286B2 (en) | Semiconductor device wire bonding method | |
JPH065729A (en) | Aligning method for printed circuit board and semiconductor element | |
JPH04302442A (en) | Semiconductor device | |
JP2842852B2 (en) | Method for bonding inner leads for TAB | |
JPS6292342A (en) | Semiconductor package for surface mounting | |
JPH03196634A (en) | Manufacture of semiconductor device | |
JP3117825B2 (en) | Substrate for bump arrangement | |
JPS6376445A (en) | Wire bonding |