JPH06310569A - Face-down bonding method of semiconductor element - Google Patents

Face-down bonding method of semiconductor element

Info

Publication number
JPH06310569A
JPH06310569A JP10118193A JP10118193A JPH06310569A JP H06310569 A JPH06310569 A JP H06310569A JP 10118193 A JP10118193 A JP 10118193A JP 10118193 A JP10118193 A JP 10118193A JP H06310569 A JPH06310569 A JP H06310569A
Authority
JP
Japan
Prior art keywords
semiconductor element
circuit board
pattern surface
hole
bonding method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10118193A
Other languages
Japanese (ja)
Inventor
Makoto Yanaka
真 谷中
Shinsuke Igarashi
晋祐 五十嵐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seikosha KK
Original Assignee
Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seikosha KK filed Critical Seikosha KK
Priority to JP10118193A priority Critical patent/JPH06310569A/en
Publication of JPH06310569A publication Critical patent/JPH06310569A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0266Marks, test patterns or identification means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303Surface mounted components, e.g. affixing before soldering, aligning means, spacing means

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To bond a semiconductor element and a circuit board at the correct position by recognizing reference patterns with an image pickup camera, and controlling the position of a chuck part of a chip mounter so as to align the position with a through hole. CONSTITUTION:A pattern surface 10a of a semiconductor element 10 held with a flat collet 20 of a chip mounted, is brought close to a circuit board 1. A cross mark 30a and the cross mark on the chip mounter are recognized with an image pickup camera 22, respectively, from the lower side of a through hole 1a. The position of the flat collet 20 is controlled so that the positions of the cross mark 30a and the through holes 1a are aligned based on the image information obtained by processing the image of each output. Under the state wherein the position alignment is completed, the semiconductor element 10 is lowered to the side of the circuit board 1. Each bump 11 is brought into contact with each corresponding connecting terminal 5. Bonding is performed by thermocompression binding. The face-down bonding method, by which the mounting accuracy can be improved and which is suitable for the small-amount production for many kinds of articles, can be obtained.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体素子を直接回路
基板に接合するワイヤレスボンディング法の一種であ
る、COB(Chip on Board)方式による半導体素子のフェー
スダウンボンディング法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a face-down bonding method for a semiconductor element by a COB (Chip on Board) method, which is a kind of wireless bonding method for directly bonding a semiconductor element to a circuit board.

【0002】[0002]

【従来の技術】従来、このような半導体素子のフェース
ダウンボンディング法としては、図7(a),(b)に
示すように、半導体素子パターン面70aを回路基板側
に向けて、チップマウンタのチャック部71で半導体素
子70を保持し、半導体素子パターン面70a上の各電
極部、例えば各電極パッド上に形成された各バンプ70
bを回路基板上の半導体素子実装部にある配線パターン
の各接続端子に接合し、半導体素子70の電極と回路基
板の配線パターンとをバンプ70bを介して接続する方
法が知られている。
2. Description of the Related Art Conventionally, as a face-down bonding method for such a semiconductor element, as shown in FIGS. 7 (a) and 7 (b), a semiconductor mount pattern surface 70a is directed to a circuit board side and a chip mounter is used. The chuck 71 holds the semiconductor element 70, and each bump 70 formed on each electrode portion on the semiconductor element pattern surface 70a, for example, each electrode pad.
A method is known in which b is joined to each connection terminal of the wiring pattern in the semiconductor element mounting portion on the circuit board, and the electrode of the semiconductor element 70 and the wiring pattern of the circuit board are connected via the bump 70b.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、上記従
来技術では、半導体素子パターン面70aを下向きにし
て半導体素子70が回路基板に実装されるので、回路基
板に対する半導体素子70の位置確認、すなわち半導体
素子70の各電極部(各バンプ70b)が回路基板の各
接続端子と合致しているか否かの位置確認をするのが難
しく、半導体素子70の各電極部を回路基板の各接続端
子に正しい位置で接合するのが難しいという問題点があ
った。
However, in the above-mentioned conventional technique, since the semiconductor element 70 is mounted on the circuit board with the semiconductor element pattern surface 70a facing downward, the position of the semiconductor element 70 with respect to the circuit board is confirmed, that is, the semiconductor element 70 is mounted. It is difficult to confirm the position of each electrode portion (each bump 70b) of the semiconductor element 70 with each connection terminal of the circuit board, and each electrode portion of the semiconductor element 70 is correctly positioned at each connection terminal of the circuit board. There was a problem that it was difficult to join with.

【0004】また、上記従来技術では、半導体素子70
の実装精度を良くするために、チップマウンタのチャッ
ク部71として角錐コレットを使用し、半導体素子70
の中心が角錐コレット71の軸心と合致しかつ半導体素
子パターン面70aが水平になるように、チップマウン
タに対する半導体素子の位置決めをしてから、半導体素
子70を角錐コレット71で真空チャックして回路基板
側へ所定量搬送するようにしている。ところが、この場
合、半導体素子の搬送中に半導体素子が動いて傾いてし
まったりすることがあり、角錐コレット71で保持され
た半導体素子を正確に所定量搬送したとしても、半導体
素子の各電極部を回路基板の各接続端子に正しい位置で
接合するのが難しいとともに、角錐コレットは個々の半
導体素子の大きさに合わせて作る必要があり、また一つ
一つが高価であり、小量多品種生産には不向きであると
いう問題点があった。
Further, in the above-mentioned conventional technique, the semiconductor element 70 is used.
In order to improve the mounting accuracy of the chip mounter, a pyramid collet is used as the chuck portion 71 of the chip mounter.
The semiconductor element 70 is positioned with respect to the chip mounter such that the center of the semiconductor element 70 is aligned with the axis of the pyramid collet 71 and the semiconductor element pattern surface 70a is horizontal, and then the semiconductor element 70 is vacuum chucked with the pyramid collet 71 to form a circuit. A predetermined amount is conveyed to the substrate side. However, in this case, the semiconductor element may move and tilt during the transportation of the semiconductor element, and even if the semiconductor element held by the pyramid collet 71 is accurately transported by a predetermined amount, each electrode portion of the semiconductor element is transported. Is difficult to join to each connection terminal of the circuit board at the correct position, and the pyramid collet needs to be made according to the size of each semiconductor element. There was a problem that was not suitable for.

【0005】本発明は、実装精度の向上を図るととも
に、チャック部として安価な平コレットを使用すること
によってチャック部の共用化を図り小量多品種生産に適
したフェースダウンボンディング法を提供することを目
的としている。
The present invention aims to improve the mounting accuracy and to provide a face-down bonding method suitable for small-quantity multi-product production by sharing the chuck part by using an inexpensive flat collet as the chuck part. It is an object.

【0006】[0006]

【課題を解決するための手段】上記目的を達成するため
に、本発明は、半導体素子パターン面を回路基板側に向
けて、チップマウンタのチャック部で半導体素子を保持
し、半導体素子パターン面上の各電極部を回路基板上の
半導体素子実装部にある配線パターンの各接続端子に接
合する半導体素子のフェースダウンボンディング法にお
いて、前記回路基板に、前記各接続端子に対する位置決
め基準となる貫通孔を設ける工程と、前記半導体素子パ
ターン面上に、前記各電極部に対する位置決め基準とな
る基準パターンを設ける工程と、前記半導体素子パター
ン面を前記回路基板に近接させた状態で、前記半導体素
子パターン面上の前記基準パターンを前記貫通孔の下方
から撮像カメラにより認識する工程と、前記撮像カメラ
の出力を画像処理して得られる画像情報に基づき、前記
基準パターンを前記貫通孔と位置合わせされるように前
記チャック部の位置を制御する工程と、前記位置合わせ
が完了した状態で前記半導体素子を前記回路基板側へ押
し下げる工程とからなる。
In order to achieve the above object, the present invention is directed to a semiconductor element pattern surface on the semiconductor element pattern surface, with the semiconductor element pattern surface facing the circuit board side and holding the semiconductor element by the chuck portion of the chip mounter. In the face-down bonding method of the semiconductor element in which each electrode part of is bonded to each connection terminal of the wiring pattern in the semiconductor element mounting part on the circuit board, the circuit board is provided with a through hole serving as a positioning reference for each connection terminal. A step of providing, a step of providing a reference pattern on the semiconductor element pattern surface, which serves as a positioning reference for each of the electrode portions, and a step of providing the semiconductor element pattern surface in the vicinity of the circuit board, on the semiconductor element pattern surface. A step of recognizing the reference pattern from below the through hole with an imaging camera, and an image processing of the output of the imaging camera. A step of controlling the position of the chuck portion so that the reference pattern is aligned with the through hole based on image information obtained as a result, and the semiconductor element is moved to the circuit board side in a state where the alignment is completed. The process consists of pushing down.

【0007】[0007]

【作用】半導体素子パターン面を回路基板に近接させた
状態で、半導体素子パターン面上の基準パターンを貫通
孔の下方から撮像カメラにより認識し、撮像カメラの出
力を画像処理して得られる画像情報に基づき、基準パタ
ーンを貫通孔と位置合わせされるようにチップマウンタ
のチャック部の位置を制御し、この位置合わせが完了し
た状態で半導体素子を回路基板側へ押し下げることによ
り、半導体素子パターン面上の各電極部を回路基板上の
半導体素子実装部にある配線パターンの各接続端子に接
合するので、半導体素子の各電極部が回路基板の各接続
端子に正しい位置で接合される。
The image information obtained by recognizing the reference pattern on the semiconductor element pattern surface from below the through hole by the image pickup camera and processing the output of the image pickup camera with the semiconductor element pattern surface being close to the circuit board. Based on the above, the position of the chuck part of the chip mounter is controlled so that the reference pattern is aligned with the through hole, and when this alignment is completed, the semiconductor element is pushed down to the circuit board side, Since each of the electrode portions is bonded to each connection terminal of the wiring pattern in the semiconductor element mounting portion on the circuit board, each electrode portion of the semiconductor element is bonded to each connection terminal of the circuit board at the correct position.

【0008】[0008]

【実施例】以下、図面に基づいて本発明の一実施例に係
る半導体素子のフェースダウンボンディング法を説明す
る。なお、この明細書中で、フェースダウンボンディン
グ法とは、COB(Chip on Board)方式により半導体素子を
直接回路基板に接合するワイヤレスボンディング法のこ
とである。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A face-down bonding method for a semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. In this specification, the face-down bonding method is a wireless bonding method in which a semiconductor element is directly bonded to a circuit board by a COB (Chip on Board) method.

【0009】図2は本発明の一実施例に係る半導体素子
のフェースダウンボンディング法に使用する回路基板を
示している。図2および図3に示すように、回路基板1
には、配線パターン2が形成されている。配線パターン
2の一部は、印刷により形成されたソルダレジスト3に
より被覆されている。また、回路基板1の半導体素子実
装部4では、配線パターン2の複数(この実施例では1
1コ)の接続端子5が外部に露出している。
FIG. 2 shows a circuit board used in a face-down bonding method for a semiconductor device according to an embodiment of the present invention. As shown in FIGS. 2 and 3, the circuit board 1
The wiring pattern 2 is formed on the. A part of the wiring pattern 2 is covered with a solder resist 3 formed by printing. Further, in the semiconductor element mounting portion 4 of the circuit board 1, a plurality of wiring patterns 2 (in this embodiment, 1
1) of the connection terminals 5 is exposed to the outside.

【0010】一方、前記回路基板1に接合される半導体
素子10には、図1(a)および図4に示すように、パ
ターン面(半導体素子パターン面)10a上の電極パッ
ド(図示省略)に、前記配線パターン2と同様に金でで
きた複数(前記接続端子5と同数)のバンプ11が形成
されている。各バンプ11は、前記各接続端子5の端部
に対応する位置に形成されている。
On the other hand, in the semiconductor element 10 bonded to the circuit board 1, as shown in FIGS. 1A and 4, electrode patterns (not shown) on the pattern surface (semiconductor element pattern surface) 10a are formed. As with the wiring pattern 2, a plurality of bumps 11 (the same number as the connection terminals 5) made of gold are formed. Each bump 11 is formed at a position corresponding to the end of each connection terminal 5.

【0011】また、本発明の一実施例に係る半導体素子
のフェースダウンボンディング法を実施するために、図
4に示すように、半導体素子10を真空チャックして保
持する平コレット(チャック部)20を有し、この平コ
レット20で保持された半導体素子10を搬送するため
のチップマウンタ21と、2台の撮像カメラ22,23
と、両撮像カメラ22,23からの各出力を画像処理し
て画像情報信号を出力する画像処理装置24と、平コレ
ット20が載置されたチップマウンタ21のXYテーブ
ルまたは平コレット20を保持しているチップマウンタ
21のロボットアームを駆動する駆動装置25と、画像
処理装置24からの画像情報信号に基づき駆動装置25
を制御する制御部(CPU)26とが設けられている。
In order to carry out the face-down bonding method of the semiconductor device according to the embodiment of the present invention, as shown in FIG. 4, a flat collet (chuck portion) 20 for holding the semiconductor device 10 by vacuum chucking. And a chip mounter 21 for carrying the semiconductor element 10 held by the flat collet 20 and two image pickup cameras 22 and 23.
And an image processing device 24 for image-processing each output from both imaging cameras 22 and 23 and outputting an image information signal, and an XY table of the chip mounter 21 on which the flat collet 20 is mounted or a flat collet 20. The driving device 25 for driving the robot arm of the chip mounter 21 and the driving device 25 based on the image information signal from the image processing device 24.
And a control unit (CPU) 26 for controlling the.

【0012】本発明の一実施例に係る半導体素子のフェ
ースダウンボンディング法は、下記の各工程(1)〜
(6)を有している。
A face-down bonding method for a semiconductor device according to an embodiment of the present invention is described in the following steps (1) to (1).
It has (6).

【0013】(1)前記回路基板1に、各接続端子5に
対する位置決め基準となる円形の貫通孔1a,1bを設
ける(図2および図4を参照)。貫通孔1aは、前記半
導体実装部4の中心部に設けられている。一方、貫通孔
1bは、貫通孔1aから任意の距離だけ離れていればよ
い。
(1) The circuit board 1 is provided with circular through holes 1a and 1b serving as a positioning reference for each connection terminal 5 (see FIGS. 2 and 4). The through hole 1a is provided in the central portion of the semiconductor mounting portion 4. On the other hand, the through hole 1b may be separated from the through hole 1a by an arbitrary distance.

【0014】(2)前記半導体素子10のパターン面1
0a上に、前記各バンプ11に対する位置決め基準とな
る基準パターンであり、貫通孔1aと位置決めされる十
字マーク30aを設けるとともに、前記チップマウンタ
21の、回路基板1と対向する面21a上に、各バンプ
11に対する位置決め基準となる基準パターンであり、
貫通孔1bと位置決めされる十字マーク30bを設ける
(図4および図5を参照)。
(2) Pattern surface 1 of the semiconductor element 10
0a is a reference pattern serving as a positioning reference for each of the bumps 11, and a cross mark 30a that is positioned with the through hole 1a is provided, and on the surface 21a of the chip mounter 21 facing the circuit board 1, A reference pattern serving as a positioning reference for the bump 11,
A cross mark 30b that is positioned with the through hole 1b is provided (see FIGS. 4 and 5).

【0015】(3)半導体素子10のパターン面10a
が水平になるように、半導体素子10を平コレット20
で真空チャックして回路基板1の上方へ搬送する(図1
(a)を参照)。
(3) Pattern surface 10a of the semiconductor element 10
So that the semiconductor element 10 is flat and the flat collet 20
And vacuum chuck to convey it above the circuit board 1 (see FIG. 1).
(See (a)).

【0016】(4)半導体素子10のパターン面10a
を回路基板1に近接させた状態(図1(a)の状態)
で、パターン面10a上の十字マーク30aおよびチッ
プマウンタ21上の十字マーク30bを貫通孔1a,1
bの下方からそれぞれ撮像カメラ22,23により認識
する(図1(a)および図4を参照)。
(4) Pattern surface 10a of the semiconductor element 10
The circuit board 1 close to the circuit board 1 (the state of FIG. 1A)
To form the cross mark 30a on the pattern surface 10a and the cross mark 30b on the chip mounter 21 in the through holes 1a, 1
It is recognized by the imaging cameras 22 and 23 from below b (see FIG. 1A and FIG. 4).

【0017】(5)両撮像カメラ22,23の各出力を
画像処理して得られる画像情報に基づき、十字マーク3
0a,30bが貫通孔1a,1bと位置合わせされるよ
うに平コレット20の位置を制御する。すなわち、両撮
像カメラ22,23の各出力を画像処理装置24により
画像処理し、制御部26が、画像処理装置24から出力
される画像情報信号に基づき、各貫通孔1a,1bの中
心と各十字マーク30a、30bの中心とのずれ量を演
算しかつこのずれ量に応じた制御信号を駆動装置25に
出力し、この駆動装置25により平コレット20が載置
されたチップマウンタ21のXYテーブルまたは平コレ
ット20を保持しているチップマウンタ21のロボット
アームを駆動する。これによって、各十字マーク30
a、30bの中心が各貫通孔1a,1bの中心と合致す
るように、平コレット20の位置がフィードバック制御
される。
(5) Based on the image information obtained by image-processing the outputs of both imaging cameras 22 and 23, the cross mark 3
The position of the flat collet 20 is controlled so that 0a and 30b are aligned with the through holes 1a and 1b. That is, the outputs of both imaging cameras 22 and 23 are image-processed by the image processing device 24, and the control unit 26 determines the centers of the through holes 1a and 1b and the respective images based on the image information signal output from the image processing device 24. The displacement amount from the center of the cross marks 30a and 30b is calculated and a control signal corresponding to the displacement amount is output to the driving device 25, and the XY table of the chip mounter 21 on which the flat collet 20 is mounted is driven by the driving device 25. Alternatively, the robot arm of the chip mounter 21 holding the flat collet 20 is driven. As a result, each cross mark 30
The position of the flat collet 20 is feedback-controlled so that the centers of a and 30b coincide with the centers of the through holes 1a and 1b.

【0018】(6)前記位置合わせが完了した状態で、
すなわち図5および図6に示すように各十字マーク30
a、30bの中心が各貫通孔1a,1bの中心と合致し
た状態で、図1(a)の位置にある半導体素子10を回
路基板1側へ押し下げ、半導体素子10の各バンプ11
を対応する各接続端子5と接触させる(図1(b)を参
照)。
(6) With the above alignment completed,
That is, as shown in FIG. 5 and FIG.
With the centers of a and 30b aligned with the centers of the through holes 1a and 1b, the semiconductor element 10 at the position shown in FIG.
With each corresponding connection terminal 5 (see FIG. 1B).

【0019】(7)各バンプ11が対応する各接続端子
5と接触した状態(図1(b)の状態)で一定量つぶれ
るように、半導体素子10を回路基板1側へさらに押し
下げる。
(7) The semiconductor element 10 is further pushed down to the circuit board 1 side so that each bump 11 is crushed by a certain amount in a state of contacting each corresponding connection terminal 5 (state of FIG. 1B).

【0020】(8)熱圧着により各バンプ11を各接続
端子5に接合する(図6を参照)。
(8) Each bump 11 is bonded to each connection terminal 5 by thermocompression bonding (see FIG. 6).

【0021】(9)各バンプ11が各接続端子5に接合
された状態で、半導体素子10の上方に位置させたディ
スペンサ40と貫通孔1a内に挿入したディスペンサ4
1とからエポキシ樹脂等の封止剤を吐出させることによ
り、半導体素子10の上下両側から半導体素子10の周
囲全体を封止剤により封止して半導体素子10を保護す
る(図1(c)および(d)を参照)。この封止剤によ
る被覆の輪郭が図2の鎖線Aで示されている。
(9) The dispenser 40 positioned above the semiconductor element 10 and the dispenser 4 inserted into the through hole 1a with each bump 11 bonded to each connection terminal 5.
By discharging a sealing agent such as epoxy resin from 1 and 2, the entire periphery of the semiconductor element 10 is sealed with the sealing agent from both upper and lower sides of the semiconductor element 10 to protect the semiconductor element 10 (FIG. 1C). And (d)). The outline of the covering by this sealant is shown by a chain line A in FIG.

【0022】本実施例によれば、パターン面10a上の
十字マーク30aおよびチップマウンタ21上の十字マ
ーク30bを貫通孔1a,1bの下方からそれぞれ撮像
カメラ22,23により認識し(上記工程(4))、両
撮像カメラ22,23の各出力を画像処理して得られる
画像情報に基づき、各十字マーク30a、30bの中心
が各貫通孔1a,1bの中心と合致するように、平コレ
ット20の位置をフィードバック制御し(上記工程
(5))、位置合わせが完了した状態で、すなわち図5
および図6に示すように各十字マーク30a、30bの
中心が各貫通孔1a,1bの中心と合致した状態で、半
導体素子10を回路基板1側へ押し下げて各バンプ11
を対応する各接続端子5と接触させ(上記工程(6)を
参照)、その後にパターン面10a上の各バンプ11を
各接続端子5に接合するので、半導体素子10の各バン
プ(電極部)が回路基板1の各接続端子5に正しい位置
で接合される(図6を参照)。
According to this embodiment, the cross mark 30a on the pattern surface 10a and the cross mark 30b on the chip mounter 21 are recognized by the image pickup cameras 22 and 23 from below the through holes 1a and 1b, respectively (see the above step (4 )), Based on the image information obtained by performing image processing on the outputs of both imaging cameras 22 and 23, the flat collet 20 is arranged so that the centers of the cross marks 30a and 30b coincide with the centers of the through holes 1a and 1b. Is feedback-controlled (step (5) above) to complete the alignment, that is, in FIG.
Also, as shown in FIG. 6, with the center of each cross mark 30a, 30b aligned with the center of each through hole 1a, 1b, the semiconductor element 10 is pushed down to the circuit board 1 side and each bump 11 is pressed.
To contact each corresponding connection terminal 5 (see the above step (6)), and thereafter each bump 11 on the pattern surface 10a is bonded to each connection terminal 5, so that each bump (electrode portion) of the semiconductor element 10 Are bonded to the respective connection terminals 5 of the circuit board 1 at correct positions (see FIG. 6).

【0023】なお、本実施例では、各接続端子5に対す
る位置決め基準となる貫通孔として、半導体素子実装部
4の中心部に円形の貫通孔1aを設けるとともに、前記
実装部4以外の箇所にも円形の貫通孔1bを設けている
が、本発明はこれに限定されない。例えば、他の実施例
としては、前記実装部4の中心部にのみ長孔形状等の異
形の貫通孔を設ける構成が考えられる。この場合には、
チップマウンタ21の面21a上に設けた前記十字マー
ク30bは不要である。
In this embodiment, as a through hole serving as a positioning reference for each connection terminal 5, a circular through hole 1a is provided at the center of the semiconductor element mounting portion 4 and also at a portion other than the mounting portion 4. Although the circular through hole 1b is provided, the present invention is not limited to this. For example, as another embodiment, a configuration in which a deformed through hole such as a long hole shape is provided only in the central portion of the mounting portion 4 is conceivable. In this case,
The cross mark 30b provided on the surface 21a of the chip mounter 21 is unnecessary.

【0024】[0024]

【発明の効果】以上詳述したように、本発明によれば、
半導体素子パターン面を回路基板に近接させた状態で、
半導体素子パターン面上の基準パターンを貫通孔の下方
から撮像カメラにより認識し、撮像カメラの出力を画像
処理して得られる画像情報に基づき、基準パターンを貫
通孔と位置合わせされるようにチップマウンタのチャッ
ク部の位置を制御し、この位置合わせが完了した状態で
半導体素子を回路基板側へ押し下げることにより、半導
体素子パターン面上の各電極部を回路基板上の半導体素
子実装部にある配線パターンの各接続端子に接合するの
で、半導体素子の各電極部が回路基板の各接続端子に正
しい位置で接合される。したがって、実装精度の向上を
図ることができるとともに、半導体素子を保持するチャ
ック部として安価な平コレットを使用することによりチ
ャック部の共用化が図れ、小量多品種生産に適したフェ
ースダウンボンディング法を得ることができる。
As described in detail above, according to the present invention,
With the semiconductor element pattern surface close to the circuit board,
The chip mounter is used so that the reference pattern on the semiconductor element pattern surface is recognized by the imaging camera from below the through hole, and the reference pattern is aligned with the through hole based on the image information obtained by image processing the output of the imaging camera. By controlling the position of the chuck part of the device and pushing down the semiconductor element to the circuit board side when this alignment is completed, each electrode part on the semiconductor element pattern surface is placed in the wiring pattern on the semiconductor element mounting part on the circuit board. Since each of the electrode terminals of the semiconductor element is joined to each of the connecting terminals of the circuit board at the correct position. Therefore, it is possible to improve the mounting accuracy, and by using an inexpensive flat collet as a chuck portion for holding a semiconductor element, the chuck portion can be shared, and a face-down bonding method suitable for small-quantity multi-product production. Can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a)〜(d)は本発明の一実施例に係る半導
体素子のフェースダウンボンディング法の説明図で、 (a)は半導体素子を回路基板に近接させた状態の図 (b)は半導体素子の各バンプが回路基板の各接続端子
に接合された状態の図 (c)は半導体素子の上下両面からその周囲全体を封止
剤により封止する様子を示す断面図 (d)は半導体素子全体が封止剤により封止された状態
を示す断面図である。
1A to 1D are explanatory views of a face-down bonding method for a semiconductor device according to an embodiment of the present invention, and FIG. 1A is a diagram showing a state in which the semiconductor device is brought close to a circuit board. FIG. 7A is a diagram in which each bump of the semiconductor element is joined to each connection terminal of the circuit board. FIG. 9C is a cross-sectional view showing a state in which the entire periphery of the semiconductor element is sealed from the upper and lower surfaces with a sealant. FIG. 4 is a cross-sectional view showing a state in which the entire semiconductor element is sealed with a sealant.

【図2】本発明に係る半導体素子のフェースダウンボン
ディング法に使用する回路基板を示す平面図である。
FIG. 2 is a plan view showing a circuit board used in a face-down bonding method for a semiconductor device according to the present invention.

【図3】図2の一部拡大図である。FIG. 3 is a partially enlarged view of FIG.

【図4】本発明に係る半導体素子のフェースダウンボン
ディング法を実施するための装置を示す概略構成図であ
る。
FIG. 4 is a schematic configuration diagram showing an apparatus for carrying out a face-down bonding method for a semiconductor device according to the present invention.

【図5】回路基板を下方から見た平面図で、半導体素子
と回路基板の位置合わせを説明するための説明図であ
る。
FIG. 5 is a plan view of the circuit board seen from below, which is an explanatory diagram for explaining the alignment of the semiconductor element and the circuit board.

【図6】半導体素子の各バンプが回路基板の各接続端子
に正しい位置で接合された状態を示す平面図である。
FIG. 6 is a plan view showing a state in which each bump of the semiconductor element is bonded to each connection terminal of the circuit board at a correct position.

【図7】(a)は従来例を示す図で、半導体素子がチャ
ック部で真空チャックされた状態を示す断面図であり、
(b)は図7(a)を下から見た平面図である。
FIG. 7A is a view showing a conventional example, and is a cross-sectional view showing a state in which a semiconductor element is vacuum chucked by a chuck portion;
FIG. 7B is a plan view of FIG. 7A viewed from below.

【符号の説明】[Explanation of symbols]

1 回路基板 1a,1b 貫通孔 2 配線パターン 4 半導体素子実装部 5 接続端子 10 半導体素子 10a パターン面(半導体素子パターン面) 20 平コレット(チャック部) 21 チップマウンタ 22 撮像カメラ DESCRIPTION OF SYMBOLS 1 Circuit board 1a, 1b Through hole 2 Wiring pattern 4 Semiconductor element mounting part 5 Connection terminal 10 Semiconductor element 10a Pattern surface (semiconductor element pattern surface) 20 Flat collet (chuck part) 21 Chip mounter 22 Imaging camera

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子パターン面を回路基板側に向
けて、チップマウンタのチャック部で半導体素子を保持
し、半導体素子パターン面上の各電極部を回路基板上の
半導体素子実装部にある配線パターンの各接続端子に接
合する半導体素子のフェースダウンボンディング法にお
いて、 前記回路基板に、前記各接続端子に対する位置決め基準
となる貫通孔を設ける工程と、 前記半導体素子パターン面上に、前記各電極部に対する
位置決め基準となる基準パターンを設ける工程と、 前記半導体素子パターン面を前記回路基板に近接させた
状態で、前記半導体素子パターン面上の前記基準パター
ンを前記貫通孔の下方から撮像カメラにより認識する工
程と、 前記撮像カメラの出力を画像処理して得られる画像情報
に基づき、前記基準パターンを前記貫通孔と位置合わせ
されるように前記チャック部の位置を制御する工程と、 前記位置合わせが完了した状態で前記半導体素子を前記
回路基板側へ押し下げる工程とからなることを特徴とす
る半導体素子のフェースダウンボンディング法。
1. A semiconductor element is held by a chuck portion of a chip mounter with the semiconductor element pattern surface facing the circuit board side, and each electrode portion on the semiconductor element pattern surface is provided in a semiconductor element mounting portion on the circuit board. In a face-down bonding method of a semiconductor element to be bonded to each connection terminal of a pattern, a step of providing a through hole which serves as a positioning reference for each connection terminal in the circuit board, and each electrode part on the semiconductor element pattern surface. A step of providing a reference pattern serving as a positioning reference for the semiconductor element pattern surface in a state where the semiconductor element pattern surface is brought close to the circuit board, and the reference pattern on the semiconductor element pattern surface is recognized from below the through hole by an imaging camera. And a reference pattern based on image information obtained by image-processing the output of the imaging camera. A semiconductor device comprising: a step of controlling the position of the chuck part so as to be aligned with the through hole; and a step of pushing down the semiconductor element to the circuit board side in a state where the alignment is completed. Face down bonding method.
JP10118193A 1993-04-27 1993-04-27 Face-down bonding method of semiconductor element Pending JPH06310569A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10118193A JPH06310569A (en) 1993-04-27 1993-04-27 Face-down bonding method of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10118193A JPH06310569A (en) 1993-04-27 1993-04-27 Face-down bonding method of semiconductor element

Publications (1)

Publication Number Publication Date
JPH06310569A true JPH06310569A (en) 1994-11-04

Family

ID=14293826

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10118193A Pending JPH06310569A (en) 1993-04-27 1993-04-27 Face-down bonding method of semiconductor element

Country Status (1)

Country Link
JP (1) JPH06310569A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6193132B1 (en) * 1997-11-27 2001-02-27 Kabushiki Kaisha Toshiba Method for bonding semiconductor chip and device therefor
EP1239500A3 (en) * 2001-03-06 2003-01-08 Citizen Electronics Co., Ltd. Tactile switch
KR100548683B1 (en) * 1997-07-30 2006-04-21 세이코 엡슨 가부시키가이샤 Method for manufacturing circuit structure unit and liquid crystal device
US20130201639A1 (en) * 2012-02-02 2013-08-08 Do Hyung Ryu Display device and method of manufacturing the same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100548683B1 (en) * 1997-07-30 2006-04-21 세이코 엡슨 가부시키가이샤 Method for manufacturing circuit structure unit and liquid crystal device
US6193132B1 (en) * 1997-11-27 2001-02-27 Kabushiki Kaisha Toshiba Method for bonding semiconductor chip and device therefor
EP1239500A3 (en) * 2001-03-06 2003-01-08 Citizen Electronics Co., Ltd. Tactile switch
US6596954B2 (en) 2001-03-06 2003-07-22 Citizen Electronics Co., Ltd. Tactile switch
US20130201639A1 (en) * 2012-02-02 2013-08-08 Do Hyung Ryu Display device and method of manufacturing the same
CN103249260A (en) * 2012-02-02 2013-08-14 三星显示有限公司 Display apparatus and method of manufacturing the same
US9271433B2 (en) * 2012-02-02 2016-02-23 Samsung Display Co., Ltd. Display device and method of manufacturing the same

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