JPH01172094U - - Google Patents
Info
- Publication number
- JPH01172094U JPH01172094U JP6858988U JP6858988U JPH01172094U JP H01172094 U JPH01172094 U JP H01172094U JP 6858988 U JP6858988 U JP 6858988U JP 6858988 U JP6858988 U JP 6858988U JP H01172094 U JPH01172094 U JP H01172094U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- synchronization signal
- display device
- video
- determination means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 2
Landscapes
- Digital Computer Display Output (AREA)
- Liquid Crystal Display Device Control (AREA)
Description
第１図は本考案実施例の構成を示すブロツク図
、第２図は本考案実施例の回路を示す図、第３図
と第４図は本考案実施例の動作タイミングを示す
図、第５図は従来例の構成を示すブロツク図であ
る。
１……水平・垂直タイミング及びクロツク作成
回路、２……フレームメモリー書き込み回路、３
……フレームメモリー読み出し及び液晶表示回路
、４……フレームメモリー回路、５……液晶表示
ユニツト、６……入力信号有無判定回路、７……
表示画面クリアー回路。
FIG. 1 is a block diagram showing the configuration of the embodiment of the invention, FIG. 2 is a diagram showing the circuit of the embodiment of the invention, FIGS. 3 and 4 are diagrams showing the operation timing of the embodiment of the invention, and FIG. The figure is a block diagram showing the configuration of a conventional example. 1... Horizontal/vertical timing and clock generation circuit, 2... Frame memory writing circuit, 3
... Frame memory reading and liquid crystal display circuit, 4 ... Frame memory circuit, 5 ... Liquid crystal display unit, 6 ... Input signal presence/absence determination circuit, 7 ...
Display screen clear circuit.
Claims (1)
示装置において、同期信号の有無を判定する信号
判定手段と、この信号判定手段により同期信号が
無いことを判定したとき表示画面を消す画面消去
手段とを備えたことを特徴とする表示装置。 In a display device that displays a video by receiving a video signal and a synchronization signal, the signal determination means determines the presence or absence of a synchronization signal, and the screen erasing means erases a display screen when the signal determination means determines that there is no synchronization signal. A display device comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6858988U JPH01172094U (en) | 1988-05-23 | 1988-05-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6858988U JPH01172094U (en) | 1988-05-23 | 1988-05-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01172094U true JPH01172094U (en) | 1989-12-06 |
Family
ID=31293898
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6858988U Pending JPH01172094U (en) | 1988-05-23 | 1988-05-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01172094U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5597774A (en) * | 1979-01-20 | 1980-07-25 | Nec Corp | Cathode-ray tube display unit |
-
1988
- 1988-05-23 JP JP6858988U patent/JPH01172094U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5597774A (en) * | 1979-01-20 | 1980-07-25 | Nec Corp | Cathode-ray tube display unit |
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