JPH01162437A - Data multi-step repeating system - Google Patents

Abstract

PURPOSE:To prevent the jitter accumulation in a clock and to execute the multi-step repeating of the high quality data even when the number of the steps of repeating is increased to a prescribed number or above by correcting a transmission timing with respective repeating stations when plural data are multiplexed and converted with a time division and the multi-step repeating is executed. CONSTITUTION:When a repeating station receives the descending reception data 1' from the base station of a time division multiplexing communication system, the crossing-over processing of a station reference clock is executed from a preamble pulse included in this to a clock. Next, the frame synchroniza tion pulse in a crossed-over descending reception data 1' is detected by a syn chronization detecting means 30 and the data 1' are written to a delaying means 50 with the timing of a detected pulse 5. On the other hand, a descending refer ence timing correcting means 60 sends a pulse 6 to read the data 1' to the means 50, adjusts the time delaying of the pulse 6 and sends it to a and sends it to an ascending reference timing correcting means 60'. At this time, when the phase of the detected pulse 5 is different from the previous phase, the phase is corrected in the dislocated direction with the means 60.

Description

[Detailed Description of the Invention] [Summary] Regarding the method of time-division multiplexing and multi-stage relaying of a plurality of data, there is a multi-stage method that allows normal data to be relayed even if the number of relay stages is greater than a predetermined number. With the aim of realizing a relay system, the clock extracted from the preamble pulse included in uplink and downlink received data is transferred to the internal reference clock, and the same amount of pulses are extracted from the preamble pulse included in the received data. The frame synchronization pulse detected by the synchronization detection means is used as a data write timing pulse, and the received data written using this data write timing pulse is read at the timing output from the downlink and uplink reference timing correction means. The downlink reference timing is generated based on the data write timing pulse sent out from the data delay means and the synchronization detection means, and if the clock extracted from the downlink reception data and the internal reference clock are asynchronous and a timing shift occurs, , a downlink reference timing correction means for correcting the reference timing in the direction of deviation, and a timing obtained by delaying the timing output from the downlink reference timing correction means by a predetermined period of time as an uplink data frame processing timing. When the reference timing is generated,
When a timing different from the data frame corrected by the downlink reference timing correction means is input, the relay station is provided with uplink reference timing correction means for correcting the reference to the shifted timing.

[Industrial application field]

The present invention relates to a method for time-division multiplexing multiple data and relaying it in multiple stages.

For example, when installing a telephone line for a small number of subscribers in a remote area, in order to save the cost and time of laying cables, it is necessary to install a terminal station for accommodating subscribers and a terminal station for accommodating subscribers as well as multiple terminal stations. The accommodating relay stations are installed in multiple stages, and data is wirelessly relayed to the base station that serves as the center.

Further, this base station accommodates this multi-stage relay station, and a digital data wireless communication system has been put into practical use in which data received from these relay stations is converted and connected to a telephone station via wire.

That is, a base station has a plurality of relay stations and terminal stations under its control, and data transmission between these stations is performed by a system that performs time division multiple access of frequencies (hereinafter referred to as a TDMA system).

When data is relayed in multiple stages in this TDMA system, each station extracts a clock for internal processing from the data, generates a clock, and relays data from the base station.

It is necessary to perform such processing with higher precision with a simpler configuration in order to relay and transmit accurate data in multiple stages.

[Conventional technology]

Fig. 3 is a block diagram explaining the conventional example, Fig. 4 is a diagram explaining the outline of the configuration of a multi-stage relay station, Fig. 5 is a diagram explaining the outline of the system configuration of multi-stage relay, and Fig. 6 is the data of the wireless section. Figures illustrating the frame format of are shown respectively.

FIG. 5 shows the configuration of a TDMA digital wireless communication system, which consists of a base for the TDMA digital wireless communication system, each terminal station 3(i) and relay station 2(i) (usually 12
It converts the speed and formant of the voice concentrated from the relay station (consisting of relay stations) to be transferred to the PCM highway Tal, and the voice that was transmitted on the PCM highway Ta) is transferred to each terminal station 3(i) and the relay station. Base station 1 transmitting data to station 2(i), multiple terminal stations 3(i), multiple telephone subscribers, etc. = 6
- A relay station 2(i) which accommodates terminals of 12 terminals and relays up to 12 stages, and a plurality of terminal stations 3 which are located at the final stage of the digital wireless communication system and accommodate terminals of a plurality of telephone subscribers, etc. (i), a concentrator 4 that converts the voice received from the base station 1 via the PCM highway (al) onto a 2-line (2W) line (b), and accommodates it in the exchange 5; It consists of an exchange 5 that accommodates telephone subscribers.

FIG. 4 shows the above-mentioned base station 1. Relay station 2 (i) and terminal station 3 (
i) The base station 1 in the figure controls the internal operations based on a predetermined program, and also controls the internal processing job schedule by operating a terminal (not shown) connected to the concentrator 4. Central processing unit (hereinafter referred to as CPU) 1 that can specify
1, a transceiver (hereinafter referred to as TRX) 12 that transmits and receives data using the TDMA method, and a speed/format that converts the data transmitted via the PCM highway (a) into the format and speed of the TDMA method. The conversion unit 13 and a preamble (a string of information inserted at the beginning of the data frame as shown in FIGS. 6(C) and (D) for the purpose of synchronization) are added to each of the plurality of transmission data to be transmitted to the downlink. ) and a time slot synchronization pattern for multiplexing by inserting them (hereinafter referred to as DTX) 14; and a reception control unit that extracts and reproduces the received data transferred from the uplink in the time slot TS. (Hereinafter [I
(referred to as RX) 15, and the relay station 2(i) in the figure
TRX21.22, which performs transmission and reception of data with upper and lower stations, and a downlink and uplink reception control unit (hereinafter referred to as DRX and tlRX) which controls reception of downlink and uplink data. 23a and 23b, downlink and uplink transmission control units (hereinafter referred to as DTX and ITX) 24a and 24b that control the transmission of downlink and uplink data, and a terminal station 3(i) or a lower relay station. A delay adjustment control unit (hereinafter referred to as ILL C) checks the time slot sending timing deviation from the transmission data and adjusts the time slot sending timing deviation within its own station based on instructions from the upper station.
0NT) 25, a control unit (hereinafter referred to as C0NT) 26 that controls processing operations within the station, and an interface unit (hereinafter referred to as INTF) 27 that interfaces with telephone subscriber terminals, data terminals, etc. The terminal station 3(i) in the figure is a TI? X31. DRX32. UTX35. I
NTF36 and C0NT33 that controls processing operations within the station
and DL, which adjusts the deviation in time slot transmission timing within its own station based on instructions from relay station 2(i), which is the upper station.
C0NT34.

Figure 3 shows DRX23a and URX23 in relay station 2(i).
An overview of the configuration of b.

That is, the DRX 23a has a downlink clock extraction circuit 233 that extracts the clock ■ from the preamble pulse included in the downlink reception data ■, and a downlink reception that follows this clock ■ based on the clock ■ extracted and output by the downlink clock extraction circuit 233. Reference clock generation circuit 410 that generates internal processing clocks ■, ■' for processing data ■ or upstream received data ■
and a downlink transfer circuit 2 that transfers the downlink received data ■ to the clock ■ generated from the reference clock generation circuit 410.
31, and the downlink received data ■' transferred by the downlink clock transfer circuit 231 is written at the timing ■ detected by the synchronization pattern detection circuit 237 (this is used as a write control signal), and the timing ■' from the downlink reference frame counter 239 is written. This is used as a read control signal) to read out the elastic memory 235, and the frame synchronization pulse (as shown in FIG. 6(D) 5YNC) to detect a synchronization pattern pulse;
It includes a downlink reference frame counter 239 that generates downlink reference timing based on the synchronization pattern pulse detected by the synchronization pattern detection circuit 237.

Further, the URX 23b includes an upstream clock transfer circuit 232, an upstream clock extraction circuit 234, and an upstream clock extraction circuit 234. Synchronous pattern detection circuit 238
and an elastic memory 236.

In addition, the code 261 shown in FIG. 3 is C0NT2 shown in FIG.
CPU control circuit, code 2, which is a functional block included in 6
71 is a terminal interface within the INTF 27, and 251 is a delay adjustment circuit within the DL CONT 25 also shown in FIG.

Further, the DTX 24a shown in FIG. 4 includes a downlink transmission data control circuit 2411. The UTX 24-pI- is equipped with an uplink transmission data control circuit 242 and an uplink reference frame counter 243 that outputs a reference timing for transmitting uplink transmission data ``.

The area between the base station 1, the relay station 2(i), and the end station 3(1) shown in FIGS. 4 and 5 is a wireless section in which data is transmitted and received using microwaves, for example, and data frames are transmitted and received in this wireless section. The format is shown in Figure 6.

That is, when the DTX 24a transfers a downstream data frame in the frame format shown in FIG. 6(B), a 16-bit preamble and a 16-bit synchronization pattern (SYNC) are inserted at a predetermined position in each time slot TS. At the same time, the main data received from the upper station is multiplexed.

The sending timing at this time is the timing when the downstream reference frame J in the DRX 23a is sent from the counter 239.
The multiplexed data will be sent to the lower station via the TX 24a.

That is, the downlink reception data (2) received from the higher-level station is sent out at the timing of the higher-level station. A downlink clock extraction circuit 233 extracts a clock (2) from the preamble pulse included in this downlink received data (2), and a reference clock generation circuit 410 generates an internal reference clock (2) based on the extracted clock (2).

Then, the downlink received data ■ is transferred to this internal reference clock ■ (however, only the phase is changed), and the downlink received data ■′ transferred to this internal reference clock ■.
A frame synchronization pulse (SYNC) contained therein is detected by a synchronization pattern detection circuit 237, and based on this, the frame synchronization pulse (SYNC) is transmitted to a lower station at a transmission timing generated by a downlink reference frame counter 239.

On the other hand, the uplink received data ■ is similarly transferred from the clock ■′ extracted by the uplink clock extraction circuit 234 to the station reference clock ■′ generated by the reference clock generation circuit 410.
The frame synchronization pulse included in the uplink reception data ``2'' is detected by the synchronization pattern detection circuit 238, and based on this, the frame synchronization pulse is sent to the upper station at the transmission timing generated by the uplink reference frame counter 243.

The transmission timing sent out from the uplink reference frame counter 243 is generated based on the timing (2) obtained by delay-adjusting the sending timing sent out from the downlink reference frame counter 239 by a predetermined time by the delay adjustment circuit 251.

[Problem that the invention seeks to solve]

In the conventional TDMA system as described above, for example, a clock is extracted from the downlink reception data (■) from the base station 1, an internal reference clock (■) is generated based on this, and each relay station 2
(i) and the terminal station 3(i) perform internal processing at the timing of the generated internal reference clock ■.

When the downlink/uplink received data ■, ■ is relayed in multiple stages in this way, the station reference clocks ■, ■′ are extracted from the clocks ■, ■′ of the downlink/uplink received data.
When switching to the clock, a slight phase shift may occur between the clocks ■, ■′ and the local reference clocks ■, ■′, and this becomes a problem in the clock extracted at the next stage and accumulates. .

Therefore, it is virtually impossible to increase the number of relay stages beyond a predetermined value in order to relay and transmit normal data.

An object of the present invention is to realize a multi-stage relay system that can relay and transmit normal data even if the number of relay stages is increased beyond a predetermined value.

[Means for solving problems]

FIG. 1 shows a block diagram illustrating the invention in detail.

The principle block diagram of the present invention shown in FIG.
0' is a synchronization detection means that detects a frame synchronization pulse included in the received clock ■'8■' when the clock extracted from the preamble pulse included in the uplink and downlink received data is switched to the local reference clock, 50.50' is the frame synchronization pulse detected by the synchronization detection means 30.30' as the data 1 write timing pulses ■, ■', and the received data written by the data write timing pulses ■, ■' are the received data ■', ■ ' is a downlink and uplink reference timing correction means 60. 60 is a data delay means that does not read data at the timings ■ and ■ output from ', and 60 is a downlink reference timing correction means based on the data write timing pulse ■ sent out from the synchronization detection means 30. 60' is a downlink reference timing correction means that not only generates timing but also corrects the reference timing in the direction of the deviation when the clock extracted from the downlink reception data and the local reference clock are asynchronous and a timing difference occurs. The timing obtained by delaying the timing ■ output from the reference timing correction means 60 by a predetermined time is set as the uplink data frame processing timing ■, and based on this uplink data frame processing timing ■, the uplink reference timing ■ is generated, and the downlink reference timing is When a timing different from the data frame corrected by the timing correction means 60 is input, the uplink reference timing correction means corrects the reference to the shifted timing, and a relay station is configured by having these means. This is a means to solve this problem.

- 15 = [Function] For example, when a relay station receives downlink reception data from a base station of a time division multiplex communication system, it transfers this downlink reception data from the clock extracted from the preamble pulse included therein to the in-station reference clock. I do.

Then, the synchronization detection means 30 detects the frame synchronization pulse included in the downlink received data ■' transferred to this internal reference clock, and writes the downlink received data ■' to the data delay means 50 at the timing of the detected pulse ■. It's crowded.

On the other hand, the downlink reference timing correction means 60 receives the downlink received data ■' written in the data delay means 50 by the pulse ■.
The pulse (2) for reading out is sent to the data delay means 50, and this pulse (2) is delayed by a predetermined time and sent to the uplink reference timing correction means 60'.

At this time, if the phase of the pulse ■ detected by the synchronization detection means 30 differs from the previous phase, that is, if the phase of the pulse ■ differs from the previous phase due to a phase shift that occurs when switching to the local reference clock, the downlink reference clock Timing correction means 6
0 performs a correction process to match the deviation, and transmits the downlink transmission data ■'' to the next stage.

Similarly, the uplink reference timing correction means 60' corrects the deviation in the uplink received data ``■'', and by configuring the uplink transmission data ``■'' to be transmitted to the next stage, the timing is always maintained regardless of the number of relay stages. It becomes possible to relay and transmit high-quality data.

〔Example〕

The gist of the present invention will be specifically explained below with reference to an embodiment shown in FIG.

FIG. 2 shows a block diagram illustrating the invention in detail. Note that the same reference numerals refer to the same objects throughout the plan.

The embodiment of the present invention shown in FIG. 2 shows a part of the configuration overview of the relay station 2(i) shown in FIGS. Means 30.30'
As described in FIG. 3, the synchronization pattern = 18- detection circuits 237, 238, data delay means 50, 50', elastic memories 235, 236, described in FIG. 3, down/up reference timing correction means 60, 60'. This is an example configured with down/up reference timing correction circuits 60a and 60b.

Note that the internal reference timing in this embodiment is determined by the clock generator (C) that oscillates the reference signal during internal processing operations.
LK GEN) Signals from 40a internal oscillator 40b■,■
'. Further, the functional blocks of this embodiment other than those described above have the same contents as those explained in FIG. 3.

Down/up clock transfer circuit 231゜23 shown in Fig. 2
2 is FIFO (First-in First-Out
) memory, and the oscillator 40b is an oscillator using a crystal oscillator as an oscillator.

Note that the DRX 230a of this embodiment shown in FIG. 2 includes the functional blocks 23L 233, 235, 237,
239, and the above-mentioned down reference timing correction circuit 60a, and the UTX 240b consists of the functional blocks 242 and 243, also explained in FIG. 3, and the above-mentioned uplink reference timing correction circuit 60b.

In this embodiment, the downlink received data (2) is obtained by extracting the preamble pulse inserted at the position shown in FIG. 6(D) by the downlink clock extraction circuit 233,
The downlink received data (2) is written to the downlink transfer circuit 231 at the timing of .

Next, the downlink received data ■ is transferred to the downlink clock transfer circuit 231
The station reference clock output from the oscillator 4ot■
By reading it out, the timing is changed to that of the internal reference clock (2), and the downlink received data (2) is sent to the elastic memory 235 and the synchronization pattern detection circuit 237.

Next, the synchronization pattern detection circuit 237 detects the downlink received data ■
' frame synchronization pulse (5YN shown in Figure 6(D)
Detect the synchronization pattern pulse from (inserted in C).

As a result, a load pulse for the downlink reference frame counter 239 is sent, and a write control signal (2) for downlink received data (2)' is sent out to the elastic memory 235, and the elastic memory 235 writes the downlink received data (2').

On the other hand, the downlink reference frame counter 239 sends a read control signal ■ to the elastic memory 235 using a load pulse.
At the same time, the downstream reference timing correction circuit 6
0a and creates the transmission timing of the downlink transmission data.

At this time, if there is a phase difference between the clocks ■ and ■, and the phase of the write control signal ■ detected by the synchronization pattern detection circuit 1B237 shifts by 1 bit before or after that of the previous frame (immediately, ■>■ or ■- (or ■≠■ depending on the accuracy of the oscillator 40b), the downlink reference timing correction circuit 60a corrects the downlink reference frame counter 239 to match the phase of the write control signal (2).

As a result of this correction, the deviated readout control signal
Timing correction is performed at the position of the guard bit (G) of the downlink frame shown in FIG.

2l- = 20- On the other hand, in the case of transmitting the uplink reception data (2), the signal (2) whose timing is sent out from the downlink reference frame counter 239 and delayed for a certain period of time by the delay adjustment circuit 251 is used as the upstream frame signal, and this is used as the base frame signal. The upstream frame counter 243 is operated.

If the downlink reference timing correction circuit 60a corrects the downlink reference timing by 1 bit, the signal ■ will also shift by 1 bit, so the uplink reference timing correction circuit 60b
performs correction processing to match the signal ■ which is shifted by one bit.

With this correction, the elastic memory 23 for upstream data
The timing of the successive control signal ■ of No. 6 is shifted in the same way as above, but since the guard bit (G) is also inserted in the upstream frame as shown in FIG. ), the timing is corrected and the correct uplink transmission data ■“ is transmitted to the upper layer.

As described above, in this embodiment, since the transmission timing is corrected at each relay station 2(i) and data is relayed, jitter is not accumulated in the clock, and high-quality data can be relayed in multiple stages. becomes possible.

〔Effect of the invention〕

According to the present invention as described above, it is possible to provide a multi-stage relay system capable of relaying high-quality data in multiple stages.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a block diagram explaining a conventional example, and FIG. 4 is an overview of the configuration of a multi-stage relay station. FIG. 5 is a diagram illustrating an overview of the system configuration of multi-stage relay, and FIG. 6 is a diagram illustrating the frame format of data in the =Sa section. In the figure, 1 is the base station, 2(j) is the relay station, and 3(i)
is the terminal station, 4 is the concentrator, 5 is the exchange, 11 is the CPU, 12, 2L22,
31 is TRX, 13 is speed/formant converter, 14.24a is DTX, 15.23b,
230b is URX. 23a, 32, 230a are DRX, 24b, 35
, 240b is UTX, 25.34 is DL C0NT,
26.33 is C0NT. 27, 36 are INTF, 30.30' is synchronization detection means, 40a is CLK G
EN, 40b is an oscillator, 50.50' is a data delay means, 60.60' is a down/up reference timing correction means, 60a, 60b is a down/up reference timing correction circuit, 231.232 is a down/up cross transfer circuit. , 23
3.234 is a downstream/upstream clock extraction circuit, 235, 2
36 is an elastometer memory, 237.238 is a synchronization pattern detection circuit, 239.243 is a downlink/uplink reference frame counter, 241.242 is a downlink/uplink transmission data control circuit, 251 is a delay adjustment circuit, 261 is a CI"U
Control circuit; 271 is a terminal interface; 410 is a reference clock generation circuit; FIG. 1 is a block diagram illustrating the present invention in detail;

Claims (1)

[Claims] In a time division multiplex communication system in which data is relayed in multiple stages between a base station and a terminal station via a plurality of relay stations, synchronization detection means (30,
30') and the frame synchronization pulse detected by the synchronization detection means (30, 30') as a data write timing pulse ([5]
, [5]'), and the received data ([1]
]', [2]') are the timings ([6]
, [8]) and the data write timing pulse (5) sent from the synchronization detection means (30), and generates the downlink reference timing. Downlink reference timing correction means (60) that corrects the reference timing in the direction of the deviation when the clock extracted from the received data and the station reference clock are asynchronous and a timing difference occurs; and the downlink reference timing correction means (60). The timing obtained by delaying the timing (8) output from If a timing different from the data frame corrected by the downlink reference timing correction means (60) is input, the uplink reference timing correction means (60') corrects the reference to the shifted timing. In preparation for this, when the data transmitted in frames is relayed through the relay station, a phase shift occurs when the relay station switches from the clock extracted from the preamble pulse included in the received data to the internal reference clock. If that occurred,
A data multi-stage relay system characterized in that the downlink reference timing correction means (60) and the uplink reference timing correction means (60') perform correction processing and transmit the corrected data to the next stage.