JP2001119362A - Control time slot switching circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a control time slot(CLTS) switching circuit, with which no deviation occurs in the position relation of a main signal and a CLTS multiframe. SOLUTION: This circuit is composed of a 1.5MHWY terminating circuit 12 for terminating a 1.5M transmission line signal, CLTS terminating circuit 13 for terminating a CLTS, processing circuit 14 for adding a supervisory and control bit, CLTS generating circuit 15 for generating the CLTS, multiplexing circuit 16 for multiplexing the 1.5M transmission line signal, 6MHWY generating circuit 17 for generating a 6M transmission line signal, timing correcting circuit 18 for correcting the deviation, first memory 19 for delaying the intra-device transmission delay component of the CLTS, first SEL 20 for exchanging the CLTS, first timing generating circuit 21 for generating exchange timing, second memory 22 for holding the CLTS, second SEL 23 for exchanging the supervisory and control bit, and second timing generating circuit 24 for generating exchange timing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control time slot (hereinafter referred to as "CLTS") relay circuit, and more particularly, to a method in which a CLTS is provided in a main signal in a low-speed side transmission device and used as a monitoring control time slot. The CLT
A CLTS relay circuit that enables remote monitoring control between high-speed transmission devices by using the spare bit of S.

[0002]

2. Description of the Related Art In digital communication, generally, a time slot (hereinafter, referred to as TS) for supervisory control is prepared in a transmitted / received signal so that supervisory control between remote transmitting apparatuses can be performed. ing. As one of the methods, there is a case where a part of a main signal is assigned as a TS for monitoring and control. Hereinafter, in order to monitor and control a device installed by a user remotely from an opposing station device, a CL signal is assigned to the main signal.
An example in which a multi-frame monitoring control TS called a TS is multiplexed to perform remote monitoring control will be described.

FIG. 4 is a diagram showing a configuration example of a conventionally used remote monitoring control method for a transmission apparatus. The figure shows
A user setting device having a transmission rate of 1.5 Mb / s was used as the low-speed device, and a user setting device was used as the high-speed device.
This is a case where a multiplexing device having a transmission speed of 6 Mb / s is used by multiplexing the devices, and an example in which a signal is transmitted from the user side to the station side is shown. The user side includes a user setting device 1a, 1b, 1c, 1d accommodating a plurality of subscriber lines, a CLTS 2 for generating or detecting a CLTS provided in the user setting device 1a, 1b, 1c, 1d; 1
a multiplexer 3 for multiplexing four systems a, 1b, 1c and 1d
And a multiplexing device 3 including a CLTS 4 for terminating a 1.5M transmission line signal and generating or detecting a CLTS, and a multiplexing converter 5 for multiplexing the four 1.5M transmission line signals into a 6M transmission line signal. Is provided.

On the other hand, on the station side, a 6
A separation converter 7 for separating the M transmission line signal into four 1.5M transmission line signals;
And a user setting device 9a, 9b, 9c, 9d that separates the 1.5M transmission line signal and outputs it to a plurality of subscriber lines.
And C provided in the user setting devices 9a, 9b, 9c, 9d
It comprises a CLTS 10 for generating or detecting an LTS and a monitoring control terminal 11.

The operation of FIG. 4 will now be described. The user setting devices 1a, 1b, 1c and 1d each accommodate a plurality of subscriber lines corresponding to various communication services, and generate and output 1.5M transmission line signals. I do. On the other hand, the user setting devices 1a, 1
b, 1c, and 1d, the CLTS2 uses the TS24 assigned to the main signal to perform CLT for monitoring and control.
Construct S. Next, four 1.5M transmission line signals are:
CLTS input to the multiplexer 3 and provided in the multiplexer 3
4 terminates each 1.5M transmission line signal to identify and separate the monitoring control bits constituting the CLTS. Further, the CLTS 4 uses the spare bits of the CLTS to transmit the monitoring control bits necessary for the multiplexer 3 to the CTS.
The LTS is added to the LTS, and a 1.5M transmission line signal is generated again.
The signal is converted to an M transmission path signal and output. Next, the 6M transmission line signal input to the multiplexer 6 on the station side is separated into four 1.5M transmission line signals by a separation converter 7 provided in the multiplexer 6. The separated 1.5M transmission line signal is CL
Termination processing is performed by the TS8, and monitoring control bits necessary for the multiplexer 6 are identified and separated.

The 1.5M transmission line signal is transmitted to the user setting device 9
a, 9b, 9c, and 9d, and separated and output to a plurality of subscriber lines. Also, the user setting devices 9a, 9b, 9c, 9
In the CLTS 10 provided for d, the CLTS is identified and the monitoring control bits assigned to the user setting devices 9a, 9b, 9c, 9d are separated. The separated bits are output to the supervisory control terminal 11 to monitor and control the user setting device including the multiplexing device described above.

FIG. 5 is a block diagram showing an example of a functional block on the transmitting side of a conventional multiplexer. The figure shows a 1.5 MHWY termination circuit 12 for terminating a 1.5 M transmission line signal,
A CLTS termination circuit 13 for terminating the LTS, a processing circuit 14 for adding a monitoring control bit of the multiplexer,
CLTS generation circuit 15 that generates
It comprises a multiplexing circuit 16 for multiplexing transmission path signals and a 6MHWY generation circuit 17 for generating 6M transmission path signals.

The operation of FIG. 5 will now be described.
The M transmission line signal establishes frame synchronization by the 1.5 MHWY termination circuit 12 and identifies the TS of the main signal. Next, C
In the LTS termination circuit 13, CL multiplexed with the main signal
The TS is separated to identify the multi-frame constituting the CLTS, and the processing circuit 14 adds a supervisory control bit required for the multiplexer to the spare bit of the CLTS. Further, the CLTS is reconstructed by the CLTS generation circuit 15 and multiplexed with the main signal to obtain a 1.5M transmission line signal.
At 6, the signal is multiplexed with a 1.5M transmission line signal of another system. After that, it is input to the 6MHWY generation circuit 17, generates a 6M transmission line signal according to a predetermined format, and outputs it to the transmission line.

[0009]

However, the conventional CLTS relay circuit described above has the following problems. That is, in order to add a supervisory control bit on the transmitting side of the multiplexing device, the CLTS multiframe is terminated and the supervisory control bit is discriminated and separated. At this time, the main signal and CLT are added.
A shift occurs in the positional relationship of the S multi-frame. This is because the 64 multiframes constituting the CLTS and the main signal are independent of each other, and the first of the 64 multiframes is started from an arbitrary position.
When reassembling the frame and adding it to the main signal, it is not possible to limit from which position the first of the 64 multiframes starts, and the positional relationship between the main signal and the CLTS multiframe held in the initial state is shifted. Become.

Therefore, the subscriber line service package accommodated in the user setting device is composed of a bit in the CLTS and a CL in the CLTS.
A type that operates at a timing using the multi-frame relationship of the TS cannot be used and causes a problem. For example, the audio channel package adopts a bit stealing method in which 8 bits allocated to a channel are allocated to 7 bits of audio for 6 frames and 1 bit for a signal is assigned to 7 bits of audio. The bit in the CLTS is used to obtain the timing described above, and the opposite device receives this bit and detects the bit steal position. At this time, C
If there is a shift in the positional relationship between the LTS multiframe and the main signal, an accurate bit steal position cannot be obtained.

The present invention relates to a conventional CLTS as described above.
The purpose of the present invention is to solve the problem of the relay circuit. Even if the termination and generation of the CLTS are performed in order to add a monitoring control bit to the CLTS in the multiplexing device, the positional relationship between the main signal and the CLTS multi-frame is maintained. An object of the present invention is to provide a CLTS relay circuit that does not cause a shift.

[0012]

To achieve the above object, a CLTS relay circuit according to the present invention has the following configuration.

[0013] First terminating means for terminating the transmission path signal output from the low-speed side transmission device, second terminating means for terminating the CLTS output from the first terminating means, and second terminating means. Means for adding a supervisory control bit required in the high-speed transmission device to spare bits in the CLTS having a separated multi-frame configuration, means for reconstructing the supervisory control bit into a predetermined CLTS and generating a transmission path signal, Means for multiplexing transmission path signals output from a plurality of low-speed transmission apparatuses and generating transmission path signals for a predetermined high-speed transmission apparatus. Means for delaying the transmission delay time of the relay circuit, and CLTS of the reconstructed transmission path signal
Selecting means for replacing the CLTS with the delayed CLTS, a memory means for temporarily holding the reconstructed transmission path signal and reading it at a predetermined timing, and a memory means for the CLTS output by the first selecting means. And a means for replacing only monitoring control bits necessary for the high-speed transmission device in the CLTS output by the low-speed transmission device.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on illustrated embodiments.

FIG. 1 shows a CLT of a multiplexer according to the present invention.
FIG. 4 is a configuration diagram illustrating an example of a transmission-side functional block that forms an S relay circuit.

FIG. 1 shows the 1.5 output from the user setting device.
1.5 MHWY termination circuit 12 for terminating M transmission path signal
A CLTS termination circuit 13 for terminating the CLTS multiplexed in the main signal, a processing circuit 14 for adding a monitor control bit required for the multiplexer to the CLTS multiframe, and a bit constituting the separated CLTS in a predetermined frame. CLTS generating circuit 15 reconstructing a 1.5M transmission line signal into a format, multiplexing circuit 16 for multiplexing four 1.5M transmission line signals, 6M transmission line signal according to a predetermined frame format from the multiplexed signal And a timing correction circuit 18 for correcting a shift between the main signal and the CLTS multiframe. Further, the timing correction circuit 18 extracts only the CLTS from the output signal of the 1.5 MHWY termination circuit 12 and delays the transmission delay in the device with a first memory 19 that replaces the CLTS. , A first SEL) 20, a first timing generation circuit 21 for generating a replacement timing of the first SEL 20, and a CLTS temporarily generated for replacing a supervisory control bit required in the multiplexer. The second memory 22 to be held, a second selection circuit (hereinafter referred to as a second SEL) 23 for exchanging monitoring control bits required by the generated multiplexing device, and a second selection circuit 23 for generating timing for exchanging monitoring control bits. The second timing generation circuit 24 is used.

The operation of FIG. 1 will be described. The 1.5M transmission line signal input from the user setting device establishes frame synchronization by the 1.5MHWY termination circuit 12 and identifies the TS of the main signal.

FIG. 2 shows a frame format of a 1.5M transmission line signal according to the present invention. Referring to the figure, a frame is composed of one F bit used for frame synchronization and the like, and a main signal of 24 TS composed of 8 bits. In this embodiment, TS 24 is used for monitoring and controlling. CLTS.

FIG. 3 shows a 64 multi-frame configuration of the CLTS according to the present invention. Referring to FIG.
The multi-frame is composed of 64 multi-frames having an 8-bit configuration, and each multi-frame is composed of a bit string for multi-frame synchronization, an alarm signal corresponding to each TS, and a bit for a control signal. The multi-frames 53 to 55 are areas allocated to the monitoring control bits of the multiplexing apparatus, and are spare bits in the CLTS multi-frame in the original user setting apparatus. In addition, b of CLTS
Bits 5 to b8 are bits provided for each channel board in the user setting device to use independently.

Next, the CLTS terminating circuit 13 terminates the CLTS multiplexed on the main signal and identifies the multi-frame constituting the CLTS. In the processing circuit 14, 53 bits of the multi-frame which is a spare bit among the bits constituting the identified CLTS multi-frame.
Monitoring control bits necessary for the multiplexer are added to b1, b2, b3, and b4 of the ~ 55 frames. Each bit constituting the CLTS multiframe processed by the processing circuit 14 is reconstructed into a predetermined CLTS multiframe by the CLTS generation circuit 15 and multiplexed with the main signal to form a 1.5M transmission path signal. At this time, the positional relationship between the main signal and the CLTS multi-frame is different from the initial state, and is shifted.

Therefore, the timing correction circuit 18 will be described. TS output from 1.5 MHWY termination circuit 12
24 is written in the first memory 19,
The intra-device transmission delay generated in the CLTS relay circuit is delayed. Next, the generated CLTS, which is the output of the CLTS generation circuit 15 that has reconstructed the CLTS after adding the necessary monitoring control bits to the multiplexer, is output from the CLTS read from the first memory 19 and the first SEL 20 by the first SEL 20. Replacement is performed according to the CLTS position replacement timing generated by one timing generation circuit 21. Further, the output of the CLTS generation circuit 15 is the generation C output from the CLTS generation circuit 15.
The LTS multiframe head signal (SSIG) is used to sequentially write the second memory 22 from the head of the multiframe. The second memory 22 stores a received CLTS multi-frame head signal (RSIG) output from the CLTS termination circuit 13.
The second CL generates only the monitoring control bits required by the multiplexing device other than the CLTS synchronization pattern output from the first SEL 20 by the second SEL 23 by reading the generated CLTS at the beginning timing.
Are switched to 1.5M transmission line signals according to the monitoring control bit replacement timing output by Note that the CLTS termination circuit 13 detects that the reception CLTS is out of synchronization with the CTREC.
Is detected, the first SEL 20 and the second SEL 23 are not switched, and the output of the CLTS generation circuit 15 is output to the multiplex conversion circuit 16 as it is.

Next, the operation of the timing correction circuit 18 will be described in more detail with reference to the flow of signals (1) to (4) shown in FIG. First, in order to keep the positional relationship between the main signal and the CLTS multi-frame in the initial state, it is possible to cope by keeping the synchronization pulse train of the CLTS multi-frame at the original position. Therefore, the synchronization pulse train of the CLTS multi-frame is a signal at the same timing as the original position.
The signal is output to the multiplex conversion circuit 16 via the signal,
On the other hand, the main signal is transmitted to the multiplexing circuit 16 via the first SEL 20 → signal → signal via the CLTS generation circuit 15.
Output to Here, since the signal is obtained by replacing the CLTS in the first SEL 20 with the CLTS output from the first memory 19, the main signal + CLTS is no different from that in the initial state, and the positional relationship between the two is shifted. Has not occurred. The signal is a signal to which a monitor control bit necessary for the multiplexer is added, and the positional relationship between the main signal and the CLTS is different from that in the initial state. Subsequently, the second SEL 23 outputs the CLT based on the timing at which the second timing generation circuit 24 outputs the signal based on a signal in which the main signal and the CLTS have not been displaced.
Only bits in the CLTS multiframe required by the multiplexing device other than the frame synchronization pulse train of the S multiframe are replaced. The second memory 22 holds signals in order to match the replacement timing. Therefore, the signal that becomes the 1.5M transmission line signal is the main signal and the C signal.
The positional relationship of the LTS multi-frame does not shift even if a monitoring control bit required for the multiplexer is added.

Next, the 1.5M transmission line signal whose timing has been corrected is input to the multiplex conversion circuit 16 by the other three systems.
It is multiplexed with M transmission path signals. After that, the data is input to the 6MHWY generation circuit 17 and the 6M
A transmission path signal is generated and output to the transmission path.

[0024]

As described above, according to the present invention, the main signal and the CL signal can be added to the spare bits of the CLTS generated by the user setting device, even if the necessary supervisory control bits are added to the multiplexing device.
Since the positional relationship between TS multi-frames is prevented from occurring, it is possible to use a subscriber line service package of a type that establishes timing using a CLTS such as a voice channel package in a user setting device. This is very effective in operating the transmission device.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of a transmission-side functional block constituting a CLTS relay circuit of a multiplexer according to the present invention.

FIG. 2 is a diagram showing a frame format of a 1.5M transmission line signal according to the present invention.

FIG. 3 is a diagram showing a 64 multi-frame configuration of the CLTS according to the present invention.

FIG. 4 is a diagram showing a configuration example of a conventionally used remote monitoring control method for a transmission device.

FIG. 5 is a configuration diagram illustrating an example of a transmission-side functional block of a conventional multiplexer.

[Explanation of symbols]

 1a, 1b, 1c, 1d: user setting device, 2 ·· CLTS unit, 3 ·· multiplexer, 4 ·· CLTS unit, 5 ·· multiplex converter, 6 ·· multiplexer, 7 ·· separation Conversion section, 8 CLTS section, 9a, 9b, 9c, 9d, user setting device, 10 CLTS section, 11 monitoring control terminal, 12 1.5 MHWY termination circuit, 13 CLTS termination circuit , 14 processing circuit, 15 CLTS generation circuit, 16 multiplexing circuit, 17 6 MHWY generation circuit, 18 timing correction circuit, 19 first memory, 20 first SEL, 21..first timing circuit, 22..second memory, 23..second SEL, 24..second timing generation circuit

Claims (1)

[Claims] A first terminating means for terminating a transmission path signal output by the low-speed side transmission device; a second terminating means for terminating a control time slot output by the first terminating means; Means for adding a supervisory control bit required in the high-speed transmission device to spare bits in a control time slot having a multi-frame configuration separated by the terminating means, and reconstructing and transmitting the supervisory control bit to a predetermined control time slot Means for generating a road signal;
Means for multiplexing transmission path signals output from a plurality of low-speed side transmission apparatuses and generating transmission path signals for a predetermined high-speed side transmission apparatus, wherein the signal output from the first termination means Means for delaying the transmission delay time of the control time slot relay circuit, first selection means for replacing the control time slot of the reconstructed transmission path signal with the delayed control time slot, and the reconstructed A memory means for temporarily holding a transmission path signal and reading it out at a predetermined timing; and a control time slot output by the first selecting means, and a monitoring control required by the high-speed transmission device in the control time slot output by the memory means. A means for exchanging only bits and constructing a transmission path signal of the low-speed transmission device; A control time slot relay circuit comprising: