JPH01155563A - Optical recording and reproducing system - Google Patents

Abstract

PURPOSE:To improve reliability by inputting the detection signal of a clock pit as a reference signal, and constituting the phase comparison means of a phased locked loop (PLL) circuit inputting a detection signal of a clock pit as a reference signal and generating the clock for data reproduction and recording of a recording medium in which the clock pit within a servo area is arranged by means of delay elements. CONSTITUTION:The phase comparator 11 used in a frequency multiply PLL circuit is composed of the delay elements 40 and 41 which are connected in serial, a latch register 42 and a data encoder 43. The pattern recognition circuit of the peripheral condition of the reference clock pit is provided. Only when the recognition circuit recognizes that the clock pit is accurate, the encoder output signal of the phase comparator 11 is used as an oscillation control signal. Thus, a more stable channel clock can be generated with respect to the fault of the detection reference clock without damaging resolution and responsibility, and reliability is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an optical recording and reproducing method for a sample format optical disk device.

[Conventional technology]

The conventional clock generation method using the frequency multiplication method compares the detected reference clock pit with the output of the frequency divider, as described in JP-A-62-140517, and if the output of the frequency divider is If it is ahead of the bit, it is up.
The down counter is decremented (-1) L, and conversely, if the frequency divider output is delayed, the counter is incremented (-1).
+1), and the oscillation frequency was controlled using the value of the up/down counter.

In addition, an invention that addresses the defect in the detection reference clock using the conventional analog method, that is, a method in which the phase comparison result is used to charge and discharge an integrating circuit via a charge pump circuit to control the oscillation frequency, is disclosed in Japanese Patent Laid-Open No. 61 -214868 etc.

[Problem that the invention seeks to solve]

The above-mentioned conventional technology takes into consideration the characteristics required for the channel clock of a sample format optical disk, such as resolution in nanoseconds (10-0 seconds), fast response, and defects in the detection reference clock. However, there were problems with improving the performance and reliability of the device.

The purpose of the present invention is to provide a digital method suitable for LSI implementation, while providing a channel that is more stable against defects in the reference clock for detection without sacrificing resolution or responsiveness compared to conventional analog methods. The purpose is to generate a clock.

[Means for solving the problem] The above purpose is to configure a phase comparator used in a frequency multiplication PLL circuit with a delay element, a latch register, and a data encoder connected in series, and to This is achieved by having a pattern recognition circuit, and when the recognition circuit recognizes a correct clock pit, the encoder output signal of the phase comparator is used as the oscillation control signal.

[Effect]

The PLL circuit, which has a phase comparator using a delay element, has high resolution of nanoseconds or less and high-speed response.In addition, when a reference clock pit cannot be found, the phase difference signal information can be held using a binary digital signal. It will be done in As a result, the channel clock generation circuit that uses the clock pit recorded on the track as the reference clock input, including the D/A converter, is completely
It becomes possible to use Si, and even in the case of pit defects, it becomes possible to eliminate the method of holding unstable analog information and to use digital processing, which makes it possible to guarantee stable operation.

〔Example〕

First, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 2 shows the overall configuration of a sample format optical disk device according to this embodiment. A laser beam emitted by a semiconductor laser 1 is shaped by a lens 2, polarized by a polarizing beam splitter (PBS) 3, and focused onto a predetermined position on an optical disk 5 by an objective lens 4' built into a two-dimensional actuator 4. The reflected light from the optical disk 5 containing brightness information passes directly through the polarizing beam splitter 3 and illuminates the detector 6 . The detector 6 outputs a current proportional to the amount of irradiated light, and the current/voltage conversion amplifier 7 converts the RF
The signal becomes 20. The tracking information and focus information included in the RF signal 2o are sent to the sample servo circuit 1.
6 drives the two-dimensional actuator 4 and functions to track the center of the track and maintain the optimum focus state. On the other hand, the RF signal 20 is turned into a pit signal 21 indicating the pit center on the disk by the pit position detection circuit 8, and is inputted to the clock pit extraction circuit 9 and the pattern recognition circuit 1o. Pattern recognition circuit 1
The timing circuit 70 obtains the synchronization signal 69 obtained at
The clock pit signal 22 extracted by the clock bit extracting circuit 9 using the clock pit gate signal generated in is inputted as a reference clock to the phase comparator 11.

The binary phase information detected by the phase comparator 11 is set in the holding circuit (register) 12 only when the reference clock inputted to the phase comparator 11 is normal or extracted from the lock pit, and is passed through the digital low-pass filter (LPF). 1
3, the signal is integrated and low-pass processed to control the oscillation frequency of a voltage controlled oscillator (VCO) 14 using a DA converter method. The output of the VCO 14 is data R/W.
The clock (channel clock) becomes 25, and at the same time the counter 15 counts 1/N (in this example, 1/270).
) is the comparison signal input to the phase comparator 11. The optical disc 5 is controlled to rotate at 30 revolutions per second by driving a DC motor 17 by a motor control circuit 18.

FIG. 3 shows the format of the optical disc 5 used in the embodiment shown in FIG. FIG. 3(a) shows a state in which the circumferential direction of the disk 5 is divided into N equal parts (1376 equal parts in the embodiment), each called a servo sector, and FIG. 3(b) shows the inside of the servo sector. Servo bite (servo area)
32 and data bytes (data area). The servo byte 32 contains all of the servo information of the optical disk, and also includes a clock pit for a reference clock signal.

FIG. 4 shows an operation time chart of the servo cutting tool 32. This will be explained below with reference to FIGS. 2 and 3. The track of the servo bite 32 includes pits (wobble pits) 30-1 and 30-2 distributed in a staggered manner from the center of the track up and down for obtaining tracking information, as well as tallock pits 31 for obtaining a reference clock.
Further, the space between the wobble pit 30-2 and the clock pit 31 is a part of the mirror for obtaining focus information. The RF signal 20 (output of the current/voltage conversion amplifier 7 in FIG. 2) indicates a state in which the reflectance is lowered at the pre-pit portion. The tracking gate signal, A/F (autofocus) gate signal, and clock pit gate signal (Fig. 2, output signal group of the timing circuit 70) are extraction gates for obtaining the necessary information for each. This is the extraction period. By taking the AND of the pit signal 21 detected by the pit position detection circuit 8 in FIG. 2 and the clock gate signal, the clock pit signal 22 shown in this figure is obtained, and the phase of the R/W clock (channel clock) 25 is It serves as a timing signal to match.

The channel states that change according to the channel clock 25 are 0 to 269, of which 0 to 239 are data bytes (data area) and 240 to 269 are servo bytes (servo area) (see Figure 3). .

FIG. 1 is a block diagram embodying the PLL type frequency multiplier circuit portion, particularly the phase comparator 11, in the embodiment of FIG. 2, and FIG. 5 is a time chart showing the operating state of the multiplier circuit. FIG. 1 will be explained below with reference to FIG. 5. The R/W clock generated by the voltage controlled oscillator 14 (
channel clock) 25 to 270 by counter 15
The output signal 24 whose frequency has been divided by a factor of 1 is input to a first delay circuit 40 having n delay elements each having a value of Δ seconds connected in series.

The output signal 55 is input to a second delay circuit 41 having the same configuration as the first delay circuit 40. The first delay circuit 40 generates a signal 5o, 2×
A signal 51.3x Δ with a second delay, a signal 52 with a second delay of Δ, and a signal 53 with a second delay of (n-2)XΔ. (n-1)X
A signal 54 with a second delay of .DELTA. and a signal 55 with a second delay of n.times..DELTA. are outputted in order (FIG. 5 a-f), and are used as upper data input signals of the latch register 42, respectively. Also, the second
Similarly, the delay circuit 41 sequentially delays Δ with respect to the input signal 55 as a second-delayed signal 56.2×Δ with a second-delayed signal 57, and outputs (n-2)XΔ with a second delay. signal 58, (
n-1) In order to output XΔ as a second-delayed signal 59 and finally nXΔ as a second-delayed signal, input them to the lower side of the latch register 42. At this time, the clock pit signal 22 is input to the latch register 42, the signal propagation state into the delay circuit at that point is set in the register 42 (in FIG. 5, Ω
At the rising edge of the clock pit signal 22 indicated by m extracted from the RF signal 20 indicated by , the state of a''k is set as indicated by n).Signal propagation of delay circuits 40 and 41 set in register 42 The data indicating the state is converted into a binary code (or Gray code) by the encoder circuit 43, and becomes the data input of the latch register 12 that stores only information based on the correct clock pit. delay circuit 40
Assuming that the state propagated to the final output 55 is the timing at which the phase is locked (the state shown in the time chart in FIG. 5), the encoder 43 has the upper side of the latch register 42 all LL I I + and the lower side all It O
11, it is determined as ±O, and the state where "OI' exists on the upper side of the latch register 42 is determined to be positive (advanced phase), and conversely, the state where It I It is on the lower side is determined to be negative (lag phase). , and output the corresponding code. Only when the clock pit signal 22 described above is correct information, the output data QO"Q7 of the encoder 43 is set in the register 12 by the pattern pass signal 23 output from the pattern recognition circuit. Data outputs 20 to 27 of the register 12 above
is input to the digital filter 13, digitally integrated (added/subtracted) for each frequency-divided output signal, and further subjected to low-pass processing. By varying the output value of the DA converter 44, the oscillation frequency of the voltage-controlled oscillator 14 and control, and the phase control loop (PLL) is closed. Note that instead of the voltage controlled oscillator 14, the
This method can also be realized by adopting the capacitor switching method described in No. 140517, and it is also possible to replace the arrangement of the latch register 42 and encoder 43 to reduce the number of register bits. It is possible.

Figure 6 shows the digital filter (LPF) shown in Figure 1.
13 shows a concrete block diagram. Adder/subtractor 61
．． Register 62-1.62-2, multiplier 63-0.63
-1.63-2 and an adder 64. The outputs 2° to 27 of the register 12 are added to and subtracted from the previous data u(nT-T) by the adder/subtractor 61 to obtain the current data u(nT). The current data u(nT) is multiplied by ao by the multiplier 63-0, and the previous data u(nT-T
) is multiplied by 31 by the multiplier 63-1, the data u(nT-2T) from the previous time is multiplied by az by the multiplier 63-2, and the respective multiplication results are added by the adder 64,
Obtain filter output data QO to Q7. At this time, it is also possible to obtain a high-order filter output by increasing the number of stages of registers and multipliers.

FIG. 7 shows a second embodiment of the present invention, in which a fast-in/first-out (Fi
Fo) It has a configuration in which a memory 65 is added, and is a test device for clock pits placed in advance in the servo area. The phase difference information input to the FiFo memory is sequentially read into the personal computer 66, which executes frequency analysis calculations and outputs the results to the X/Y plotter 67.

As described above, according to this embodiment, the PL is fully digitalized.
The L-type multiplier circuit enables the creation of a channel clock generation circuit that has high resolution and high-speed response and is not affected by defective pits such as dropouts, providing a highly reliable sample format optical disk device. This has the effect of making it possible to do so. In addition, in the second embodiment, compared to the case where a conventional analog PLL circuit is used, one phase difference information is a digital signal, and it is possible to directly perform calculations such as Fourier calculations, which improves the accuracy of the measuring instrument. Effective in improving reliability.

〔Effect of the invention〕

According to the present invention, a channel clock can be generated using a PLL type multiplier circuit implemented as an LSi, so that an inexpensive and highly reliable system can be constructed.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a PLL type N multiplier circuit using delay elements used in the present invention, FIG. 2 is an overall configuration diagram showing a first embodiment of the present invention, and FIG. 3 is an embodiment of the embodiment of FIG. 2. Figure 4 is a diagram showing the timing in the servo area, Figure 5 is a timing diagram to explain the operation of Figure 1, and Figure 6 is the embodiment of Figure 2. The block diagram of the digital filter used, FIG. 7, is the second embodiment of the present invention.
FIG. 2 is a partial configuration diagram showing an embodiment of the present invention. 1... Semiconductor laser, 5... Optical disk, 7...
Current/voltage conversion amplifier, 8... pit position detection circuit,
1°...Pattern recognition circuit, 11...Phase ratio softener,
12... Holding circuit (register), 13... Digital filter (LPF), 14... Voltage controlled oscillator, 1
5... Counter, 31... Glock pit, 40.
41...Delay circuit, 42...Latch register, 43
...Encoder Figure 1 Figure Z Figure 3 (cL) Figure 3 (b) Figure 5 Figure 6

Claims (1)

[Claims] 1. Using a recording medium having tracks in which servo areas and data areas are alternately arranged along the scanning direction, and in which clock pits are arranged in advance in the servo area, the clock A phase comparison means of a phase locked loop (PLL) circuit which inputs a pit detection signal as a reference signal and generates a clock for data reproduction or data recording on the recording medium is constituted by a delay element. Optical recording and playback method. 2. A recognition circuit is provided for determining whether or not the reference signal clock pit of the PLL circuit is correctly detected, and when the recognition circuit detects a defect in the clock pit,
2. The optical recording and reproducing system according to claim 1, wherein the output data of the phase comparison means is held digitally without being updated. 3. A digital output value indicating the phase comparison result of the PLL circuit is frequency-analyzed to check the embedding status of the clock pit.
An optical recording and reproducing method according to claim 1.