JPH10112141A - Pll circuit and optical device provided therewith - Google Patents

Abstract

PROBLEM TO BE SOLVED: To permit a PLL circuit to stably operate without following up read data of low reliability by controlling operation of a frequency comparator according to degrees of reliability of read data signals. SOLUTION: When a read-head of an optical disk reproducing device passes above a track of a disk, an amplitude of RF signal 1 is higher than a specified value and constant if the disk has no defects. If read data signal 3 is also high in the reliability and a first voltage control oscillator 11 is controlled based on the output results of a frequency comparator 7 and a phase comparator 5, the output of the voltage control oscillator 11 is locked at the read data signal 3, and the read data are reproduced. Next, in a case of a defective disk, an upper side amplitude of RF signal 1 becomes small the read data signal 3 of an output of a digitizing circuit 2 outputs a low level signal. An envelope detection circuit 4 detects this and outputs a defect detection signal 12. As a result, the state at locking immediately before the defect is maintained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (Phase Locked Loop) circuit for reproducing a read clock from a read data signal read from a recording medium in an optical disk device, for example, and more particularly to a PLL (Phase Locked Loop) circuit which does not receive an input signal from the recording medium. The present invention relates to a PLL circuit that stably follows a stable case.

[0002]

2. Description of the Related Art As shown in FIG. 4, a block of an optical disk apparatus includes a pickup 23 for reading data from a recording medium 22 (hereinafter referred to as an optical disk), a preamplifier 24 for amplifying an output of the pickup 23, and a preamplifier 24. And a digital signal processing unit 25 including a PLL block and an error correction block for generating a read clock synchronized with the output of the digital signal, and a servo for controlling rotation of a disk based on the binary signal. A processor section 26; and a spindle motor 31 for rotating a disk in accordance with an output result of the servo processor section 26.
A D / A converter 27 that converts an output of the digital signal processing unit 25 into an analog value and outputs audio data 30;
It comprises a ROM decoder 28 which converts the output of the digital signal processor 25 into digital data 29 which can be processed by a personal computer or the like.

As shown in FIG. 3, a PLL block for reproducing a read clock from a read data signal output from the preamplifier 24 includes a voltage controlled oscillator 11 for outputting an oscillation signal having a frequency corresponding to an input signal, and a voltage controlled oscillator. And a read data signal 3 obtained by binarizing the RF signal 1 read from the recording medium of the optical disk device via the preamplifier 24, and outputs a control signal corresponding to the phase difference. A phase comparator 5, a first charge pump 6 for charging or discharging electric charge according to the comparison result of the phase comparator 5, and a period between adjacent transition points of the read data signal 3 at an output 14 of the voltage controlled oscillator. The frequency at which the read data signal 3 is compared with the frequency of the voltage-controlled oscillator 11 by counting and a control signal corresponding to the frequency difference is output. Comparator 7, a second charge pump 8 that charges or discharges electric charges based on the comparison result of the frequency comparator 7, and an addition circuit 9 that adds the first charge pump output and the second charge pump output. , And a loop filter 10 which receives the output of the adder 9 as an input. According to this configuration, when the synchronous clock necessary for reading the read data signal 3, that is, the output 14 of the voltage controlled oscillator is higher than a desired value, the control signal is output from the frequency comparator 7 and the second charge The pump 8 discharges the charge, and the output voltage of the loop filter 10 drops. As a result, the output frequency of the voltage controlled oscillator 11 decreases. When the synchronous clock required for reading the read data signal is lower than a desired value, a control signal is output from the frequency comparator 7 and the second charge pump 8
Is charged, and the output voltage of the loop filter 10 rises. As a result, the output frequency of the voltage controlled oscillator 11 increases. With such an operation of the frequency comparator 7, the output frequency of the voltage controlled oscillator 11 is pulled into the capture range of the phase comparator 5. On the other hand, the phase comparator 5 compares the phase of the synchronous clock with the phase of the read data signal 3, and when the phase of the synchronous clock advances with respect to the read data signal 3,
The control signal is output from the phase comparator 5, the first charge pump 6 discharges the electric charge, and the output voltage of the loop filter drops. As a result, the output frequency of the voltage controlled oscillator 11 decreases. When the phase of the synchronous clock lags behind the read data signal 3, a control signal is output from the phase comparator 5, the first charge pump 6 charges the electric charge, and the output voltage of the loop filter 10 rises. As a result, the output frequency of the voltage controlled oscillator increases. Thus, the output frequency of the voltage controlled oscillator 11 is pulled into the capture range of the phase comparator 5 by the control signal from the frequency comparator 7,
Thereafter, the phase comparator 5 operates so that the output of the voltage controlled oscillator 11 and the phase of the read data signal coincide.

[0004]

In the above-described PLL circuit configuration, the head for reading a signal from the optical disk performs an operation of crossing tracks of the optical disk at a high speed (hereinafter referred to as a seek operation), or when the power of the optical disk is turned on. If the rotation is unstable, or if there is an incomplete area such as a scratch or a defect on the optical disc, the period of the adjacent transition point of the read data signal is significantly different from the original period. The frequency is pulled to a frequency that is significantly different from the desired frequency, and the PLL output during operation such as the seek operation becomes unstable. Therefore, even if the rotation of the optical disk and the operation of the head are restored to a stable state, the operation of the PLL is unstable, so that it takes time to return to a stable state, which hinders the improvement of the access time of the optical disk reproducing apparatus. .

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problem by detecting the reliability of the read data signal. It is an object of the present invention to provide a PLL circuit which can improve the access time of an optical disk reproducing apparatus by operating stably without leaving a large distance.

[0006]

According to the present invention, a mirror portion and a defective portion of a disk are detected from an RF signal read from an optical disk, and a decrease in the reliability of a read data signal is detected. Suspends the operation of the detector and prevents the PLL from following the low-reliability read data signal, and outputs the same frequency to the defect part generated during the steady state.
The operation of the PLL circuit in the defect and mirror unit is stabilized by applying the control voltage of the LL voltage controlled oscillator to the first PLL voltage controlled oscillator.

FIG. 5 shows the envelope waveform of the RF signal at the mirror section and the defect section. The mirror section is an area where no data exists between the tracks on the disk, and the lower value of the envelope signal at this time is higher than usual, so that a mirror signal can be generated by detecting this. Also, a defect portion is an area where data is inaccurate or incomplete due to a scratch or a defect on the disc on the track of the disc, and the upper value of the envelope signal at this time is lower than usual, so this is detected. Thus, a defect signal can be generated.

According to a first aspect of the present invention, there is provided a PLL circuit which outputs an oscillation signal having a frequency corresponding to an input signal, an output signal of the voltage control oscillator, and an RF signal read from a recording medium. A phase comparator for detecting a phase difference with a data signal obtained by binarizing the data signal, and outputting a comparison result according to the phase difference; and a first charge pump for charging or discharging electric charge based on the comparison result of the phase comparator. And counting the period of the adjacent transition point of the data signal with the output of the voltage controlled oscillator, comparing the data signal with the oscillation signal output by the voltage controlled oscillator, and according to the frequency difference. A frequency comparator that outputs a comparison result, a second charge pump that charges or discharges an electric charge according to the comparison result of the frequency comparator, and a first charge pump output. An adder circuit for adding the serial second charge pump output, a first loop filter for outputting the input signal as an input the output of said adder circuit, said RF
A detection circuit for detecting a period in which a transition point adjacent to a data signal obtained by binarizing the signal is different from the original period and outputting a detection signal, wherein the frequency comparator outputs The comparison result is controlled based on the detection signal.

A PLL circuit according to a second aspect of the present invention is the PLL circuit according to the first aspect, wherein the detection circuit receives the RF signal as input and detects a mirror portion of the recording medium. .

The PLL circuit according to a third aspect of the present invention is the PLL circuit according to the first aspect, wherein the detection circuit detects a defect portion of the recording medium by using the RF signal as an input. .

The PLL circuit according to a fourth aspect of the present invention is characterized in that, in the PLL circuit according to the first aspect, the detection circuit detects based on an envelope of the RF signal. In a PLL circuit for generating a clock signal synchronized with an RF signal read from a recording medium, the frequency of the RF signal is compared with the frequency of the clock signal. A frequency comparator, means for detecting an incomplete part of the recording data of the recording medium based on the RF signal, and means for holding an output of the frequency comparator during detection of the incomplete part, During the holding operation, the tracking of the RF signal is stopped.

A PLL circuit according to a sixth aspect of the present invention is the PLL circuit according to the first aspect, wherein the second voltage-controlled oscillator outputs an oscillation signal having a frequency corresponding to the second input signal; A phase frequency comparator for detecting a frequency difference and a phase difference between the output signal of the voltage controlled oscillator and the reference clock and outputting a comparison result according to the frequency difference and the phase difference; and a charge based on the comparison result of the phase frequency comparator. A third charge pump that charges or discharges the voltage, a second loop filter that smoothes the output of the third charge pump and outputs the second input signal to control the voltage controlled oscillator, and the defect signal And the output of the second loop filter is input to the addition circuit via the switch circuit while the defect signal is being output. Is characterized by comprising been added.

[0013] The optical disk device according to claim 7 is
A PLL circuit according to claim 1 or 5 or 6 is provided.

With such a configuration, the PLL circuit according to any one of the first to fifth aspects of the present invention can reliably operate the frequency comparator when the rotation of the optical disk is unstable, such as during a seek operation or when the power is turned on, or when the optical disk has scratches or defects. A stable output frequency immediately before can be maintained without following a low-reliability read data signal. Therefore, when the read data signal switches from a low-reliability state to a high-reliability state, the PLL is quickly applied to the read data signal. The circuit can be drawn in, and it contributes to the improvement of the access time of the optical disk device according to the seventh aspect.

With this configuration, the PLL circuit according to the sixth aspect of the present invention also has a reliable frequency comparator when the rotation of the optical disk is unstable, such as during a seek operation or when power is turned on, or when there is a scratch or defect on the optical disk. Outputs a frequency near the output frequency in a steady state without following a low-reliability read data signal, so that when the read data signal switches from a low-reliability state to a high-reliability state, the read data signal quickly In this case, a PLL circuit can be drawn in, and the access time of the optical disk device can be improved.

[0016]

FIG. 1 is a block diagram showing a configuration of a PLL circuit according to a first embodiment of the present invention. In this figure, 1 is an analog RF signal read from the optical disk. Reference numeral 2 denotes a binarization circuit for binarizing the RF signal 1, and reference numeral 3 denotes a read data signal binarized by the binarization circuit 2, for example, in a compact disc (hereinafter referred to as a CD), EFM (Eight to Fourteen Mo).
(duration) signal, which is an NRZI signal having a period of 3T to 11T. Reference numeral 4 denotes an envelope detection circuit which holds the maximum value and the minimum value of the amplitude of the RF signal 1 to detect an envelope and outputs information on a mirror portion and a defect portion of a disk. Reference numeral 5 denotes a read data signal 3 and a first voltage controlled oscillator. 11 is a phase comparator for comparing the phases of the outputs, 6 is a first charge pump for charging or discharging electric charges according to the comparison result of the phase comparator 5, and 7 is an adjacent transition point of the binarized read data signal 3. Of the voltage controlled oscillator 11
The frequency comparator 8 compares the frequency of the read data signal 3 with the frequency of the voltage controlled oscillator 11 and outputs a control signal according to the frequency difference. Second to discharge
A charge pump 9; an adder circuit for adding the output of the first charge pump 6 and the output of the second charge pump 8;
Reference numeral 10 denotes a first loop filter that smoothes an input signal and controls a voltage controlled oscillator 11, and 11 denotes a first voltage controlled oscillator controlled by an output of the loop filter 10.

Next, the EFM signal will be briefly described.
FIG. 6 is a diagram illustrating a phase relationship between the EFM signal and the synchronous clock. The EFM signal has a maximum period of 11T and a minimum period of 3T.
In the NRZI signal, the period TMAX, TMIN, TA between adjacent transition points of the EFM signal is counted at the output of the PLL, and the frequency comparison between the EFM signal and the PLL output can be performed by detecting the maximum value TMAX. In a state where synchronization is established as shown in FIG. 6, the maximum value of the count value is 11.

Next, the operation of the embodiment shown in FIG. 1 will be described. When the signal read head of the optical disk reproducing device passes over the track of the disk and the disk has no defect due to scratches or defects, the amplitude of the RF signal 1 is larger than a specified value and is constant. Therefore, the read data signal 3 has high reliability, and if the first voltage controlled oscillator 11 is controlled based on the output of the frequency comparator 7 and the output of the phase comparator 5, the first voltage controlled oscillator The output of 11 is locked so that the read data signal can be reproduced.

Next, when the signal read head of the optical disk reproducing device passes over the track of the disk, and a defect is present on the track due to a scratch or defect on the disk, the upper amplitude of the RF signal 1 becomes small. The read data signal 3, which is the output of the binarization circuit 2, is a low-level signal. In addition, the envelope detection circuit 4 uses R
It detects that the upper amplitude of the F signal 1 has become smaller and outputs a defect detection signal 12. As a result, the read data signal 3 including the low level period longer than the expected value is input to the frequency comparator 7, but the frequency comparison operation is stopped by the defect detection signal 12, so that the second charge pump 8 Output does not charge or discharge, and retains the locked state immediately before the defect. Further, since there is no change point of the read data signal 3 to be compared in the phase comparator 5, this also holds the state at the time of locking immediately before the defect. Accordingly, the output of the loop filter 10 also has the voltage value at the time of locking immediately before the defect, and
The output frequency of LL does not follow the read data signal 3 at the time of the defect, and holds the frequency at the time of the lock immediately before the defect until the next highly reliable read data signal is input. Next, when a highly reliable read data signal is input after passing through the defect on the disk, the defect signal 12 is released and the phase comparator 5 and the frequency comparator 7 are released.
Resumes operation, and the PLL output frequency immediately follows the read data signal and locks.

Next, when the signal read head of the optical disk reproducing device is passing through the mirror portion of the disk due to the seek operation, the lower amplitude of the RF signal 1 becomes small, and the read data signal output from the binarization circuit 2 becomes smaller. 3 outputs a high-level signal. The envelope detection circuit is RF
When the lower amplitude of the signal 1 is detected to be small, a mirror detection signal 13 is output. As a result, the read data signal 3 including the high-level period longer than the expected value is input to the frequency comparator 7.
3, the frequency comparison operation is stopped, so that the output of the second charge pump holds the lock state immediately before the mirror. Further, since there is no change point of the read data signal 3 to be compared in the phase comparator 5, this also holds the state at the time of locking immediately before the mirror. Therefore, loop filter 1
Since the output of 0 becomes the voltage value at the time of locking immediately before the mirror, P
The output frequency of LL does not follow the read data signal 3 at the time of mirroring, and holds the frequency at the time of locking immediately before the mirror until the next highly reliable read data signal is input.
Next, when a highly reliable read data signal is input after passing through the mirror portion of the disk, the mirror detection signal 13 is released, and the phase comparator 5 and the frequency comparator 7 resume operation and the PLL is started.
The output frequency immediately follows the read data signal and locks.

FIG. 2 shows a second embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of an LL circuit. 2, the blocks having the same functions as those of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. An external reference signal 15 is determined so that the output frequency of the second voltage controlled oscillator 19 becomes the same as that of the first voltage controlled oscillator 11. Reference numeral 16 denotes a phase frequency comparator for comparing the phase and frequency of the external reference signal 15 and the output 21 of the second voltage controlled oscillator 19. Reference numeral 17 denotes a third charge pump for charging or discharging an electric charge according to the comparison result of the phase frequency comparator 16, and reference numeral 18 denotes a voltage controlled oscillator 1 for smoothing an input signal.
A second loop filter 19 for controlling 9, a voltage controlled oscillator 19 controlled by the output of the loop filter 18, and its electrical characteristics are the same as those of the first voltage controlled oscillator 11. Reference numeral 20 denotes a switch circuit controlled by the defect detection signal 12.

Next, the operation of this embodiment will be described. As described with reference to FIG. 1, when the information of the mirror or the defect is detected from the RF signal, the input / output of the first loop filter 10 holds the voltage immediately before the information of the mirror or the defect is detected. Here, only when a defect is detected, instead of holding the voltage in the first loop filter 10 block, the switch circuit 20 is turned on and the output voltage of the second loop filter 18 is input to the addition circuit 9. At this time, as in the first embodiment, the operation of the frequency comparator 7 is stopped, and the phase comparator 5 is stopped because there is no change point of the read data signal 3, and the first charge pump 6 and the first charge pump 6 are stopped. The output of the second charge pump 8 becomes high impedance. First voltage controlled oscillator 1
The first and second voltage controlled oscillators 19 oscillate at substantially the same frequency, and have substantially the same characteristics when formed on a semiconductor integrated circuit.
0 and the output voltage of the second loop filter 18 are substantially equal, so that when the rotation of the optical disk is in a steady state before and after the defect detection, the first loop filter 1
By giving the output voltage of the second loop filter 18 to 0, external noise becomes strong and the output frequency of the first voltage controlled oscillator 11 is stabilized. Therefore, when the read data signal is switched from the low reliability state to the high reliability state, the PLL circuit can be quickly pulled in to the read data signal.

[0023]

According to the present invention, since the operation of the frequency comparator is controlled in accordance with the reliability of the read data signal, the PLL circuit follows the low reliability read data signal. It always works without any trouble. Further, when the read data signal is switched from the low reliability state to the high reliability state, the output frequency of the voltage controlled oscillator can be quickly pulled in to the read data signal, which contributes to the improvement of the access time of the optical disk device.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of a PLL circuit of the present invention.

FIG. 2 is a diagram illustrating a PLL circuit according to a second embodiment of the present invention;

FIG. 3 is a diagram showing a conventional PLL circuit.

FIG. 4 is a diagram showing a configuration of an optical disk device.

FIG. 5 is a diagram illustrating an operation of an envelope detection unit.

FIG. 6 is a diagram showing timings of an EFM signal and a synchronous clock.

[Description of Signs] 1 RF signal input 2 Binarization circuit 3 Read data signal 4 Envelope detection circuit 5 Phase comparator 6, 8, 17 Charge pump 7 Frequency comparator 9 Addition circuit 10, 18, Loop filter 11, 19 Voltage control Oscillator 12 Defect detection output 13 Mirror detection output 14, 21 PLL circuit output 15 External reference signal 16 Phase frequency comparator 20 Switch circuit 22 Optical disk 23 Pickup 24 Preamplifier 25 Digital signal processing unit 26 Servo processor 27 D / A converter 28 ROM decoder Part 29 Digital data 30 Audio data

Claims (7)

[Claims] 1. A voltage-controlled oscillator for outputting an oscillation signal having a frequency corresponding to an input signal, and a position of an output signal of the voltage-controlled oscillator and a data signal obtained by binarizing an RF signal read from a recording medium. A phase comparator that detects a phase difference and outputs a comparison result according to the phase difference; a first charge pump that charges or discharges electric charge according to the comparison result of the phase comparator; A frequency comparator that compares an oscillation signal with the data signal and the frequency output by the voltage-controlled oscillator by counting a period by an output of the voltage-controlled oscillator, and outputs a comparison result according to the frequency difference; A second charge pump that charges or discharges electric charge according to a comparison result of the frequency comparator, and adds the first charge pump output and the second charge pump output And calculation circuit, and a first loop filter for outputting the input signal as an input the output of said adder circuit,
A PLL circuit comprising: a detection circuit that detects a period in which a transition point adjacent to the data signal obtained by binarizing the RF signal is different from an original period and outputs a detection signal; Wherein the comparison result outputted by the control circuit is controlled based on the detection signal. 2. The PLL circuit according to claim 1, wherein said detection circuit detects the mirror portion of said recording medium by receiving said RF signal as an input. 3. The PLL circuit according to claim 1, wherein the detection circuit detects the defect portion of the recording medium by using the RF signal as an input. 4. The detection circuit according to claim 1, wherein said detection circuit performs detection based on an envelope of said RF signal.
The PLL circuit as described in the above. 5. A PLL circuit for generating a clock signal synchronized with an RF signal read from a recording medium, the frequency comparator comparing a frequency of the RF signal with a frequency of the clock signal. Means for detecting an incomplete portion of the recording data of the recording medium based on the RF signal, and means for holding an output of the frequency comparator during detection of the incomplete portion, wherein during the holding operation, A PLL circuit which stops following an RF signal. 6. The PLL circuit according to claim 1, wherein
A second voltage-controlled oscillator for outputting an oscillation signal having a frequency corresponding to the input signal of the second voltage-controlled oscillator, detecting a frequency difference and a phase difference between an output signal of the second voltage-controlled oscillator and a reference clock, and detecting the frequency difference and the phase difference. A phase frequency comparator that outputs a comparison result according to the above, a third charge pump that charges or discharges electric charge based on the comparison result of the phase frequency comparator, and smoothes the output of the third charge pump. A second loop filter for outputting the second input signal and controlling the voltage controlled oscillator, and a switch circuit controlled by the defect signal, wherein the switch circuit is provided while the defect signal is being output. Wherein the output of the second loop filter is input to the adder circuit via the adder and added. 7. An optical disk device comprising the PLL circuit according to claim 1, 5 or 6.