JPH01119825A - Hash processing controller - Google Patents

Abstract

PURPOSE:To shorten hash processing time by providing a data table on the inside of an existing memory integrated into a system and generating an access address data based on a leading address data of the data table and an external data. CONSTITUTION:By outputting an address assigned to a leading address register 5 from a CPU 1, the leading address data alpha of a prescribed data table is supplied to the leading address register 5 from a decoder 8. Also, an external data X is inputted to the accumulator of the CPU 1 or an internal register from a buffer for holding the external data X with respect to an external data register 4, and simultaneously, the external data X is fetched to the external data register 4, as well. Subsequently, both the data are added by an adder 6, and an access address data (X+alpha) is generated. In such a way, when an address of a hash processing circuit is outputted from the CPU 1, a state that the output of the adder 6 is supplied to a main memory 2 can be selected, and a hash jump can be executed.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a hash processing control device, and more specifically, a hash processing control device that performs hash jump, 4-notch, etc. of a data table based on externally supplied data. The present invention relates to a hash processing control device suitable for.

<Conventional technology> Conventionally, in control systems that incorporate P1 to slice processors, general-purpose microprocessors, etc.,
There are cases where it is necessary to perform specific processing in response to command data supplied from an external source, and if there is a large amount of command data supplied from an external source, hash processing may be required to speed up command branch processing. It is becoming common to do this. In other words, the hash function is similar to successive approximation processing, and performs calculations based on a function (hereinafter referred to as hash function) that uses command data as a variable, and stores target information such as destination address data and coefficient data. Since this process calculates the address data that is being used and directly retrieves the target information based on the calculated address data, when command data is supplied from the outside, it is possible to calculate the address data that should be accessed in the memory in a short time. Obtainable.

To explain in more detail: (1) When performing a hash jump in a bit slice processor, the map memory method is generally used. FIG. 4 is a block diagram schematically showing the structure of a hash jump using the map memory method, in which a hash address output unit ( 41), the above hash address data f(
x) is supplied as read address data, the jump address data JAD stored in advance is read out from the map memory (42), and when the jump address data JAD is supplied, the micro program memory (44 ) A sequencer (43) that accesses the microprogram starting from the corresponding address in the microprogram sequence stored in advance and performs the predetermined processing based on the command data.
That's right.

Therefore, for example, when performing 256 types of branch processing using 8-bit command data, if the jump address is 1 word, hash address data f(x) will be equal to command data Command data X through core address output j part (41)
You can easily use a register to temporarily hold the
Moreover, a hash jump can be quickly performed.

■ When performing a hash jump in a microprocessor, two common methods are to set up a jump table in the main memory (see Figure 5) and to set up a dedicated map memory (see Figure 6). used for.

In the former method, command data X supplied from the outside is temporarily held in an external command register (51), and command data X read from the external command register (51) is sent to the processor via a data bus (52). (53), a predetermined calculation is performed to obtain the hash address data f(x) (specifically, for example, the command data ) and read the jump destination address data JAD from the hash address data f(x) in the jump table (54j) provided in the main memory (54), thereby making it possible to perform a hash jump.

In the latter method, hash address data f(x) is supplied to the map memory (62) by supplying command data X supplied from the outside to the hash address output section (61). This map memory (6
2) is supplied with a chip select signal generated by a decoder (65) based on output data from the processor (64). therefore,
Based on the chip select signal, the pre-stored jump destination address data JAD is read from the map memory (62) and sent to the block +J (6) via the data bus (63).
4), it is possible to perform a hash jump that accesses the main memory (66) based on the jump destination address data JAD.

<Problems to be Solved by the Invention> When the configuration shown in FIG. 5 is adopted, the command data Since it is necessary to perform calculations based on the transferred data internally, at least several steps are required to perform one hash jump, and the hash jump is actually performed after the command data is supplied. There is a problem in that it takes a long time to get there. especially,
If the process performed by hash jump is a process with a relatively small number of steps, such as vector drawing processing, the time required to perform the steps for performing hash jump cannot be ignored, so the successive approximation method is used. Although it is possible to reduce the time required to perform a branch process compared to the case where the method is adopted, it is not possible to achieve a sufficient reduction in the required time.

When the configuration shown in FIG. 4 or 6 is adopted, the jump destination address data JAD can be obtained without performing any calculations by the processor, so the actual processing after command data is supplied is possible. Although this can significantly reduce the time required to perform a hash jump, it requires a dedicated map memory, which increases the scale of the hardware and increases the overall cost. There is.

In other words, if the types of hash jumps increase, the capacity of the map memory will inevitably need to be increased.Furthermore, if the number of words of the jump destination address JAD increases, the capacity of the map memory will also inevitably increase. It is necessary to make it larger.

In addition, programmable read-only memory (hereinafter abbreviated as PROM) is usually used as map memory, but if PROM is used, the contents cannot be changed, so system upgrades cannot be easily handled. The problem is that it cannot be done.

Conversely, if you use static random access memory (hereinafter abbreviated as SRAM) as map memory,
Although the contents can be easily changed, a new problem arises in that an address arbiter is required to provide the map memory with an address for setting the table, which further complicates the configuration.

<Object of the invention> This invention was made in view of the above problems,
An object of the present invention is to provide a hash processing control device that can omit a dedicated memory and shorten the time required from when command data is supplied from the outside to when a predetermined memory access is performed. There is.

<Means for Solving the Problems> To achieve the above object, the hash processing control device of the present invention includes external data holding means for temporarily holding data supplied from the outside, and It includes a head address holding means for holding address data, and an address generating means for generating address data for accessing the memory based on the data held in both holding means.

However, the above address generating means may be an accelerator or a product-sum calculator, but is preferably an address bus that integrates data held in both holding means in parallel. In this case, the address bus used is
It is preferable that the data held in the head address holding means be the upper bits, and the data held in the external data holding means be the lower bits.

Further, it is preferable that a plurality of the memory blocks are provided and the start address holding means selectively holds the start address data of any one of the memory blocks.

Furthermore, the memory block may be one that holds jump destination address data for hash jump, or may be a data table.

Effect> With the hash processing control device having the above configuration, when accessing a corresponding address of a predetermined memory block based on data supplied from the outside, the start address data of the memory block can be held in the start address holding means. At the same time, the data supplied from the outside is temporarily held in the external data holding means, and the memory is accessed by temporarily feeding the data held in both holding means to the address generating means. It is possible to generate address data for

When the address generating means is an adder, address data for accessing the memory can be generated by adding the data held in both holding means.

Similarly, when the address generation means is a product-sum operation unit, address data for accessing the memory can be generated by performing a product-sum operation based on the data held in both holding means. Can be done.

Furthermore, if the address generating means is an address bus that integrates data held in both holding means in parallel, the memory can be accessed by simply outputting data from both holding means to the address bus. address data can be generated. In this case, if the address bus is such that the data held in the head address holding means is the upper bit and the data held in the external data holding means is the lower bit, the upper bits 1 to 1 are For a memory block defined by , address data for access can be generated based on data supplied from the outside.

Further, when a plurality of the memory blocks are stored and the start address holding means selectively holds the start address data of any of the memory blocks, the start address holding means holds the start address data. By changing the address data, the memory block to be accessed can be easily selected.

Furthermore, if the memory block holds jump destination address data for a hash jump, a hash jump can be performed, and if the memory block is a data table, data access can be performed. can be set.

<Example> Hereinafter, embodiments will be described in detail with reference to the accompanying drawings showing examples.

FIG. 1 is a block diagram showing an embodiment of a hash processing control device of the present invention.

In this embodiment, the central processing unit (hereinafter referred to as C
By supplying the address data output from the main memory (2) (abbreviated as PU) (1), the data at the corresponding address is taken into the CP IJ (1). , an external data register (4) that temporarily holds external data taken in through the buffer (3), and an external data register (4) that holds the start address data of the data table allocated to the main memory (2).
It has an adder (6) that adds the contents of the first address register (5) to generate access address data and supplies it to the main memory (2). To explain in more detail, the CPU (11) and the address bus (
A decoder (8) is installed which inputs the address data sent out through the buffer (3) and both registers ('1. ).Furthermore, the address data from the CPU (1) and the address data from the adder (6) are switched by a decode signal from the decoder (8). The data is selectively supplied to the main memory (2) through the selector (9) which is connected to C.P.
The same data is also transferred to the accumulator or internal register of U (1). Also, when changing the start address data of the data table, C
P U (New address data output from 11 is data bus 00) to the start address register (5)
is supplied to

To explain in more detail the relationship between the output address data from CP Ll (1) and the decoder (8), at least one address out of the address space of CPtJ (1) is assigned as the address of the first address register (5). , at least one address is assigned as an input address from the outside, and at least one address is assigned as an address of the external data register (4). Then, at least one address is allocated as the address of the buffer (3) and the external data register (4), and 1
External data is transferred from the buffer (3) to the CP in one access.
U (11 accumulators or internal registers and simultaneously supplied to the external data register (4). Also, at least one address is accessed from the main memory (2) based on the output address of the hash processing circuit. Furthermore, for the remaining addresses, the selector (9) is switched and controlled by the decode signal from the decoder (8), so that the main memory (2) is directly accessed.

Further, a data table (2a) in which a large number of jump destination address data JAD is stored is provided in a predetermined area of the main memory (a).

The operation of the hash processing control device having the above configuration is as follows.

First, from the CPU (1) to the start address register (5
), the decoder (8) supplies a decode signal to the start address register (5), selects the start address data write permission state, and in this state, ) through CPU U (11 to start address register (5
) of a predetermined data table.

After that, the buffer (3) is selected via the re-decoder (8) by outputting the address assigned as an external input address from CP (J (11), and the external data is held in the buffer (3). , then the CPU (
1), by outputting the address assigned to the buffer (3) and external data register (4),
A decode signal is supplied from the decoder (8) to the buffer (3) and the external data register C), and from the buffer (3) holding external data
At the same time as the external data X is loaded into the accumulator (1) or the internal register, the external data X is also loaded into the external data register (4).

In this state, external data X is temporarily held in the external data register (4), and starting address data α is held in the starting address register (5), so the adder (6) The data is added,
Access address data X+α is generated. Also, C
From P U (1), the decoder (
It is possible to select the state in which the access address data X+α output from the calculator (6) is supplied to the main memory (2) through the selector (9) which is switched and controlled based on the decode signal from the calculator (8). .

Therefore, the supplied access address data X+α
Based on the main memory (2), the content of the corresponding address, that is, the jump destination address data
By taking this jump destination address data JAD into the CPU (1), a hash jump can be performed.

After performing one hash jump as described above, when it becomes necessary to perform a hash jump, by performing the processing below the selection of the buffer (3) above, new data that depends on external data can be created. Have him do a hash jump.

If there is no need to perform a hash jump, the selector (9) is switched by the decode signal output from the decoder (8), and the address data output from the CPU (11) is directly stored in the main memory (2). Normal memory should be supplied.

can be accessed.

Furthermore, if coefficient data is stored in the data table (2a) instead of jump destination address data, processing can be performed based on coefficient data that depends on external data. Therefore, compared to a dedicated map memory that can only store jump destination address data, the degree of freedom of stored data can be significantly increased.Furthermore, the main memory (2) can store multiple f-data It is also possible to adopt a configuration in which a pull (2a) is provided and the CPU (1) supplies the start address data of any data table to the start address register (5).

As is clear from the above explanation, in this embodiment, there is no need for the CPU (1) to calculate the access address data, so the time required to read the necessary data from the data table can be shortened. Moreover, since the data table (2a) is provided in the main memory (2), there is no need to install a dedicated map memory, and the overall hardware configuration can be simplified. Furthermore, since the data table (2a) is provided in the main memory (2), version upgrades can be easily handled.

<Embodiment 2> FIG. 2 is a schematic block diagram showing another embodiment. The difference from the above embodiment is that a product-sum calculator (6a) is provided in place of the adder (6). In addition, a multiplier register (6b) is provided, which is supplied with multiplier data j by the CPU (1) and supplies this multiplier data j to the product-sum calculator (6a), and the main memory (2) is replaced by a read-only memory ( (hereinafter abbreviated as ROM) (2b), random access memory (hereinafter abbreviated as RAM) (2C), and a buffer that is selectively operated by a decode signal output from a decoder (8) (qal
The only difference is that the address data from CP tJ (1, 1) and the address data from the product-sum operation section (6a) are selectively sent to the address bus (7) via (9b).

In this embodiment, the buffer (9b) transfers the address data from the product-sum operation unit (6a) to the address bus (7).
) is selected, the access address data is sent based on the external data X held in the external data register (4) and the start address data α held in the start address register (5). jX ten α
Based on the access address data, T ROM (2
b), or CRAM (2C);/) 11B It is possible to read the destination address data JAD and perform a hash jump.

Therefore, if the data stored in the data table (2a) is not 1 word but j words, by simply supplying external data
It is possible to access data in word units.

<Embodiment 3> FIG. 3 is a block diagram showing still another embodiment. The difference from the embodiment of FIG. 1 is that the adder (6) is omitted and the main memory (2) is supplied with The upper bit part of the address bus (11) for address data is stored in the first address register (5), and the upper bit part is stored in the external data register (5).
4), the connected points, and both registers (41
F5) that can make the output high impedance is used, and a buffer F (12) is provided in place of the selector (9), so that the output is supplied from the decoder (8) to both registers (4) and (5). The output enable signal is inverted by the inverter (13) and sent to the buffer (12).
) is the only point that is supplied to the output control terminal.

In this embodiment, similarly to the embodiment of FIG.
External data X can be held in the external data register (/I), and start address data α can be held in the start address register (5). In this state, the decoder (8) supplies an output enable signal to both registers (/+15), and the inverter (
13) to the buffer (12), the contents of the start address register (5) will be set to upper pips 1~ and the contents of the external data register (4) will be set to lower pis 1~. Access address data β is supplied to the main memory (2) through the address bus (11), and destination address data JA corresponding to external data
A hash jump can be performed by reading D from the main memory (2).

Therefore, the configuration can be simplified by omitting the adder (6), and the external data register (
4) and the bit width of the start address register (5) can also be reduced.

In addition, regarding the above inverter (13), PLD (pr
It can be integrated with the decoder (8) by converting it into an ogrammable Logic Device.

In addition, the main memory (2) is composed of a ROM (2b) and a RAM (2c), and a data table (2).
a) can be provided in either the ROM (2b) or the RAM (2c), or both, and if such a configuration is adopted, the upper processor (not shown) It is possible to deal with version upgrades, etc. by simply downloading the software from , and there is no need to perform special memory content change processing to deal with version upgrades.

It should be noted that the present invention is not limited to the above embodiments; for example, it is possible to use a FIFO memory as the buffer (3), and also to By supplying separate control signals, it is possible to import external data into the CPU (1) and external data into the external data register (4) at different timings. Various design changes can be made without changing the gist of the invention.

<Effects of the Invention> As described above, the present invention provides a data table in an existing memory built into a system, and generates access address data based on the start address data of the data table and external data. Since I am trying to do this, I omit the step for performing on the cPU and use the cP
It is possible to reduce the burden on U, shorten the time required for hash processing, and eliminate the need for extra dedicated memory, achieving a smaller and simpler hardware configuration. It has the unique effect of being able to

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the hash processing control device of the present invention, FIGS. 2 and 3 are block diagrams showing other embodiments, and FIGS. FIG. 2 is a block diagram showing a conventional example. (2) Main memory, (2a) Data table, (2b) ROM, C2c) -RAM,
(4)...external data register, (5...start address register, (6)...adder, (6a)...product-sum calculator, (11)...address bus, patent application People Daikin Industries, Ltd.

Claims (1)

[Claims] 1. A device that accesses a corresponding address of a predetermined memory block (2a) based on data x supplied from the outside, the external device temporarily retaining the data x supplied from the outside. Data holding means (4) and memory block (2a
) and the memory (2) (2b) (2c) based on the data x and α held in both the holding means (4) and (5).
1. A hash processing control device comprising address generation means (6), (6a), and (11) for generating address data for accessing. 2. The hash processing control device according to claim 1, wherein the address generating means is an adder (6). 3. The hash processing device according to claim 1, wherein the address generating means is a product-sum calculator (6a). 4. The above claim 1, wherein the address generation means is an address bus (11) that integrates data held in both the holding means (4) and (5) in parallel.
The hash processing control device described in Section 1. 5. The address bus (11) is connected to the start address holding means (
5. The hash processing control device according to claim 4, wherein the data held in the external data holding means (4) is used as the upper bits, and the data held in the external data holding means (4) is used as the lower bits. 6. A plurality of memory blocks (2a) are provided, and the start address holding means (5) selectively holds the start address data α of any one of the memory blocks (2a). The hash processing control device according to scope 1. 7. The hash processing control device according to claim 1, wherein the memory block (2a) holds jump destination address data for hash jump. 8. The hash processing control device according to claim 1, wherein the memory block (2a) is a data table.