JPH01108896A - Sequential scanning converting television receiver - Google Patents

Abstract

PURPOSE:To obtain high picture quality without jitters to also a non-standard video signal by processing the writing of a time axis correcting memory and digital processing before that by a clock phase-locking a horizontal synchronizing signal. CONSTITUTION:A time axis correcting part 4 lies between a Y/C demodulating part 3 and a scanning lines number converting part 5, the writing/reading clocks of a time axis correcting memory 4A are made independent, the former is made into a clock phase-locking the horizontal synchronizing signal, the latter is made into a clock phase-locking a color sub-carrier and the clocks of the pre-stage and the post-stage of the time axis correcting part 4 are respectively fitted to these clocks. Consequently, in the processing to the writing of the time axis correcting memory 4A, the jitters in the non-standard NTSC signal itself and the jitters due to the digital processing are dissolved and processing after the reading of the time axis correcting memory can be processed by the clock phase-locking the color sub-carrier without the jitters. Thus, an R, a G and a B signals of high picture quality can be obtained.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a high-definition television receiver that converts an incremental scan video signal to a progressive scan video signal on the receiver side, and particularly relates to a high-definition television receiver that converts an incremental scan video signal to a progressive scan video signal, and is particularly applicable to non-broadcast television receivers such as VTRs. The present invention relates to a television receiver that can maintain high image quality even for system video signals.

[Conventional technology]

Current ink-lace scanning has ink-lace disturbances such as interline flicker and line crawling.
This causes image quality deterioration. Therefore, a progressive scan conversion television receiver is now in practical use, in which the image quality is improved by converting increment scan to progressive scan on the receiver side.

[Problem that the invention seeks to solve]

The above image quality improvement is achieved by converting the NTSC signal into a digital signal and using a large capacity memory to perform Y/C separation and scanning line interpolation. The system clock for digital processing is a 4f3. Clock (fs
c: frequency of color subcarrier) and 8f8. It's a clock. In broadcasting NTSC signals, the color subcarrier is synchronized with the horizontal synchronization signal, and the horizontal synchronization signal has no jitter.
In non-broadcasting NTSC signals such as VTRs (hereinafter referred to as non-standard NTSC signals), the color subcarrier is not synchronized with the horizontal synchronization signal, and the horizontal synchronization signal and Y signal contain jitter. Therefore, conventional progressive scan conversion television receivers have the following problems.

In a non-standard NTSC signal, the color burst and horizontal synchronization signal are not synchronized, so if the signal is A/D converted and processed using a clock synchronized with the color subcarrier of the color burst, the number of samples per line will be strictly 910. Instead, the sample position between lines varies from line to line, causing jitter. As a countermeasure to this problem, the present applicant has proposed in Japanese Patent Application No. 61-199393 a technique of performing A/D conversion using a clock phase-locked to the horizontal synchronizing signal and performing subsequent processing. However, since the input video signal itself has jitter, the high image quality achieved by progressive scan conversion can only be enjoyed by absorbing jitter somewhere in the video signal processing.

SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a progressive scan conversion television receiver that can provide high image quality without jitter even with non-standard video signals.

[Means for solving problems]

The device of the present invention is used as a television receiver to convert an input video signal into a digital signal, and then converts the input video signal into a digital signal.
Y signal demodulated via C demodulator.

A time-multiplexed color difference (R-Y, B-Y) signal is input to a time axis correction section that includes a time axis correction memory with independent write and read clocks, and the time axis corrected signal is converted to the number of scanning lines. Further, the sequentially scanned Y signal is directly converted into a sequential scanning signal, and the time-multiplexed color difference signal is divided through a color division circuit to form an RY signal and a B-Y signal (from No. 8,
It has a video processing section that inputs the data into the matrix circuit, converts it into R, G, and B signals, performs D/A conversion, and outputs the data as analog R, G, and B signals. Here, the above A/
The clock of the D conversion/YC demodulation section and the write clock of the time axis correction memory are clocks that are phase-locked to the horizontal synchronization signal that is synchronously separated from the input video signal, and the clock that is read out from the time axis correction memory and after that. The circuit clock is phase-locked to the color subcarrier.

[Effect]

In the present invention, two systems are used as clocks for digital processing: a clock phase-locked to the horizontal synchronizing signal and a clock phase-locked to the color subcarrier of the color burst. A time axis correction section is interposed between the YC demodulation section and the scanning line number conversion section, and makes the write and read clocks of the time axis correction memory independent, and the former is a clock phase-locked to the horizontal synchronization signal, and the latter is a color subcarrier. The clock is phase-locked to the above clock, and the clocks at the front and rear stages of the time axis correction section are each synchronized with the above clock. As explained in the example, non-standard N
The jitter in the TSC signal itself and the jitter caused by its digital processing are eliminated, and the processing after reading out the time axis correction memory can be performed using a clock phase-locked to a jitter-free color subcarrier.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit block diagram, in which the upper part shows a part that performs a series of signal processing, and the lower part shows a clock generation part.

First, the clock generation part will be explained.

Two series of clocks are generated: a clock whose phase is locked to the horizontal synchronization signal, and a clock whose phase is locked to the color burst. The input video signal 1 of this device is input to a sync separation circuit 10, where a horizontal sync signal is separated and input to a PLL circuit 11. The PLL circuit 11 generates a pulse whose phase is locked to the horizontal synchronization signal, and the clock generation circuit 14 generates a clock pulse of a predetermined frequency.

The 910 fH clock for this series is 4fs. However, in order to indicate that it is synchronized with the horizontal synchronizing signal, the display corresponds to the number of dots in one scanning line. The input video signal 1 is also input to an APC circuit 12, which generates a color subcarrier synchronized with the color burst, pulsed by a PLL circuit 13, and pulsed by a clock generation circuit 14, which generates 4fsc and 8f synchronized with the color subcarrier.
Generates the sc clock. Further, the color subcarrier generated by the APC circuit 12 is converted into a digital signal by the A/D converter 15, and used for demodulation by a color demodulation circuit 33, which will be described later.

Next, the portion in the upper part of FIG. 1 that performs signal processing will be explained. The clock in signal processing is 91 OfH' = 4 fsc, 8rs for each range shown at the top of the figure.
c. Input video signal 1 is converted into a digital signal by A/D converter 2 and input to Y/C demodulator 3 .

The Y/C demodulator 3 includes a Y/C separation circuit 31. YC processing circuit 3
It includes a 21-color demodulation circuit 33 and outputs a Y signal and a time-multiplexed color difference (R-Y, B-Y) signal. The Y/C separation circuit 31 uses line memory/field memory,
Although not shown, motion detection enables motion adaptive Y/C.
Perform separation.

The yc processing circuit 32 performs processing such as edge enhancement, contrast adjustment, and gain adjustment. The C signal, which is the output of the YC processing circuit 32, is subjected to time multiplexed color difference (R-Y, B
−Y) signal. Y signal and time-multiplexed color difference (
The R-Y, B-Y) signals are input to the time axis correction section 4 at the next stage. The color demodulation circuit 33 has an A/D clock 910 f.
The digital color subcarrier 15a output from the converter 15 is multiplied by the C signal at two phases (0° and 90°) to demodulate the color difference signal.

The time axis correction unit 4 includes a time axis correction memory 4A and a memory controller 4B, and writing and reading of the time axis correction memory 4A are performed independently and asynchronously. That is, write with 9 10 fH clocks input to the memory controller 4B, 4f. Read by clock. Y with jitter
Signal/color difference (R-Y.

B-Y) signals are aligned in phase by this writing, and 4rsc
By reading with a clock, jitter components contained in each of the Y, RY, and BY signals are absorbed.

The output of the time axis correction section 4 is input to the scanning line number conversion section 5,
It is converted into a progressive scanning signal. In the following, the time-multiplexed color difference signal will be expressed as C0. The scanning line number conversion section 5 includes a Y interpolation circuit 51. A Co interpolation circuit 52 forms a line interpolation value, and a time compression circuit 53 switches and outputs it at a double speed 8fsc clock.

The Y signal and Co signal converted to sequential scanning are converted into the Y signal directly, the C0 signal through the color division circuit 6, the R-Y signal, and the B-Y signal.
The signal is input to the matrix circuit 7, and then converted into R, G, and B signals, and then sent to the D/A converter 8 (IL 8 (2)
, 8 (3), each of which is output as an analog signal.

〔Effect of the invention〕

As explained above, the present invention provides a progressive scan conversion television receiver that prevents image quality deterioration caused by increment scanning and obtains high image quality. This has been improved so that high image quality can be obtained even when

In a non-standard NTSC signal, the horizontal synchronization signal and color subcarrier are not synchronized, and the Y signal itself contains jitter, but in the present invention, writing to the time axis correction memory and previous digital processing is processed using a clock that is phase-locked to the horizontal synchronization signal, so it is the Y signal in the input video signal.

Even if there is jitter in the horizontal synchronization signal, YC after A/D conversion
In the demodulator, Y/C separation, yc processing, and color demodulation are performed using the same clock as described above, so that no errors occur due to the processing. Furthermore, even if there is jitter in the Y signal, the write address in the time axis correction memory is correct, so the jitter is absorbed by reading it out with a clock phase-locked to the jitter-free color subcarrier. Since subsequent digital processing such as conversion of the number of scanning lines is also processed using the above-mentioned system of clocks, high-quality R, G, and B signals can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram of an embodiment of the present invention. 2.15-A/D converter, 3-Y/C demodulator, 31-Y/C separation circuit, 32-YC processing circuit, 3
3--color demodulation circuit, 4-time axis correction circuit, 4A-time axis correction memory, 4B--memory controller, 5--scanning line number converter, 6--color division circuit, 7-
Matrix circuit, 8(1) to 8(3)-D/A converter, 10-synchronous separation circuit, 11, 13-PLL circuit, 12-A
PC circuit, 14-.- clock generation circuit.

Claims (1)

[Claims] After converting an input video signal into a digital signal, a Y signal and a time-multiplexed color difference (R-Y, B-Y) signal demodulated through a YC demodulator are written.・The read clocks are input to the time axis correction unit including mutually independent time axis correction memories, and the time axis corrected signals are converted into sequential scanning signals in the scanning line number conversion unit, and the sequentially scanned Y signals are Directly, the time-multiplexed color difference signal is divided through a color division circuit to become an R-Y signal and a B-Y signal, and then input to a matrix circuit to become R, G, and B signals, each of which is D/A converted and converted into an analog signal. A television receiver having a video processing unit that outputs R, G, and B signals, wherein the clock of the A/D conversion/YC demodulation unit and the write clock of the time axis correction memory are synchronously separated from the input video signal. A progressive scan conversion television receiver characterized in that the clock is phase-locked to a horizontal synchronization signal, and the readout clock of the time axis correction memory and the clock of subsequent circuits are clocks phase-locked to a color subcarrier. .