JPH01101747A - Dsi interface circuit for digital cross connection - Google Patents

Abstract

PURPOSE:To miniaturize a device and to save a concentrating space by re- coupling respective inputted DS1 signals as a stuff frame with using same one clock and serially arranging DS1 data from #1 to #28 for the unit of stuff frame length. CONSTITUTION:In the receiving side of the DS1 signal, a circuit 10, which stuff-synchronizes the 28 number of the DS1 signals, a circuit 20 to store these stuff-synchronized signals and a circuit 30, which multiplexes the signals read out of the storing circuit 20 and sends them as a DS3' signal are equipped. Then, in the transmitting side of the DS1 signal, a circuit 30' which multi- separates the received DS3' signal, a circuit 20' which stores the multi-separated signal, and a circuit 10' which destuff-synchronizes the signal read out of the storing circuit 20' and sends the 28 number of the DS1 signals are equipped. Thus, since the plural number of the DS3' signals which are inputted into a time-dividing switch, include the DS1 signals arranged in order, a cross connect can be easily executed for the unit of the DS1. Then, the device scale can be reduced and a concentrating scale can be widely miniaturized.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a cross-connect system for digital transmission, particularly to synchronization between digital signals required when interconnecting time-division multiplexed digital signal transmission paths. Regarding the method.

[Conventional technology]

With the expansion of the application area of digital communication in recent years, initial route settings for digital transmission lines, expansion of lines during operation,
The cross-connect method for changing routes in response to service changes or failure occurrences has the potential to reduce the scale of equipment, reduce line concentration space, save labor in connection work, and diversify the hierarchy levels that can be switched. Multifaceted technological demands are increasing.

Conventionally, this type of cross-connect system for digital transmission uses a distribution rack equipped with a group of switches that change the interconnection of multiple signal lines (for example, coaxial cables), and connections are made by manually operating the switches. There are two types of digital signals on transmission lines: synchronous signals that are synchronously multiplexed, and asynchronous signals that are stuffed multiplexed.

Among these, for asynchronous digital signals.

Since there is no technology to apply time switches that switch connections by changing time slots, space switches that interconnect signal lines are used as the switch group for the two-distribution rack.

[Problem that the invention seeks to solve]

The above-mentioned conventional cross-connect system for digital transmission uses a space switch as a switching means for interconnecting transmission lines, so the device can be miniaturized.

The problem is that it is very difficult to sufficiently meet various demands such as reduction of line concentration space and switching units. In other words, a one-hour switch can be easily miniaturized through circuit integration.

Miniaturizing the space switch involves the problem of introducing low-order group signal lines into the distribution rack, and the space switch itself occupies a large physical area, so miniaturizing the device and saving space for concentrating lines requires physical effort. This is not possible due to constraints.

[Means for solving the problem] The DSI interface circuit according to the present invention includes, on the receiving side of the DSI signal, a circuit for stuff-synchronizing 28 DSI signals, and a circuit for storing these stuff-synchronized signals. a circuit, and a circuit that multiplexes the signals read out from the storage circuit and sends it out as a DS 3' signal,
On the transmitting side of the DSI signal.

A circuit that demultiplexes the received DS 3' signal, a circuit that stores the demultiplexed signal, and a circuit that synchronizes the signals read from the storage circuit and sends out 28 DS1 signals. It is characterized by having the following.

[Effect]

In the present invention, the DS of the North American digital hierarchy
When switching multiple I signals using a time-division switch, the receiving side switches these DSI signals into two
After composing one stuff frame by inserting stuff into each DSI signal and synchronizing the mutual DSI signals, the new 28 SI signals are combined with the own high-order group clock generated inside the device. The transmitting side performs demultiplexing, which is the opposite operation to the above, as well as destuff synchronization and one time division switch. Perform pre-preparation and post-processing.

〔Example〕

FIG. 1 is a diagram showing an embodiment of the present invention. On the receiving side, ■ is the North American primary group D to be serially multiplexed.
For SI signals, 28 signals are handled as one unit. 10 is a DSI stuff synchronization circuit, which is a clock supplied from the M13' multiplexing circuit 30 and has a higher pit rate than the pit rate of the DSI signal 1; are synchronized using the staff synchronization method. DSI stuff synchronization circuit lO
The new SL signal 2 output from the memory circuit 20
After the DSI signals from Φ1 to ≠28 are stored in the n
The signals are sequentially read out through the pit pass line 3. The frame configuration at this time is DS3, in which 28 DS1 signals are arranged in series based on one frame length unit.
'An example of the signal is shown in FIG.

In Fig. 2, for example, subframe 1 has a signal DS.
The data of 1-1 is the signal DS 1-1 in subframe 2.
2 data is inserted, and so on.

Data of 28 DSI signals are stuffed and synchronously multiplexed into one frame in 28 subframes. In other words, in FIG.
3/The multiplexing circuit 30 performs stuff synchronization in each DS1 unit, and 28 pieces of data are arranged in series in units of one staff frame length for each ID5I signal and sent to the line 4 as a DS3' signal.

Further, the DS3' clock 5, which is a synchronization clock, is supplied from a common clock source (not shown) in order to synchronize with other interface circuits.

Note that the transmitting side, that is, the sending circuit for the DSI signal 1, is composed of a circuit opposite to the above, that is, an M13' demultiplexing circuit 30', a memory circuit 20', and a destuffing synchronization circuit 10'.
? , 28 by receiving the DS3' signal and performing the operation opposite to the above.
Sends out the actual DSI signal.

〔Effect of the invention〕

As explained above, the present invention reassembles each of the input DS 1 signals as a stuff frame using the same clock, and converts the DSI data from 1 to ≠ 28 into 1
The stacks are arranged in series in units of frame length and converted into DS 3' signals. That is, since the plurality of DS3' signals inputted into the nine time division switches include DSI signals arranged in an orderly manner, cross-connection in DSI units is easily possible. This is from DS3' signal to DS
The same applies to the conversion of the I signal, and therefore the device scale is small and the line concentration scale can be significantly reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a diagram showing the frame structure of a DS3' signal when 28 DS1 signals are stuff-synchronously multiplexed according to the present invention.

Claims (1)

[Claims] 1. On the receiving side of the DS1 signal, there is a circuit that stuff-synchronizes the 28 DS1 signals, a circuit that stores these stuff-synchronized signals, and a circuit that multiplexes the signals read from the storage circuit and outputs the DS3 signal. 'The circuit that sends out the DS1 signal as a signal, and the DS1 signal transmitting side
A circuit for demultiplexing the S3' signal, a circuit for storing the demultiplexed signal, and a circuit for destuffing and synchronizing the signals read from the storage circuit and sending out 28 DS1 signals. A DS1 interface circuit for digital cross connect characterized by the following.