JP7352507B2 - gaming machine - Google Patents

Description

The present invention relates to gaming machines such as pachinko machines, arranged ball machines, mahjong ball gaming machines, slots, and enclosed pachinko machines (managed gaming machines) that circulate enclosed game balls internally. The present invention relates to a gaming machine that can reduce the amount of money.

As a conventional gaming machine such as a pachinko machine, a gaming machine as described in Patent Document 1 is known, for example. This gaming machine sets 0 in the lower byte of a time saving number command for transmitting data of the number of time saving times managed by the main control to the sub control if the number of time saving times is 127 or more.

Japanese Patent Application Publication No. 2015-100700

However, the above gaming machine has a problem in that the control burden cannot be reduced .

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a gaming machine that can reduce the control burden.

The above object of the present invention is achieved by the following means. Note that reference numerals of embodiments to be described later are given in parentheses, but the present invention is not limited thereto.

According to the gaming machine according to the invention of claim 1, a count updating means for updating a predetermined count value as the game progresses;
a count display means (for example, a liquid crystal display device 41 shown in FIG. 5) that displays the predetermined count value updated by the count update means in a plurality of numbers;
The count display means (for example, the liquid crystal display device 41 shown in FIG. 5)
Displaying a fluctuation animation indicating that the predetermined count value is updated (see, for example, FIG. 30);
The fluctuation animation is
In displaying the updated predetermined count value on the count display means (e.g., the liquid crystal display device 41 shown in FIG. 5), the first digit out of a plurality of numbers is displayed regardless of the pre-update value of the predetermined count value. The count display means (for example, the liquid crystal display device 41 shown in FIG. 5) displays a high-speed fluctuation animation (for example, the high-speed fluctuation animation KAI shown in FIGS. ), and for the second digit adjacent to the first digit, a low-speed fluctuation animation that allows the change to be visually recognized (for example, see Figure 30 (c-2) to (f-2)) is displayed on the count display means (for example, the liquid crystal display device 41 shown in FIG. 5),
The high-speed fluctuation animation is displayed a predetermined number of times or for a predetermined time until the second digit changes to a number indicating the updated predetermined count value (see paragraph [0217] of the specification). It is said that
Further, according to the gaming machine according to the invention of claim 2, in the gaming machine according to claim 1 , the low-speed fluctuation animation is a fluctuation animation to the extent that it can be visually recognized that the numbers are changing by 1. ,
The high-speed fluctuation animation can be repeatedly displayed for a predetermined number of times or for a predetermined time until the second digit changes from the predetermined count value before updating to the predetermined count value after update. (See specification paragraph [0217]) .

According to the present invention, control burden can be reduced.

1 is a perspective view showing the appearance of a gaming machine according to an embodiment of the present invention. It is a perspective view of the front side showing the state where the door of the game machine is opened before the game board according to the same embodiment is installed. It is a front view showing a state where the door of the game machine is opened before the game board according to the same embodiment is installed. It is a perspective view of the rear side showing the appearance of the gaming machine according to the same embodiment. It is a front view of the game board according to the same embodiment. It is a block diagram showing a control device of a gaming machine according to the same embodiment. Figures of a production scenario table according to the same embodiment are shown, (a) shows a diagram in which a plurality of production scenario data are stored, and (b) is stored within one layer data of the production scenario data shown in (a). FIG. 7(c) is a diagram showing the control table referenced by the control code data shown in FIG. FIG. 2 is a block diagram showing a VDP according to the same embodiment. (a) is an explanatory diagram that explains the flow of the conventional game, (b) is an explanatory diagram that explains the flow of the rescue game, and (c) is an explanatory diagram that explains the flow of the game with special electric support symbols. It is. (a) shows a table in which a variable pattern table to be referred to depending on the gaming state is stored, and (b) is a diagram showing a variable pattern table selected in the normal gaming state. (a) shows a variation pattern table selected in the first time saving game state (1st to 79th rotations), and (b) shows a variation pattern table selected in the first time saving gaming state (80th to 99th rotations) It is a figure showing a table. (a) shows a variation pattern table selected in the first time saving game state (100th rotation), (b) shows a variation pattern table selected in the second time saving gaming state (1st rotation), (c) is a diagram showing a variation pattern table selected in the second time saving game state (2nd to 100th rotation). It is a diagram showing a variation pattern table selected in the second time saving game state (101st to final rotation). It is an explanatory diagram explaining processing contents when a small hit and a special electric support symbol are used together. 7 is a block diagram of a one-chip microcomputer mounted on the main control board shown in FIG. 6. FIG. (a) is an explanatory diagram of a reception prescaler register built into the asynchronous serial communication circuit shown in FIG. 15, and (b) is an explanatory diagram of a reception buffer register built into the asynchronous serial communication circuit shown in FIG. 15. be. (a) is an explanatory diagram of a transmission prescaler register built into the asynchronous serial communication circuit shown in FIG. 15, and (b) is an explanatory diagram of a transmission buffer register built into the asynchronous serial communication circuit shown in FIG. 15. be. (a) to (c) are timing charts showing the serial communication format of one frame. (a) is an explanatory diagram of the communication setting register built in the synchronous serial communication circuit shown in FIG. 15, and (b) is an explanatory diagram of the transmission data register built in the synchronous serial communication circuit shown in FIG. 15. , (c) is an explanatory diagram of the reception data register built in the synchronous serial communication circuit shown in FIG. 15, and (d) is an explanation diagram of the transmission/reception status register built in the synchronous serial communication circuit shown in FIG. 15. It is a diagram. 7 is a block diagram of a payout control one-chip microcomputer mounted on the payout/launch control board shown in FIG. 6. FIG. (a) is an explanatory diagram of the serial communication baud rate setting register built in the asynchronous serial communication circuit shown in FIG. 20, and (b) is an explanatory diagram of the serial communication setting register built in the asynchronous serial communication circuit shown in FIG. It is an explanatory diagram. (a) is an explanatory diagram of the asynchronous serial communication status register built in the asynchronous serial communication circuit shown in FIG. 20, and (b) is an explanatory diagram of the serial communication data register built in the asynchronous serial communication circuit shown in FIG. It is an explanatory diagram. FIG. 3 is a timing chart showing the timing from when the external power source is cut off until the internal voltage drops. (a) is an explanatory diagram for explaining the state in which the movable accessory device is moved to the front of the liquid crystal display device during a customer waiting demonstration, and (b) is an explanatory diagram for explaining the state in which the movable accessory device shown in (a) is moved to the front of the liquid crystal display device. FIG. 6 is an explanatory diagram illustrating a state in which the customer returns to the origin position (original position), the customer waiting demonstration is canceled, and a normal screen is displayed on which a special symbol is displayed in a variable manner. (a) to (d) are explanatory diagrams illustrating the flow of a conventional change performance in which the previous number of balls is changed to a new number of balls in a count-up performance. (a) to (d) are explanatory diagrams illustrating predetermined scenes for displaying numerical information on the previous number of pitches and numerical information on the new number of pitches on the liquid crystal display device. (a) to (d) are explanatory diagrams illustrating the flow of a change performance according to the same embodiment in which the previous number of balls is changed to a new number of balls in the count-up performance. (a-1) to (a-4) are explanatory diagrams illustrating scenes that are predetermined for displaying an image that changes from a common fluctuation animation to a new number of pitches on a liquid crystal display; (b) -1) to (b-4) are explanatory diagrams explaining the flow of images changing from a common fluctuation animation to a new number of pitches, (c-1) to (c-4) are (a- 1) - (a-4) is an explanatory diagram illustrating a predetermined scene for displaying on a liquid crystal display an image that changes from a common variation animation to a new number of pitches, using a method different from those shown in (a-4). . (a) to (f) are explanatory diagrams illustrating the flow of images that change from a common fluctuation animation to a new number of pitches when a new count-up effect occurs during the count-up effect. In (a) to (g), when performing a change effect that changes from the previous number of pitches to a new number of pitches in the count-up production, a high-speed fluctuation animation is displayed on the liquid crystal display device by one place, and ten The digit is an explanatory diagram illustrating displaying a low-speed fluctuation animation in which the number is increased one by one. In (a) to (b), when the count of a timer etc. is subtracted, the second decimal place displays a high-speed fluctuating animation on the liquid crystal display, and the first decimal place displays a low-speed fluctuating animation. It is an explanatory view explaining display on a liquid crystal display device. (a) shows a table in which a distribution table to be referred to according to the number of changes in the special pattern after the background change is stored, (b) shows the first distribution table, and (c) shows the second distribution table. It is a figure which shows a distribution table, (d) shows a 3rd distribution table, and (e) shows a 4th distribution table. (a) shows the sub-control variation pattern distribution table, (b) shows the left symbol lottery distribution table, (c) shows the symbol change notice table, and (d) shows the changing symbol lottery distribution table. FIG. (a-1) to (a-5) show screen examples of conventional background change effects showing the flow of change from the current background to the background after the change, and (b-1) to (b-5) ) shows an example screen of the background change effect according to the same embodiment showing the flow of change from the current background to the background after the change, and (c-1) to (c-5) show the screen example of the background change effect from the current background to the changed background. , is a diagram showing a screen example of a background change effect according to another embodiment different from (b-1) to (b-5) showing the flow of changing the background after the change. It is a flowchart figure explaining main processing of main control concerning the same embodiment. 36 is a flowchart illustrating a continuation of the main processing of the main control shown in FIG. 35. FIG. 36 is a flowchart diagram illustrating the setting switching process shown in FIG. 35. FIG. FIG. 3 is a flowchart diagram illustrating power supply abnormality check processing. FIG. 3 is a flowchart illustrating main control timer interrupt processing according to the embodiment. 40 is a flowchart diagram explaining the normal symbol processing shown in FIG. 39. FIG. It is a flowchart figure explaining the special symbol processing shown in FIG. FIG. 42 is a flowchart diagram illustrating starting port check processing 1 (2) shown in FIG. 41; 42 is a flowchart diagram illustrating the special symbol variation start process shown in FIG. 41. FIG. FIG. 44 is a flowchart illustrating transmission of the relief count command shown in FIG. 43; FIG. 44 is a flowchart illustrating transmission of the time saving number command shown in FIG. 43; 44 is a flowchart diagram illustrating the hit determination process shown in FIG. 43. FIG. It is a flowchart figure explaining the special electric support symbol hit determination process shown in FIG. It is a diagram showing a program example of a special electric support symbol hit determination table. It is a flowchart figure explaining the process during special symbol fluctuation shown in FIG. It is a flowchart figure explaining the process during special symbol confirmation time shown in FIG. (a) shows a normal symbol hit determination table used when executing a winning lottery for normal symbols, (b) shows a special symbol jackpot determining table used when executing a winning lottery for special symbols, (c) shows the special symbol small hit determination table used when executing the special symbol winning/failure lottery, and (d) shows the special electric support symbol winning determination table used when executing the special symbol winning/failing lottery. FIG. It is a flowchart figure explaining the process during special symbol fluctuation concerning other embodiments. FIG. 7 is a flowchart diagram illustrating transmission of a relief count command according to another embodiment. It is a flowchart figure explaining the time saving frequency|count command transmission based on other embodiment. FIG. 55 is a flowchart illustrating the data division processing shown in FIGS. 53 and 54. FIG. It is a flowchart figure which shows the main processing of the sub-control based on the same embodiment. 57 is a flowchart diagram showing the data analysis process shown in FIG. 56. FIG. FIG. 7 is a flowchart showing sub-control command reception processing according to the embodiment. It is a flowchart figure which shows the timer interruption process of sub-control based on the same embodiment. (a) shows a flowchart for explaining an initial command list related to moving images, (b) shows a flowchart for explaining a regular command list for moving images, and (c) shows a flowchart for explaining a command list for still images. .

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a gaming machine according to the present invention will be specifically described below with reference to the drawings, taking a pachinko gaming machine as an example. In the following description, when referring to directions such as up, down, left, and right, the directions are meant to be up, down, left, and right when viewed from the front in the drawing.

<Explanation of external configuration of pachinko machine>
First, the external configuration of the pachinko gaming machine according to the present embodiment will be described with reference to FIGS. 1 to 6.

<Explanation of the external configuration of the front of the pachinko machine>
As shown in FIG. 1, the pachinko game machine 1 has a wooden outer frame 2, and a hinge 4a (see FIG. 2) provided on the front side of the outer frame 2 on the left side. It is provided with a rectangular front frame 3 which is pivotally mounted to be freely openable and closable and detachable.

The front frame 3 includes an upper mounting part 5 and a lower mounting part 6 provided below the upper mounting part 5, as shown in FIGS. 2 and 3. An upper opening/closing door 7 is provided on the front side of the upper mounting part 5 and supports a transparent glass which is pivotally connected to the vertical axis via the hinge 4a so as to be openable and detachable. A lower opening/closing door 8 is pivotally attached to the lower opening/closing door 8 by a hinge 4b provided on the same side as the hinge 4a so as to be freely openable/closable and detachable.

As shown in FIG. 1, this lower opening/closing door 8 includes an upper tray 9 for storing discharged game balls, and a lower tray for receiving and storing surplus balls when the upper tray 9 is full. A saucer 10 is integrally formed. Further, the lower opening/closing door 8 is provided with a ball rental button 11 and a prepaid card ejection button 12 (card return button 12), and a built-in lamp (not shown) is lit on the upper tray surface portion of the upper tray 9. A push-button type performance button device 13 is provided which can change the performance effect by pressing the button at the same time. Further, the upper tray 9 is provided with a ball removal button 14 for pulling out the game balls stored in the upper tray 9 downward, and is further provided with a setting button 15 which is approximately a cross key. The setting buttons 15 can be operated by the player, and include a circular enter key 15a provided in the center, a triangular upper key 15b provided above the enter key 15a in the figure, and a A triangular left key 15c provided on the left side of the key 15a in the drawing, a triangular right key 15d provided on the right side of the enter key 15a in the drawing, and a triangular right key 15d provided on the lower side of the enter key 15a in the drawing. It is composed of a lower key 15e and a lower key 15e.

On the other hand, on the right end side of the lower opening/closing door 8, as shown in FIG. 1, a firing handle 16 for operating the firing unit is provided, and as shown in FIGS. A speaker 17 that emits BGM (background music) or sound effects is provided on the surface side and near the firing handle 16. Decorative lamps such as LED lamps are arranged at various locations on the upper door 7 and the lower door 8 to create a decorative effect of light.

On the other hand, the upper mounting portion 5 is provided with a game board mounting frame 18, as shown in FIGS. It is mounted with the game area 40 shown facing forward, and is fixed within the game board mounting frame 18. That is, as shown in FIG. 3, the upper mounting portion 5 is provided with a plurality of connection connectors 19 (four in the figure) at the lower right side. The game board YB is mounted within the game board mounting frame 18 by being connected to a connector (not shown) provided on the back surface of the game board YB. Then, the game board YB is fixed within the game board mounting frame 18 by the fixtures 20a and 20b provided vertically on the right side surface. As a result, the game board YB is mounted within the game board mounting frame 18, and the upper opening/closing door 7 supporting transparent glass is provided on the front side of the gaming area 40 of the game board YB (see FIG. 1). ). The game area 40 is an area surrounded by ball guide rails UR (see FIG. 5) arranged on the surface of the game board YB.

On the other hand, as shown in FIGS. 2 and 3, in the lower mounting portion 6, a firing mechanism 21 is arranged approximately in the center in the left-right direction, and a speaker 17 is arranged on the right side of the firing mechanism 21. As shown in FIG. 3, this firing mechanism 21 includes a support plate 22 made of sheet metal, a firing rail 23 mounted on the front surface of the support plate 22, and a game ball mounted on the front surface of the support plate 22 for firing game balls. a ball holding part 25 that holds the ball at a firing standby position 24 on the firing rail 23; a striking mallet 27 that is swingably supported around a drive shaft 26 in the front-rear direction on the front surface of the support plate 22; and a back side of the support plate 22. A dispensing/discharging control board 70 is provided with a discharging motor that is attached to the striking hammer 27 and drives the striking mallet 27 in the striking direction via the drive shaft 26.

<Explanation of the external structure of the game board>
On the other hand, as shown in FIG. 5, in the game area 40 of the game board YB, a liquid crystal display device 41 made of an LCD (Liquid Crystal Display) or the like is arranged approximately at the center. This liquid crystal display device 41 divides the display area into three areas: left, middle, and right, and can independently display numbers, characters, letters (character dialogue, lyric captions, etc.), or special designs in a variable manner. It is. Decorative top decorations 42a, left decorations 42b, and right decorations 42c are provided around the liquid crystal display device 41, and on the back sides of these top decorations 42a, left decorations 42b, and right decorations 42c, A movable accessory device 43 is arranged.

As shown in FIG. 5, this movable accessory device 43 includes an upper movable accessory 43a, a left movable accessory 43b, a right movable accessory 43c, and an upper left movable accessory that performs a predetermined performance operation as the game progresses. It is composed of motors (not shown) such as two-phase stepping motors that drive the object 43d and the upper, left, right, and upper left movable accessories 43a to 43d, respectively. It should be noted that decorative lamps such as LED lamps that create a presentation effect by decorating with light are arranged on these upper, left, right, and upper left movable accessories 43a to 43d.

On the other hand, a special symbol 1 starting port 44 is arranged directly below the liquid crystal display device 41, and a special symbol 1 starting port switch 44a (see FIG. 6) for detecting winning balls is provided inside the special symbol 1 starting port 44. Then, a predetermined number (for example, 4) of the effective number of winning balls detected by this special symbol 1 starting port switch 44a (see FIG. 6), that is, the number of first starting pending balls, will be displayed on the liquid crystal display device 41. . In addition, this first starting pending ball count is incremented by 1 (+1) when a game ball enters the special symbol 1 starting port 44 and is detected by the special symbol 1 starting port switch 44a (see FIG. 6). When the variable display of a special symbol such as a number, character, or symbol (decorative symbol) begins, it is subtracted by 1 (-1).

On the other hand, a special symbol 2 starting port 45 is arranged on the lower right side of the liquid crystal display device 41, and a special symbol 2 starting port switch 45a (see FIG. 6) for detecting winning balls is provided inside the special symbol 2 starting port 45. Then, a predetermined number (for example, 4) of the effective number of winning balls detected by the special symbol 2 starting port switch 45a (see FIG. 6), that is, the number of second starting pending balls, will be displayed on the liquid crystal display device 41. . In addition, this second starting pending ball count is incremented by 1 (+1) when a game ball enters the special symbol 2 starting port 45 and is detected by the special symbol 2 starting port switch 45a (see FIG. 6). When the variable display of a special symbol such as a number, character, or symbol (decorative symbol) begins, it is subtracted by 1 (-1).

On the other hand, this special symbol 2 starting opening 45, as shown in FIG. 5, is equipped with an opening/closing member 45b, and when this opening/closing member 45b is opened, the game ball is in a state where it is easy to win. This opening/closing member 45b is opened for a predetermined number of times and for a predetermined time when a normal symbol lottery is won, which will be described later, and the opening/closing operation is controlled by a normal electric accessory solenoid 45c (see FIG. 6). Note that hereinafter, a device including such an opening/closing member 45b and a normal electric accessory solenoid 45c may be referred to as a normal electric accessory.

On the other hand, on the right side of the special symbol 1 starting port 44, as shown in FIG. 5, a winning device 46 is arranged. This winning device 46 opens and closes in such a way that a big winning opening (not shown), which is closed by an opening/closing door 46a, is opened when a special symbol lottery to be described later is won, that is, when a special game state occurs due to a jackpot. The door 46a is driven and controlled by a special electric accessory solenoid 46b (see FIG. 6), and the game ball can enter the grand prize opening (not shown). Incidentally, the game ball that enters the big winning hole (not shown) is detected as a winning ball by the big winning hole switch 46c (see FIG. 6) provided inside the big winning hole (not shown).

On the other hand, when the special symbol lottery is not won, that is, when the special game state is not in effect, the opening/closing door 46a is driven and controlled by the special electric accessory solenoid 46b (see FIG. 6), and the grand prize opening (not shown) is driven. is closed. As a result, the game ball cannot enter the big prize opening (not shown). Note that hereinafter, a device including such an opening/closing door 46a and a special electric accessory solenoid 46b may be referred to as a special electric accessory.

On the other hand, in the upper right part of the liquid crystal display device 41, as shown in FIG. (see FIG. 6). In addition, general winning holes 48 are arranged on the right side of the winning device 46 and on the left side of the special symbol 1 starting hole 44, respectively. This general winning hole 48 includes an upper right general winning hole 48a located on the right side of the above-mentioned prize entry device 46, an upper left general winning hole 48b located on the left side of the special symbol 1 starting hole 44, and a left middle general winning hole 48a. It consists of an opening 48c and a lower left general winning opening 48d. An upper right general winning opening switch 48a1 (see FIG. 6) is provided inside the upper right general winning opening 48a to detect the passage of a game ball, and an upper left general winning opening switch 48a1 (see FIG. 6) is provided inside the upper left general winning opening 48b to detect the passage of a gaming ball. A general winning hole switch 48b1 (see FIG. 6) is provided, and a left center general winning hole switch 48c1 (see FIG. 6) for detecting passage of a game ball is provided inside the left middle general winning hole 48c, and a lower left general winning hole switch 48c1 (see FIG. 6) is provided. Inside the opening 48d, there is provided a lower left general winning opening switch 48d1 (see FIG. 6) that detects passage of a game ball.

On the other hand, an out port 49 is arranged directly below the special symbol 1 starting port 44, into which a game ball (out ball) that has flowed down to the most downstream part of the gaming area 40 without winning a prize enters. The game ball that enters the out port 49 is detected as a non-winning ball by the out port switch 49a (see FIG. 6) provided inside, and the above-mentioned winning ball also enters the back side of the game board 4. Since it flows down to the most downstream part, it is detected by the outlet switch 49a (see FIG. 6). Therefore, the outlet switch 49a (see FIG. 6) detects the total number of ejected outs, that is, the same number of game balls as the game balls fired into the game area 40 by the firing handle 16.

On the other hand, on the lower right peripheral edge of the gaming area 40 of the game board 4, three 7 segments are arranged side by side, two of which are special symbol display devices 50, and the other 7 segment display devices 52a displays the special symbol 1, special symbol 2, the number of starting and pending balls of the normal symbol, and the game state. As shown in FIG. 5, this special symbol display device 50 is composed of a special symbol 1 display device 50a and a special symbol 2 display device 50b, and on the left side of the special symbol 1 display device 50a, one A normal symbol display device 51 consisting of an LED is provided, and furthermore, a round lamp 52b for informing the number of rounds of the jackpot game and a right-handed hitting notification lamp 52c for notifying right-handed hitting are provided.

Further, an identification lamp device 50A indicating identification information corresponding to the special symbol 1 and the special symbol 2 is provided on the upper end side of the left decoration 43b.

This identification lamp device 50A has first and second identification lamps 50Aa and 50Ab for informing the player of information that the special symbol 1 and the special symbol 2 are changing, or that the special symbol 1 and the special symbol 2 have won or lost. have. The first identification lamp 50Aa corresponds to the special symbol 1, and the second identification lamp 50Ab corresponds to the special symbol 2. Then, when the special symbol 1 is changing, the first identification lamp 50Aa blinks, when the special symbol 1 is a hit, the first identification lamp 50Aa lights up, and when the special symbol 1 is a loss, the first identification lamp 50Aa goes out. Furthermore, when the special symbol 2 is changing, the second identification lamp 50Ab blinks, when the special symbol 2 is a hit, the second identification lamp 50Ab lights up, and when the special symbol 2 is a loss, the second identification lamp 50Ab blinks. 50Ab turns off the light.

Although not shown, a plurality of game nails are arranged in the game area 40 of the game board 4, and a windmill 53 is arranged as a member for changing the falling direction of the game ball.

<Explanation of the external configuration of the back of the pachinko machine>
Thus, as shown in FIG. 4, the back side of the pachinko game machine 1 constructed in this manner has a frame-like back mechanism plate 54 attached thereto, which covers the game board mounting frame 18 and presses the game board YB from the back side. There is. A game ball storage tank 55 is provided on the upper right side of the back mechanism board 54 to store game balls supplied from a game ball supply device (not shown) of the pachinko hall side island equipment, and furthermore, A tank rail 56 is provided to lead out the balls from the game ball storage tank 55.

A payout device 57 and a payout passage 58 are attached to the inclined lower end of the tank rail 56, and when a game ball enters a winning hole such as a big winning hole (not shown), or a game ball lending device (not shown), the game balls in the game ball storage tank 55 are paid out by the payout device 57 via the tank rail 56, and the game balls are passed through the payout passage 58 into the upper tray 9 ( (see Figure 1).

Further, a transparent back cover 59 (see also FIG. 3) that is detachably attached to the back side of the game board YB is installed approximately in the center of the back mechanism board 54. A transparent sub-control board case 80a housing the control board 80 is provided in a detachable manner. A transparent main control board case 60a housing the main control board 60 inside is removably provided below the sub-control board case 80a. A transparent payout/firing control board case 70a containing a board 70 is provided in a detachable manner. Further, below the main control board case 60a, a power board case 130a housing a power board 130 is removably provided.

<Description of control device>
Next, a control device that is provided in the pachinko game machine 1 having the external configuration as described above and performs electronic control according to the progress of the game will be explained using FIG. 6. As shown in FIG. 6, this control device includes a main control board 60 that controls overall gaming operations, a payout/launch control board 70 that pays out game balls based on control commands from the main control board 60, It mainly consists of a sub-control board 80 that controls images, light, and sound.

<Explanation regarding the main control board>
The main control board 60 is a one-chip microcomputer consisting of a main control CPU 600a, a main control ROM 600b that stores game programs that describe a series of game control procedures, and a main control RAM 600c that functions as a work area, buffer memory, etc. The computer 600 displays content (performance display) regarding the ratio of how many prize balls are played when the probability is low (the winning lottery probability is a normal low probability state), and generates a special gaming state advantageous to the player. It is mainly equipped with a measurement/setting display device 610 consisting of 7 segments that also serves to display probability setting contents, a RAM clear switch 620, and a setting key switch 630.

A payout/launch control board 70 that controls the payout motor M to pay out game balls is connected to the main control board 60 configured as described above. Furthermore, a special symbol 1 starting port switch 44a that detects winning in the special symbol 1 starting port 44, a special symbol 2 starting port switch 45a that detects winning in the special symbol 2 starting port 45, and a normal symbol starting port The normal symbol start opening switch 47a detects the passage of 47, and the winning to the general winning opening 48 (upper right general winning opening 48a, upper left general winning opening 48b, middle left general winning opening 48c, lower left general winning opening 48d). The upper right general winning opening switch 48a1, the upper left general winning opening switch 48b1, the middle left general winning opening switch 48c1, the lower left general winning opening switch 48d1, and the winning opening (not shown) that is opened or closed by the opening/closing door 46a. The big winning opening switch 46c to be detected is connected to the out opening switch 49a which can detect the same number of game balls as the game balls fired into the gaming area 40 by the firing handle 16. Furthermore, a normal electric accessory solenoid 45c that controls the operation of the opening/closing member 45b, a special electric accessory solenoid 46b that controls the operation of the opening/closing door 46a, a special symbol 1 display device 50a, and a special symbol 2 display device 50b. , a normal symbol display device 51, a 7-segment display device 52a, a round lamp 52b, and a right-handed hitting notification lamp 52c are connected.

The main control board 60 configured as described above is advantageous to the player when the main control CPU 600a receives a signal from the special symbol 1 starting port switch 44a, the special symbol 2 starting port switch 45a, or the normal symbol starting port switch 47a. A lottery is conducted to determine whether to generate a special gaming state that is advantageous to the player (a so-called "win") or not to generate a special gaming state that is advantageous to the player (a so-called "lose"). The variation pattern of the special symbol, the display content of the stop symbol or the normal symbol is determined, and the determined information is transmitted to the special symbol 1 display device 50a, the special symbol 2 display device 50b, or the normal symbol display device 51. Thereby, the lottery result will be displayed on the special symbol 1 display device 50a, the special symbol 2 display device 50b, or the normal symbol display device 51. Further, the main control board 60, that is, the main control CPU 600a generates a production control command DI_CMD including the determined information, and transmits it to the sub control board 80. The main control board 60, that is, the main control CPU 600a, controls the special symbol 1 starting opening switch 44a, the special symbol 2 starting opening switch 45a, the upper right general winning opening switch 48a1, the upper left general winning opening switch 48b1, and the middle left general winning opening switch. 48c1, lower left general winning port switch 48d1, when receiving signals from the big winning port switch 46c, determines how many game balls to pay out to the player, and pays out a payout control command PAY_CMD containing the determined information. - By transmitting to the launch control board 70, the payout/launch control board 70 will pay out game balls to the player.

In addition, as a result of the lottery, if a lottery with a normal symbol is won, the normal electric accessory solenoid 45c is drive-controlled so that the opening/closing member 45b is opened a predetermined number of times and for a predetermined time, and if a lottery with a special symbol is won, The special electric accessory solenoid 46b is controlled to open a grand prize opening (not shown).

On the other hand, the main control board 60, that is, the main control CPU 600a, includes a special symbol 1 starting opening switch 44a, a special symbol 2 starting opening switch 45a, an upper right general winning opening switch 48a1, an upper left general winning opening switch 48b1, and a middle left general winning opening switch. 48c1, every time a signal is received from the lower left general winning port switch 48d1 and the big winning port switch 46c, the number of prize balls is counted, and each time a signal from the out port switch 49a is received, the total number of ejected game balls is calculated. Measure. Then, the main control board 60, that is, the main control CPU 600a, based on the measured number of prize balls and the total number of ejected game balls, displays content (performance display) regarding the ratio of how many prize balls were played at low accuracy. Output to measurement/setting display device 610. As a result, the measurement/setting display device 610 displays content (performance display) regarding the ratio of how many prize balls were played during low accuracy.

Furthermore, the measurement/setting display device 610 is capable of displaying the setting content of the probability of generating a special gaming state advantageous to the player, for example, in six levels from "1" to "6". . Therefore, when changing such settings, a special key is inserted into the setting key switch 630, and when turned on, the RAM clear switch 620 changes the probability of generating a special gaming state advantageous to the player. For example, the settings can be changed in six stages from "1" to "6" (for example, setting "6" has the highest probability of generating a special game state advantageous to the player. , setting "1" has the lowest probability of generating a special gaming state advantageous to the player). The settings changes are then displayed on the measurement/settings display device 610, and when the settings changes are confirmed, the dot at the bottom right of the 7 segments lights up, indicating that the settings have been finalized. It has become.

On the other hand, the RAM clear switch 620 clears all the memory areas of the main control RAM 600c (see FIG. 6) when the RAM clear switch 620 is pressed other than when a dedicated key is inserted into the setting key switch 630 and turned on. Instead, only some memory areas are cleared.

<Explanation regarding payout/launch control board>
The payout/launch control board 70 receives the payout control command PAY_CMD from the main control board 60 (main control CPU 600a), and generates a payout motor signal based on the received payout control command PAY_CMD. Then, the generated payout motor signal controls the payout motor M to pay out game balls to the player. Further, the payout/launch control board 70 performs an operation to shoot game balls in response to a player's operation based on a prize ball count signal indicating a payout operation of game balls and a status signal related to an abnormality in the payout operation. Performs processing to start or stop.

On the other hand, a touch sensor is provided on the periphery of the firing handle 16 shown in FIG. Then, it is output to the payout/launch control board 70. In response to this, the payout/emission control board 70 will transmit the detection signal to the main control board 60 (main control CPU 600a). Then, the main control board 60 (main control CPU 600a) will transmit the detection signal to the sub control board 80 as the production control command DI_CMD. This makes it possible to transmit information as to whether or not the player touched the handle 16 to play the game to the sub-control board 80.

<Explanation regarding the sub control board>
The sub-control board 80 receives the production control command DI_CMD from the main control board 60 (main control CPU 600a), executes and controls various productions, and also controls the display image displayed on the liquid crystal display device 41. , a sub-one-chip microcomputer consisting of a sub-control ROM 800b that stores a control program that describes production control procedures, a production scenario table PR_TBL shown in FIG. 7, etc., and a sub-control RAM 800c that functions as a work area, buffer memory, etc. It is equipped with 800.

Furthermore, the sub-control board 80 includes a sound LSI 801 that generates desired BGM and sound effects, a sound RAM 802 that functions as a work area, a buffer memory, etc., and displays information on the liquid crystal display device 41 based on instructions from the sub-one-chip microcomputer 800. A VDP 803 that generates image data to be compressed, a work area for decompressing video compressed data, a frame buffer area that temporarily stores image data displayed on the liquid crystal display device 41, and a DDR2 SDRAM 804 for still image compression. A game ROM 805 is installed in which data, CG data such as moving image compressed data, and sound data such as BGM and sound effects are stored in advance. Note that the still image is a so-called sprite image, and represents a single image such as text data such as characters, a background image, or a special design. Furthermore, a moving image refers to a collection of continuously changing still images (multiple frames), and by continuously drawing multiple still images on the liquid crystal display device 41, smooth operation is possible. is to be reproduced.

The sub-control board 80 configured in this way is connected to a decorative lamp board 90 on which decorative lamps such as LED lamps for producing lamp effects are mounted, and further includes built-in lamps (not shown). ) A push-button performance button device 13 that can be pressed by the player to change the performance effect when the light is turned on is connected, and a speaker 17 that emits BGM, sound effects, etc. is connected. Further, a movable accessory device 43 is connected to the sub-control board 80, which performs a predetermined performance operation as the game progresses, and the special symbol 1 and the special symbol 2 are changing, or the special symbol 1 and the special symbol An identification lamp device 50A for informing the player of information on winning or losing of 2 is connected, a setting button 15 that allows various settings is connected, and a liquid crystal display device 41 is connected. Needless to say, this decorative lamp board 90 also includes decorative lamps arranged on the upper, left, right, and upper left movable accessories 43a to 43d.

Thus, the sub-control board 80 configured in this way operates based on the special symbol fluctuation pattern based on the lottery result transmitted from the main control board 60 (main control CPU 600a), the current gaming state, the number of balls on hold for starting, and the lottery result. The sub-control CPU 800a receives the production control command DI_CMD, which includes basic information necessary for the decorative patterns etc. to be stopped. Then, the sub-control CPU 800a determines by lottery a performance pattern corresponding to the received performance control command DI_CMD from among a large number of performance patterns stored in advance in the sub-control ROM 800b, and executes the determined performance pattern. The instructing control signal is temporarily stored in the sub control RAM 800c.

The sub-control CPU 800a transmits to the sound LSI 801 a control signal related to sound among the control signals for instructing execution of the effect pattern stored in the sub-control RAM 800c. In response to this, the sound LSI 801 reads sound data corresponding to the control signal from the game ROM 805 or sound RAM 802 and outputs it to the speaker 17. As a result, the speaker 17 emits BGM and sound effects corresponding to the above-determined performance pattern.

Further, the sub-control CPU 800a transmits a control signal related to light to the decorative lamp board 90 among the control signals for instructing execution of the effect pattern stored in the sub-control RAM 800c. As a result, the decorative lamp board 90 performs control to turn on or turn off decorative lamps such as LED lamps that produce a lamp effect, so that a lamp effect corresponding to the determined effect pattern is executed. .

Then, the sub-control CPU 800a transmits to the VDP 803 a command list related to images among the control signals for instructing execution of the effect pattern stored in the sub-control RAM 800c. As a result, the VDP 803 generates image data to display an image based on the command list, and sends the generated image data to the liquid crystal display device 41, thereby displaying an image corresponding to the determined effect pattern. It will be displayed on the liquid crystal display device 41.

Further, the sub-control CPU 800a transmits to the movable accessory device 43 a control signal related to the movable accessory among the control signals for instructing execution of the performance pattern stored in the sub-control RAM 800c. Thereby, the movable accessory device 43 will move in accordance with the performance pattern determined above.

<Explanation of the production scenario table>
Here, the performance scenario table PR_TBL stored in the sub control ROM 800b will be explained in detail using FIG. 7. As shown in FIG. 7(a), the performance scenario table PR_TBL stores a plurality of performance scenario data PS_DATA corresponding to the performance pattern determined by the sub-control CPU 800a. The performance scenario data PS_DATA stores a plurality of pieces of one-layer data PS_DATA1, which are data for each layer used when drawing image data to be displayed on the liquid crystal display device 41. As shown in FIG. 7B, this one layer data PS_DATA1 includes frame data PS_DATA10 for drawing 1 frame to 10 frames, control code data PS_DATA11, and a position when displaying on the liquid crystal display device 41. Coordinate data PS_DATA12, pixel calculation data PS_DATA13 such as image transformation, enlargement, reduction, transparency, etc., and scaling data PS_DATA14 indicating image enlargement and reduction are stored. Furthermore, the sound data PS_DATA15 indicating the sound emitted from the speaker 17, the movable accessory data PS_DATA16 for moving the movable accessory device 43, and the lighting or display of a decorative lamp such as an LED lamp that produces a lamp effect. Lamp data PS_DATA17 for turning off the light is stored.

Furthermore, the control code data PS_DATA11 stores the address of the sub-control ROM 800b in which the control table CH_TBL shown in FIG. . That is, the control table CH_TBL stores a plurality of character data CH_DATA, as shown in FIG. address data PS_DATA 111 indicating the address address of , image size data PS_DATA 112 indicating the image size, button data PS_DATA 113 indicating validity/invalidity of the repeated press effect of the setting button 15 or the press effect of the effect button device 13, and the movable accessory device 43. Movable accessory timing data PS_DATA114 indicating the timing to start moving the movable accessory is stored. As a result, the control code data PS_DATA11 refers to one character data CH_DATA from among the plurality of character data CH_DATA stored in the control table CH_TBL shown in FIG. 7(c). Note that the one-layer data PS_DATA1 stored in the production scenario data PS_DATA is stored in order of priority, starting from the lowest priority, and the video is stored in the lowest priority position from the control table CH_TBL shown in FIG. 7(c). Control code data PS_DATA11 that refers to the data PS_DATA110 shown in FIG. PS_DATA11 is stored.

<Explanation of VDP>
On the other hand, the VDP 803 that generates image data to be displayed on the liquid crystal display device 41 is configured as shown in FIG.

As shown in FIG. 8, the VDP 803 includes an interface circuit (I/F) 8030 for the DDR2SDRAM 804, an interface circuit (I/F) 8031 for the game ROM 805, and an interface circuit (I/F) for the sub-one-chip microcomputer 800. ) 8032 is built-in. Further, the VDP 803 includes a system control register 8033 that is accessed from the sub-one-chip microcomputer 800 (sub control CPU 800a) via an interface circuit (I/F) 8032, a command memory 8034 that stores a command list, and a command memory 8034 that stores a command list. A command parser 8035 for analysis, a CG memory controller 8036 for controlling reading of data in the game ROM 805, a still image decoder 8037 for decoding compressed still image data, a video decoder 8038 for decoding compressed video data, and a still image decoder. The images decoded (expanded) by the video decoder 8037 and the video decoder 8038 are processed by a geometry engine 8039 that performs affine transformations and projection transformations such as enlargement, reduction, rotation, and movement; A rendering engine 8041 that generates image data, a DDR2SDRAM controller 8042 that controls reading and writing of data in the DDR2SDRAM 804, and an image data generated by the rendering engine 8041 to the liquid crystal display device 41. The display controller 8043 includes a display controller 8043 that controls display timing, etc., and an LVDS transmitter 8044 that transmits image data to the liquid crystal display device 41 in an LVDS (Low Voltage Differential Signaling) format.

The system control register 8033 is a register group in which the sub-one-chip microcomputer 800 (sub-control CPU 800a) writes instruction data for the VDP 803, and a register from which the sub-one-chip microcomputer 800 (sub-control CPU 800a) reads information indicating the operating state of the VDP 803. It is roughly divided into groups. As a result, the sub-one-chip microcomputer 800 (sub-control CPU 800a) operates the VDP 803 as appropriate by writing necessary setting values into predetermined input registers, and operates the VDP 803 by referring to the values of the necessary output registers. It becomes possible to grasp the status.

On the other hand, the command memory 8034 stores a command list, and this command list is sent from the sub-one-chip microcomputer 800 (sub-control CPU 800a) via the interface circuit (I/F) 8032. . To explain more specifically, the sub-one-chip microcomputer 800 (sub-control CPU 800a) stores in advance the production pattern corresponding to the production control command DI_CMD received by the main control board 60 (main control CPU 600a) in the sub-control ROM 800b. A command list is created based on the determined performance pattern, and transmitted to a command memory 8034 via an interface circuit (I/F) 8032. In response to this, the command memory 8034 stores the command list.

On the other hand, the command parser 8035 analyzes the command list stored in the command memory 8034, and by analyzing the command list, a drawing operation is executed every frame. That is, based on the analysis result of the command list by the command parser 8035, the still image decoder 8037 uses the CG memory controller 8036 to generate a still image from the address address of the game ROM 805 indicated by the address data PS_DATA111 (see FIG. 7(c)). The compressed image data is read, and the read compressed still image data is decoded (expanded). The decoded still image data is then temporarily stored in the built-in VRAM 8040.

On the other hand, based on the analysis result of the command list by the command parser 8035, the video decoder 8038 uses the CG memory controller 8036 to compress the video from the address address of the game ROM 805 indicated by address data PS_DATA111 (see FIG. 7(c)). The data is read and the read video compressed data is decoded (expanded). The decoded video data is then temporarily stored in the DDR2SDRAM 804.

In this way, the decoded (expanded) still image or moving image (one frame worth of moving image) is the analysis result of the command list by the command parser 8035, that is, the various data (frame data PS_DATA10, frame data PS_DATA10, Based on the coordinate data PS_DATA12, pixel calculation data PS_DATA13, and scaling data PS_DATA14), the geometry engine 8039 performs processing such as affine transformation such as enlargement, reduction, rotation, and movement, and projection transformation. The image data will be stored in the built-in VRAM 8040, and the video data will be stored in the DDR2SDRAM 804.

Thereafter, the rendering engine 8041 functions, the DDR2SDRAM controller 8042 reads out the video data stored in the DDR2SDRAM 804, and the rendering engine 8041 draws the video data. Next, still image data is read from the built-in VRAM 8040, and the still image data is drawn. Thereby, the still image data is overwritten and drawn on the moving image data, thereby generating image data to be displayed on the liquid crystal display device 41. Note that this generated image data will be written into the frame buffer area in the DDR2SDRAM 804 by the DDR2SDRAM controller 8042.

In this way, the image data written in the frame buffer area is read out from the DDR2SDRAM controller 8042 by the display controller 8043 and transmitted to the liquid crystal display device 41 by the LVDS transmitter 8044. As a result, the image data generated by the rendering engine 8041 is displayed on the liquid crystal display device 41.

By the way, the image data displayed on the liquid crystal display device 41 is updated frame by frame, but the diagram is shown below so that the sub-one-chip microcomputer 800 (sub-control CPU 800a) can know when the display operation for one frame has finished. 6. VSYNC (vertical synchronization signal) shown in FIG. 8 is transmitted as an interrupt signal from the VDP 803 to the sub control CPU 800a. This allows the sub-control CPU 800a to understand that one frame of image data has been displayed on the liquid crystal display device 41. Note that this VSYNC interrupt signal is generated, for example, every 33 ms.

<Description of power supply board>
By the way, power is supplied to each of the boards described above from a power supply board 130 shown in FIG. This power supply board 130 includes a voltage generation section 1300, a voltage monitoring section 1310, and a system reset generation section 1320. This voltage generation unit 1300 receives an AC voltage of 24 V AC, which is an external power supply, supplied from a transformer (not shown) installed in a game parlor, and generates multiple types of DC voltages.The generated DC voltages are as follows: Although not shown, it is supplied to each board.

Further, the voltage monitoring unit 1310 monitors the voltage of the AC 24V AC voltage, and when this voltage is cut off or a power outage occurs and a voltage abnormality is detected, a voltage abnormality signal ALARM is sent to the main control board 60. This is what is output to. The voltage abnormality signal ALARM outputs an "L" level signal when the voltage is abnormal, and outputs an "H" level signal when the voltage is normal.

On the other hand, the system reset generation unit 1320 generates a system reset signal RST when the power is turned on, and the generated system reset signal RST is output to each board.

<Explanation of relief games and special electric support games>
Next, the rescue game and the special electric support game will be specifically explained with reference to FIGS. 9 to 14.

<Explanation of conventional games>
As shown in FIG. 9(a), in the conventional game, the normal gaming state (state without low-probability power support) shifts to the jackpot gaming state, and then shifts to the gaming state of variable probability winning or non-probable variable winning. becomes. If the game state is shifted to a variable probability winning game state, the game is shifted to a variable probability gaming state (state with high probability electricity support) and then to a jackpot gaming state. On the other hand, if the game state changes to a non-probable variable winning game state, the game state shifts to a time-saving gaming state (state with low-probability power support), and then to the jackpot game state, or the special symbol changes a predetermined number of times (for example, 100 times). ), a game will be played in which the game shifts to the normal game state (state with no low electricity support). Note that "low certainty" refers to a gaming state in which the jackpot lottery probability is low, "highly certain" refers to a gaming state in which the jackpot lottery probability is high, and "variable" gaming state refers to a gaming state in which the jackpot lottery probability is high. It is a high probability state, and the special symbol fluctuation time is shortened, and the game state is an electric support state. It shows a gaming state in which the time has been shortened and the state has become an electric support state, and the electric support means an electric chew support. Under the electric chew (ordinary electric accessory) support state, the operating rate (opening time and number of openings) of the opening/closing member 45b of the special symbol 2 starting port 45 improves, and the winning rate at the special symbol 2 starting port 45 increases. Since the winning frequency per unit time increases, the game state becomes more advantageous for the player compared to the case where there is no electric chew support state (normal game state).

<Explanation of relief game>
On the other hand, in the rescue game, as shown in FIG. 9(b), the normal game state (low probability no support state) shifts to the jackpot game state, and then the game state shifts to a probability variable win or a non-probable variable win game state. I will do it. If the game state is shifted to a variable probability winning game state, the game is shifted to a variable probability gaming state (state with high probability electricity support) and then to a jackpot gaming state. On the other hand, if the game state changes to a non-probable variable winning game state, the game state shifts to the first time-saving gaming state (state with low probability power support), and then to the jackpot game state, or the special symbol changes a predetermined number of times (for example, 100 times), a game will be played in which a transition is made to a normal game state (a state with no low electricity support).

However, the flow of the game described above is the same as the conventional game. The difference between this rescue game and the conventional game is that, as shown in FIG. 9(b), the special symbol changes from the normal game state (no low voltage support state) for a predetermined number of times (for example, 1000 times). When executed, the game moves to the second time-saving game state (state with low power support), and then moves to the jackpot game state, or the variation of the special symbol reaches a predetermined number of times (for example, 1000 times). The difference is that the game is then played in such a way that the game shifts to a normal game state (state with no low voltage support).

By providing such a game, it is possible to add a purpose to playing the game other than winning a jackpot, and furthermore, it is possible to reduce the disadvantage to the player caused by not winning a jackpot for a long time.

By the way, in the above-mentioned relief game, the following processing is performed in this embodiment.

That is, as shown in FIG. 9(b), when transitioning from the non-probability variable winning gaming state to the first time-saving gaming state (state with low-probability power support), the ending of the jackpot performance in the non-probable variable winning gaming state Then, on the liquid crystal display device 41, a game state notification image after the end of the jackpot effect indicating the first time-saving game state such as "chance time entered 100 times" and a time-save number indicating the maximum number of fluctuations in which the first time-saving game state can be maintained. The time-saving rush effect including the notification will be executed by the sub-control CPU 800a. However, when the special symbol is changed a predetermined number of times (e.g., 1000 times) and the transition to the second time-saving gaming state (state with low power support) is performed, the special symbol for the predetermined number of times (e.g., 1000 times) For example, when a special symbol changes for the 1001st time, the sub-control CPU 800a does not execute the time-saving entry performance when the symbol changes, and immediately after transitioning to the second time-saving game state (state with low electricity support), the liquid crystal display A time-saving effect, such as displaying an image on the display device 41 that urges the player to "play right", will be executed. As a result, the opening/closing member 45b of the special symbol 2 starting port 45 is opened immediately after the player hits the right hand, so the player can enjoy a time-saving game, thereby improving the player's interest. be able to. In addition, when entering the second time-saving gaming state, the special symbol 2 is changed which may result in a gaming state advantageous to the player compared to the special symbol 1, so the second time-saving gaming state ( For example, immediately after transitioning to the state with low power support (state with low power support), when the special symbol changes for the 1001st time, the time-saving rush effect takes longer than the fluctuation in the normal game state (state without low power support), and the sub This will be executed by the control CPU 800a. Thereby, it is possible to store the second start reservation balls, and it is possible to prevent the first start reservation balls from being consumed immediately after entering the second time-saving game state. In addition, since the time-saving effect to enter the second time-saving game state is performed during the fluctuation, it is better to shorten the effect time and display it more concisely than the time-saving effect to enter the first time-saving game state. At this time, since the performance time is short, unlike the time-saving performance that enters the first time-saving game state, only the display indicating the second time-saving game state such as "Help time entry" is displayed, and the second time-saving game state is maintained. It is preferable not to display the number of times.

On the other hand, in the present embodiment, the average fluctuation time per fluctuation in the deviation fluctuation in the first time saving gaming state (state with low electricity support support) and the deviation fluctuation in the second time saving gaming state (state with low electricity guarantee support) The average fluctuation time per fluctuation is set to be different. In other words, the average change per change in the number of time savings in the first time saving game state (state with low power guarantee support) and the number of time reductions in the second time saving game state (state with low power guarantee support), whichever has the greater number of time savings. It is set to take less time. This makes it possible to improve the fluctuating efficiency, thereby increasing the player's interest.

On the other hand, the first time-saving gaming state (state with low power support) is used in the latter half of the jackpot performance to make the player expect whether or not there will be a jackpot again before transitioning to the normal gaming state after the jackpot performance. However, compared to the first half of the jackpot performance, the ratio of selections that are out of reach has been increased. On the other hand, in the second time-saving game state (state with low power support), the number of fluctuations is greater than the first time-saving game state, so the selection ratio of out-of-reach is lowered as the second half of the second time-saving game state progresses. . This makes it possible to improve the fluctuating efficiency, thereby increasing the player's interest.

On the other hand, as shown in FIG. 9(b), when the special symbol miss fluctuation is executed a predetermined number of times (for example, 1000 times) and the transition to the second time-saving gaming state (state with low electricity support), the sub-control The CPU 800a executes a time-saving effect such as displaying an image on the liquid crystal display device 41 that prompts the player to "hit the right hand," but when transitioning to the second time-saving game state (state with low power support) , Even if a special symbol lottery is won and a jackpot is achieved, the sub-control CPU 800a can save time by displaying an image on the liquid crystal display device 41 encouraging the player to hit right. The rush effect is executed first, and the effect changes from the middle. Therefore, when shifting to the second time-saving game state (state with low power support), if the special symbol lottery is won and it becomes a jackpot, a part of the same performance as the time-saving rush performance will be performed, If the right hit notification is given at the start of the time-saving performance, the player will not be able to judge whether it is a hit or a miss, thereby improving the player's interest. In other words, when transitioning to the second time-saving gaming state (state with low power support), if you win a lottery with a special symbol and it becomes a jackpot, the time-saving entry effect will not be performed and the winning fluctuations such as reach will be performed, while the special If a time-saving effect is performed when a symbol is not won in the lottery and the result is a loss, the player will be able to judge whether it is a win or a loss, thereby reducing the player's interest. This will result in you being forced to do so. Therefore, in this embodiment, when transitioning to the second time-saving game state (state with low power support), if a special symbol lottery is won and it becomes a jackpot, a performance that is partially common to the time-saving rush performance is performed. , A right-handed notification is made at the start of the time-saving rush performance. Further, when shifting to the second time-saving game state (state with low electric power support), a right-hand hitting notification lamp 52c (see FIG. 5) for notifying right-hand hitting is turned on at the start of the 1001st special symbol variation. At this time, when transitioning to the second time-saving gaming state (state with low power support), if you win the special symbol lottery and hit the jackpot, you will be notified on the LCD that you have hit the jackpot in the fanfare performance that will be followed by the start of the jackpot. In order to display the information on the entire liquid crystal of the display device 41, the right-handed hit notification may be temporarily hidden. In this case, by lighting the right-handed hitting notification lamp 52c (see FIG. 5) and continuing the right-handed hitting notification, the right-handed hitting display that was started due to the transition to the second time-saving gaming state will be hidden. As a result, the player can continue playing right-handed without hesitating whether or not to continue playing right-handed.

On the other hand, as shown in FIG. 9(b), the special symbol is changed a predetermined number of times (for example, 1000 times) and before the transition to the second time-saving gaming state (state with low power support), the power supply When the power is turned on again and the game is resumed, the sub-control CPU 800a displays on the liquid crystal display device 41 the remaining number of times up to the predetermined number of times (for example, 1000 times). A background image (image) is made different from the background image (image) at the time of returning to the game, or a part of the lighting of the decorative lamp is made different from the lighting of the decorative lamp at the time of returning to the game. This allows the hall side to know which gaming machines 1 have played the game close to the predetermined number of times (for example, 1000 times), thereby making it possible to correct any disadvantages on the hall side. In other words, if the power supply is cut off after the special symbol has been executed 900 times at the end of the previous day's business, the special symbol will be 100 times worse in the next day's business. If the game is executed twice, a transition will be made to the second time-saving game state (state with low electricity support). In this case, the hall side may unintentionally provide the second time-saving gaming state to the player by executing the relief game for the number of fluctuations on the previous day over several days, thereby putting the hall side at a disadvantage. becomes. Therefore, in this embodiment, the gaming machine 1 that has played the game close to the predetermined number of times (for example, 1000 times) is notified to the hall side. As a result, an employee on the hall side can take measures such as pressing the RAM clear switch 620 and clearing the main control RAM 600c in which the number of fluctuations in special symbols is held. Disadvantages can be corrected.

On the other hand, as shown in FIG. 9(b), the special symbol is changed a predetermined number of times (for example, 1000 times) and before the transition to the second time-saving gaming state (state with low power support), the power supply If the power has been cut off (power outage), when the power is turned on again and the game is resumed, the sub-control CPU 800a will repeat the above-mentioned predetermined number of times (for example, 1000 times) in the variation of the special symbol in the first rotation after returning to the game. The performance will be executed according to the number of times remaining. As a result, the player may continue to hold the number of fluctuations in which the special symbol lost at the end of the previous day's business, or the RAM clear switch 620 is pressed and the main control RAM 600c holding the number of fluctuations in which the special symbol loses is cleared. It is possible to estimate whether the game has been cleared or not, thereby increasing the player's motivation to continue playing the game.

On the other hand, in the normal gaming state (state without low electric power support) as shown in FIG. This will give a warning, such as displaying an image that prompts you to do so. However, as shown in FIG. 9(b), when the special symbol miss variation is executed a predetermined number of times (for example, 1000 times) and the transition to the second time-saving gaming state (state with low power support) occurs, the second When a player hits the right hand due to a change in special symbols before shifting to a time-saving game state (a state with low electric power support), the above-mentioned warning is not given. As a result, it is possible to prevent a situation that reduces the interest of a player who knows the number of times it will take to shift to the second time-saving gaming state (state with low power support) shown in FIG. 9(b).

<Explanation of the game with special electric support symbol>
Next, the game of the special electric support symbol will be explained with reference to FIG. 9(c).

In the game with the special electric support symbol, as shown in FIG. 9(c), the normal game state (low probability no support state) shifts to the jackpot game state, and then the game state is either a probability variable win or a non-probability variable win. It will be moved to. If the game state is shifted to a variable probability winning game state, the game is shifted to a variable probability gaming state (state with high probability electricity support) and then to a jackpot gaming state. On the other hand, if the game state changes to a non-probable variable winning game state, the game state shifts to the first time-saving gaming state (state with low probability power support), and then to the jackpot game state, or the special symbol changes a predetermined number of times (for example, 100 times), a game will be played in which a transition is made to a normal game state (a state with no low electricity support).

However, the flow of the game described above is the same as the conventional game. The difference between this special electric support symbol game and the conventional game is that, as shown in FIG. 9(c), the game changes from the normal game state (low electric support no state) to the special electric support symbol (no jackpot operation). If you win, you will move to the second time-saving game state (state with low power support), and then move to the jackpot game state, or if the special symbol changes a predetermined number of times (for example, 100 times or more). , the difference is that the game is played by shifting to a normal game state (state with no low power support).

By providing such a game, it is possible to add a purpose to playing the game other than winning a jackpot, and furthermore, it is possible to reduce the disadvantage to the player caused by not winning a jackpot for a long time.

Thus, in the game with special electric support symbols as described above, in this embodiment, the following processing is performed.

9(c) or 9(b), the special symbols change a predetermined number of times (for example, 100 times) from the first time saving state (state with low power support) and the normal gaming state (low power support state). When returning to the state (without electric support), the sub-control CPU 800a displays the result performance on the liquid crystal display device 41 (wins ○○ times, number of acquisitions ○○○ points, etc.). However, when the special symbol changes from the second time-saving game state (state with low power support) shown in FIG. ), or when the special symbol changes reach a predetermined number of times (for example, 1000 times) from the second time-saving game state (state with low power support) shown in FIG. 9(b), the normal game state (low power support state) When returning to the state (without electric support), the sub-control CPU 800a controls the liquid crystal display device 41 so that the result effect is not displayed after a predetermined number of final fluctuations. Thereby, appropriate information can be provided to the player. That is, in the second time-saving game state (state with low power support) shown in FIG. 9(c) or in the second time-saving game state (state with low power support) shown in FIG. Since the result is not passed through the player, there is no information available to the player even if the result effect is displayed on the liquid crystal display device 41. Therefore, as shown in this embodiment, even in the same time-saving game state, if the effects are made to differ depending on the trigger for entry, appropriate information can be provided to the player.

By the way, tables as shown in FIGS. 10 to 12 are used to determine whether or not to perform the result presentation as described above. This point will be explained in detail below.

The table TBL shown in FIG. 10(a) is stored in the main control ROM 600b, and stores a variable pattern table designation code corresponding to each gaming state and a variable pattern table to be referred to. Note that the variation pattern table designation code is data for referring to the variation pattern table managed on the program.

Specifically, in the table TBL shown in FIG. 10(a), in the normal gaming state, "00H" is selected as the variable pattern table designation command, and NOR_TBL is used as the variable pattern table to be referred to. becomes. In addition, in the first time-saving game state shown in FIG. 9(b) or the first time-saving game state shown in FIG. 9(c), in the variation of the special symbol from the 1st to the 79th rotation, the variation pattern table designation command is "01H" is selected, and JT1_TBL1 is used as the fluctuation pattern table to be referred to. Then, in the first time-saving game state shown in FIG. 9(b) or the first time-saving game state shown in FIG. 9(c), in the variation of the special symbol from the 80th to the 99th rotation, the variation pattern table designation command is "02H" is selected and JT1_TBL2 is used as the fluctuation pattern table to be referred to, and in the 100th rotation special symbol fluctuation, "03H" is selected as the fluctuation pattern table designation command and as the fluctuation pattern table to be referred to. , JT1_TBL3 will be used.

On the other hand, in the second time-saving game state shown in FIG. 9(b) or the second time-saving game state shown in FIG. " is selected, and JT2_TBL1 is used as the variation pattern table to be referred to. Then, in the second time-saving game state shown in FIG. 9(b) or the second time-saving game state shown in FIG. 9(c), in the variation of the special symbol from the 2nd to the 100th rotation, the variation pattern table designation command is "05H" is selected and JT2_TBL2 is used as the variation pattern table to be referred to, and in the variation of special symbols from 101st to final rotation, "06H" is selected as the variation pattern table designation command, and the variation pattern to be referred to is JT2_TBL3 will be used as the table.

On the other hand, in the variable probability gaming state shown in FIG. 9(b) or the variable probability gaming state shown in FIG. 9(c), "07H" is selected as the variable pattern table designation command, and the variable pattern table to be referred to is HI_TBL. will be selected. Note that HI_TBL is not shown in the figure and its explanation will be omitted.

By the way, the variation pattern table NOR_TBL referred to in the normal gaming state is as shown in FIG. 10(b). Specifically, if you do not win the special symbol lottery, but lose, and the number of first starting pending balls or second starting pending balls is "0", the normal variation 12 seconds is selected with the probability shown. , with the probability shown, normal reach is selected (20 seconds), and with the probability shown, SP reach is selected (50 seconds). If there is "1" first start held ball or second start held ball, the normal variation 8 seconds is selected with the probability shown, and the normal reach deviation (20 seconds) is selected with the probability shown. With a probability of , the SP reach difference (50 seconds) will be selected. Furthermore, when there are "2" first start held balls or second start held balls, the normal variation of 5 seconds is selected with the illustrated probability, and the normal reach deviation (20 seconds) is selected with the illustrated probability, With the probability shown in the figure, SP reach deviation (50 seconds) will be selected. Furthermore, if there are "3" first start held balls or second start held balls, the normal variation 3 seconds is selected with the illustrated probability, and the normal reach deviation (20 seconds) is selected with the illustrated probability, With the probability shown in the figure, SP reach deviation (50 seconds) will be selected.

On the other hand, as shown in Figure 10(b), in the special symbol lottery, if you win the small win A of the special electric support symbol or the small win B of the special electric support symbol, the normal reach will be missed with the probability shown. + Time-saving entry performance (25 seconds) is selected, and SP reach miss + Time-saving entry performance (55 seconds) will be selected with the probability shown. In this way, when the special electric support symbol is won, a series of fluctuation patterns are selected in which a losing performance is performed during the fluctuation of the special symbol, and then a time-saving entry performance is performed.

On the other hand, as shown in FIG. 10(b), if the small win C is won in the special symbol lottery, the normal reach (20 seconds) will be selected. At this time, during the small winning operation, the sub control CPU 800a executes the small winning effect.

On the other hand, as shown in Figure 10(b), if you win the special symbol lottery and win the probability variable hit, the normal reach (30 seconds) is selected with the probability shown, and the SP reach is selected with the probability shown. (60 seconds) is selected, and (100 seconds) per total rotational variation is selected with the probability shown.

On the other hand, as shown in FIG. 10(b), if you win the special symbol lottery and win the non-probability variable hit, the normal reach hit (30 seconds) is selected with the probability shown, and the SP Per reach (60 seconds) will be selected.

Next, the variation pattern table JT1_TBL1 that is referred to in the variations of the special symbols from the 1st to the 79th rotation in the first time-saving game state is as shown in FIG. 11(a). Specifically, in the case where the special symbol 1 lottery is not won and the number of first starting pending balls is "0" to "3", the normal variation of 12 seconds is selected. Then, if you do not win the special symbol 2 lottery and it is a loss, and the number of second starting pending balls is "0", the normal fluctuation 5 seconds is selected with the probability shown, and the normal reach is a loss with the probability shown. (20 seconds) is selected, and SP reach deviation (50 seconds) is selected with the probability shown. Furthermore, if you do not win the special symbol 2 lottery and you lose, and the number of second starting pending balls is "1" to "3", the normal variation 3 seconds is selected with the probability shown, and the probability shown is Then, the normal reach is selected (20 seconds), and the SP reach is selected (50 seconds) with the probability shown.

On the other hand, as shown in FIG. 11(a), if the special electric support symbol is won in the special symbol lottery by the small win A, the normal variation of 3 seconds will be selected.

By the way, when a small hit and a special electric support symbol are used together, a process as shown in FIG. 14 will be performed. That is, if the small win A is won with a probability of 1/200, it will also be used as the special electric support symbol, and after the small win, 1000 times will be awarded as the time saving number. If the small win A of the special electric support symbol is won during the time saving game, 1000 times is not reset as the number of time saving times. On the other hand, if the small win B is won with a probability of 100/200, it will also be used as the special electric support symbol, and 100 times will be awarded as the number of time savings after the small win. When the small win B of the special electric support symbol is won during the time saving game, 100 times is not reset as the number of time saving times. On the other hand, if the small win C is won with a probability of 99/200, it is made so that it does not double as the special electric support symbol. In this way, if the small win and the special electric support symbol are used together, it is possible to provide a new gameplay feature of whether or not time is saved after a small win. It can improve people's interest.

However, even if you win the small win A of the special electric support symbol during the time saving game, the time saving is not added again, so as shown in Figure 11 (a), the special If the small win A of the electric support symbol is won, the normal variation 3 seconds which is the same variation pattern as the normal variation is selected.

On the other hand, as shown in FIG. 11(a), if the special electric support symbol wins small win B in the special symbol lottery, the normal reach miss + time-saving entry effect (25 seconds) will be selected with the probability shown. , SP reach miss + time-saving entry effect (55 seconds) is selected with the probability shown. However, if you win the small win B of the special electric support symbol during the time-saving game, as shown in FIG. It will be done. Note that the time-saving entry performance can be switched depending on each gaming state so that the sub-control CPU 800a performs a time-saving count reset performance.

On the other hand, as shown in FIG. 11(a), if the small winning C is won in the special symbol lottery, the normal variation (3 seconds) will be selected.

On the other hand, as shown in FIG. 11(a), if you win the special symbol lottery and win the probability variable hit, the normal reach (30 seconds) is selected with the probability shown, and the SP reach is selected with the probability shown. (60 seconds) is selected, per full rotation fluctuation (100 seconds) is selected with the probability shown, and per sudden change (10 seconds) is selected with the probability shown.

On the other hand, as shown in FIG. 11(a), if you win the special symbol lottery and win the non-probability variable hit, the normal reach hit (30 seconds) is selected with the probability shown, and the SP Per reach (60 seconds) will be selected.

Next, the variation pattern table JT1_TBL2 that is referred to in the variation of the special symbol from the 80th to the 99th rotation in the first time saving game state is as shown in FIG. 11(b). Specifically, in the case where the special symbol 1 lottery is not won and the number of first starting pending balls is "0" to "3", the normal variation of 12 seconds is selected. Then, if you do not win the special symbol 2 lottery and it is a loss, and the number of second starting pending balls is "0", the normal fluctuation 5 seconds is selected with the probability shown, and the normal reach is a loss with the probability shown. (20 seconds) is selected, and SP reach deviation (50 seconds) is selected with the probability shown. Furthermore, if you do not win the special symbol 2 lottery and you lose, and the number of second starting pending balls is "1" to "3", the normal variation 3 seconds is selected with the probability shown, and the probability shown is Then, the normal reach is selected (20 seconds), and the SP reach is selected (50 seconds) with the probability shown.

Therefore, as shown in FIG. 11(b), when the special symbols change from the 80th to the 99th spin near the end of the first time-saving game state, the selection ratio of reach (normal reach, SP reach) is increased. ing. This makes it possible to give the player a sense of anticipation that he or she might win.

On the other hand, as shown in FIG. 11(b), when the special electric support symbol wins the small win A in the special symbol lottery, the normal variation of 3 seconds will be selected. In addition, as shown in Figure 11(b), if you win the special electric support symbol's small win B in the special symbol lottery, the normal reach will be missed + time-saving entry effect (25 seconds) will be selected with the probability shown. , SP reach miss + time-saving entry effect (55 seconds) is selected with the probability shown.

On the other hand, as shown in FIG. 11(b), if the small win C is won in the special symbol lottery, the normal variation (3 seconds) will be selected.

On the other hand, as shown in FIG. 11(b), if you win the special symbol lottery and win the probability variable hit, the normal reach (30 seconds) is selected with the probability shown, and the SP reach is selected with the probability shown. (60 seconds) is selected, per full rotation fluctuation (100 seconds) is selected with the probability shown, and per sudden change (10 seconds) is selected with the probability shown.

On the other hand, as shown in FIG. 11(b), if you win the special symbol lottery and win the non-probability variable hit, the normal reach hit (30 seconds) is selected with the probability shown, and the SP Per reach (60 seconds) will be selected.

Next, the variation pattern table JT1_TBL3 that is referred to in the variation of the special symbol at the 100th rotation in the first time saving game state is as shown in FIG. 12(a). Specifically, if you do not win the special symbol lottery and are a loser, if the number of first starting pending balls or second starting pending balls is "0" to "3", the winning result performance (30 seconds) will be selected.

On the other hand, in the special symbol lottery, if the small win A of the special electric support symbol is won, a losing result performance (30 seconds) will be selected. However, even if you win a small hit with the special electric support symbol during the time saving game, as shown in Figure 14, since the time saving is not added again, the special electric support symbol will be won in the special symbol lottery. If the small win A is won, a winning result presentation with the same fluctuation pattern as the normal fluctuation winning will be selected.

In addition, as shown in FIG. 12(a), in the special symbol lottery, if the special electric support symbol wins the small win B, a reset performance (80 seconds) is selected from the result performance. becomes. However, if you win the small win B of the special electric support symbol during the time-saving game, as shown in FIG. A pattern will be selected.

On the other hand, as shown in FIG. 12(a), if the small winning C is won in the special symbol lottery, the losing result presentation (30 seconds) will be selected.

On the other hand, as shown in FIG. 12(a), if you win the special symbol lottery and win a probability variable win or a non-probability variable win, a series of variation patterns (100 seconds) will be selected.

Next, the variation pattern table JT2_TBL1 referred to in the variation of the special symbol of the first rotation in the second time-saving game state becomes as shown in FIG. 12(b). Specifically, as shown in FIG. 12(b), in the case where the special symbol lottery is not won and it is a loss, the first starting reserved ball or the second starting reserved ball is "0" to "3". In this case, the unsuccessful entry effect (12 seconds) will be selected.

On the other hand, as shown in FIG. 12(b), in the special symbol lottery, if the special electric support symbol wins the small win A or the small win C, the winning effect (12 seconds) will be selected. Become. If the small win B of the special electric support symbol is won, a series of fluctuation patterns (80 seconds) from the rush performance to the reset performance will be selected.

On the other hand, as shown in FIG. 12(b), if you win the special symbol lottery and win a definite variable hit, or if you win a non-probable variable hit, a series of variable patterns (100 seconds) will be selected.

Next, the variation pattern table JT2_TBL2 that is referred to in the variation of the special symbols from the 2nd to the 100th rotation in the second time saving game state becomes as shown in FIG. 12(c). Specifically, in the case where the special symbol 1 lottery is not won and the number of first starting pending balls is "0" to "3", the normal variation of 5 seconds is selected. If you do not win the special symbol 2 lottery and you lose, and the number of second starting pending balls is "0" to "3", the normal variation 1.5 seconds is selected with the probability shown in the diagram. With the probability shown, the normal reach is selected (20 seconds), and with the probability shown, the SP reach is selected (50 seconds).

On the other hand, as shown in FIG. 12(c), if you win the special electric support symbol's small win A or C in the special symbol lottery, the normal variation of 1.5 seconds will be selected. Become.

On the other hand, as shown in Fig. 12(c), if you win the small hit B of the special electric support symbol in the special symbol lottery, the normal reach will be missed + time-saving entry effect (25 seconds) will be selected with the probability shown. Then, with the probability shown in the figure, SP reach miss + time-saving entry performance (55 seconds) is selected.

On the other hand, as shown in FIG. 12(c), if you win the special symbol lottery and win a variable probability win, or if you win a non-probability variable win, the normal reach win (30 seconds) is selected with the probability shown. Then, the sudden hit (10 seconds) will be selected with the probability shown.

Next, the variation pattern table JT2_TBL3 that is referred to in the variations of the special symbols from the 101st to the final rotation in the second time-saving game state is as shown in FIG. Specifically, in the case where the special symbol 1 lottery is not won and the number of first starting pending balls is "0" to "3", the normal variation of 5 seconds is selected. If you do not win the special symbol 2 lottery and you lose, and the number of second starting pending balls is "0" to "3", the normal variation 1.5 seconds is selected with the probability shown in the diagram. With the probability of , normal reach is selected (20 seconds).

On the other hand, as shown in FIG. 13, when the special electric support symbol small win A or small win C is won in the special symbol lottery, the normal variation of 1.5 seconds will be selected.

On the other hand, as shown in FIG. 13, if you win the small hit B of the special electric support symbol in the special symbol lottery, the normal reach miss + time-saving entry effect (25 seconds) will be selected with the probability shown, With a probability of , SP reach is missed + time-saving entry performance (55 seconds) is selected.

On the other hand, as shown in FIG. 13, if you win the special symbol lottery and win a probability variable win, or if you win a non-probability variable win, the normal reach win (30 seconds) is selected with the probability shown in the illustration. The sudden hit (10 seconds) will be selected with a probability of .

Thus, using such a variation pattern table, it is selected whether or not to perform a result presentation. Therefore, in the first time-saving game state, when the first time-saving game state ends, the variation pattern table JT1_TBL3 shown in FIG. 12(a) is selected, and before the end, the fluctuation pattern table JT1_TBL3 shown in FIG. Variation pattern table JT1_TBL2 will be selected, and thus a different variation pattern table will be selected. On the other hand, in the second time-saving game state, when the second time-saving game state ends at the 100th rotation or 1000th rotation, and even before it ends, the fluctuation pattern table JT2_TBL2 shown in FIG. 12(c) is selected, or the variation pattern table JT2_TBL3 shown in FIG. 13 is selected, and thus the same variation pattern table is selected. Thereby, it is possible to select whether or not to perform a result effect, thereby making it possible to provide appropriate information to the player.

By the way, as shown in FIG. 9(b), a predetermined number of times (for example, 1000 times) the special symbol is changed and the predetermined number of times (for example, 1000 times) is executed, which triggers the transition to the second time-saving gaming state (state with low power support). The number of times may be any number of times, but it is preferable to set the number of times to be equal to or less than triple the denominator of the jackpot probability. In this way, if the denominator of the jackpot probability is set to a number less than or equal to the number tripled, the jackpot will often occur within the number of times tripled, and even if the jackpot is not hit by this number of times, the game It is possible to prevent the player from forcibly continuing the game aiming at the second time-saving gaming state (state with low electricity support) shown in FIG. 9(b).

Furthermore, when transitioning to the second time-saving game state (state with low power support) shown in FIG. 9(b), the number of time-savings granted may be any number of times, but the denominator of the jackpot probability is quadrupled. It is preferable to set the number of times less than or equal to the number given above. In this way, if the number of times is less than or equal to the number multiplied by 4 the denominator of the jackpot probability, there is a possibility that you will definitely hit the jackpot at least once by the number of times that is multiplied by 4, so you can continue playing. Benefits can be given to players.

By the way, when a large number of time savings is given (a number of time savings exceeding the denominator of the jackpot probability), the current number of time savings is not displayed on the liquid crystal display device 41 until the predetermined number of times is reached. A fixed number of times, such as 100 times, is displayed on the liquid crystal display device 41. To explain in more detail, each time the number of time reductions changes, the main control board 60 (main control CPU 600a) transmits a time reduction number command indicating the number of time reductions. Then, the sub control CPU 800a receives the time saving number command. At this time, even if the sub-control CPU 800a receives a time reduction number command indicating the number of time reductions, the sub control CPU 800a controls the current number of time reductions not to be displayed on the liquid crystal display device 41 until the number of time reductions reaches a predetermined number or less. The liquid crystal display device 41 is controlled to display a fixed number of times such as times. Then, when the predetermined number of time reductions has been reached, the sub-control CPU 800a controls the liquid crystal display device 41 to display time reduction number information based on the received time reduction number command indicating the number of time reductions. By doing so, it is possible to improve the player's interest. In other words, in the case of a large number of time savers (the number of time savers exceeding the denominator of the jackpot probability), if the time saver state continues until the next jackpot is won, if the number of time savers is displayed and counted down, the player This aggravates the anxiety of the players, thereby reducing the interest of the players. On the other hand, if the remaining number of times reaches a predetermined number, such as 100, it is better to notify the player that the time-saving game may end. It is possible to prevent a situation where the time-saving game ends without the person knowing. Therefore, according to the present embodiment, it is possible to improve the player's interest.

By the way, in this embodiment, an example was shown in which the rescue game and the special electric support symbol game are described separately, but the present invention is not limited to this, and a game that includes both games may be performed.

<Explanation of serial communication>
Next, serial communication will be specifically explained with reference to FIGS. 15 to 24.

<Main control board: Description of one-chip microcomputer>
To explain in detail, the one-chip microcomputer 600 shown in FIG. 6 has a configuration as shown in FIG. 15. That is, as explained above, the one-chip microcomputer 600 includes a main control CPU 600a, a main control ROM 600b that stores a game program that describes a series of game control procedures, and a main control ROM 600b that functions as a work area, buffer memory, etc. A control RAM 600c is mainly built in, and a clock generation circuit 640 is also built in. This clock generation circuit 640 divides the frequency of an external clock (not shown) to generate a clock used inside the one-chip microcomputer 600.

Furthermore, the one-chip microcomputer 600 has a built-in reset controller 641 as shown in FIG. It controls reset signals such as RST and an abnormality reset signal generated by WDT (watchdog timer) 643, which will be described later.

Furthermore, the one-chip microcomputer 600 has a built-in interrupt controller 642, as shown in FIG. It is something to control.

Furthermore, the one-chip microcomputer 600 has a built-in WDT (watchdog timer) 643, as shown in FIG. It is something to do. Note that this abnormal reset signal is input to the reset controller 641 and resets the inside of the one-chip microcomputer 600. Therefore, an asynchronous serial communication circuit (CH0) 646, an asynchronous serial communication circuit (CH1) 647, and a synchronous serial communication circuit 648, which will be described later, are also reset.

On the other hand, the one-chip microcomputer 600 has a built-in CTC (Counter Timer Circuit) 644, as shown in FIG. It is something that generates. Note that this timer interrupt signal is output to the interrupt controller 642 described above.

Further, the one-chip microcomputer 600 has a built-in random number circuit 645, as shown in FIG. 15, and this random number circuit 645 generates hardware random numbers used for random number lottery of special symbols.

Furthermore, the one-chip microcomputer 600 has an asynchronous serial communication circuit (CH0) 646 and an asynchronous serial communication circuit (CH1) 647 built-in to enable serial communication. This asynchronous serial communication circuit (CH0) 646 indicates a channel 0 asynchronous serial communication circuit, and the asynchronous serial communication circuit (CH1) 647 indicates a channel 1 asynchronous serial communication circuit. Therefore, the internal structure is the same. The following description will be made on the premise that the internal structures of the asynchronous serial communication circuit (CH0) 646 and the asynchronous serial communication circuit (CH1) 647 are the same.

The asynchronous serial communication circuit (CH0) 646 and the asynchronous serial communication circuit (CH1) 647 each have a built-in reception prescaler register RXPRE shown in FIG. However, since the internal structure is the same, in this embodiment, it is illustrated as one reception prescaler register RXPRE). As shown in FIG. 16(a), this reception prescaler register RXPRE consists of 16 bits, and from the least significant bit (0th bit) to the 12th bit consists of a reception baud rate setting register RPR in which the reception baud rate can be set. The 13th bit is unused, the 14th bit consists of a parity setting register RPEN that can set the presence or absence of parity, and the most significant bit (15th bit) sets odd parity or even parity. It consists of a parity odd/even setting register REVEN.

This reception baud rate setting register RPR has an initial value of 0000h and can read and write values, and can set the reception baud rate from 0000h to 1FFFh. The reception baud rate (bps) is calculated by the internal clock (clock generated by the clock generation circuit 640 shown in FIG. 15) frequency/(reception baud rate setting register RPR×32). Specifically, for example, if the internal clock (clock generated by the clock generation circuit 640 shown in FIG. 15) frequency is 20 MHz and 01F4h (=500) is set in the reception baud rate setting register RPR, the reception baud rate ( bps) is calculated as 20 (MHz)/(500×32), which is 1,250 (bps). Note that when 0000h is set in the reception baud rate setting register RPR, the calculation is performed assuming that 0001h is set in the reception baud rate setting register RPR.

On the other hand, the parity presence/absence setting register RPEN has an initial value of 0 and allows reading and writing of values. When 0 is set, no parity is set, and when 1 is set, parity is set. Further, the parity odd-even setting register REVEN has an initial value of 0 and allows reading and writing of values. When 0 is set, even parity is set, and when 1 is set, odd parity is set.

On the other hand, the asynchronous serial communication circuit (CH0) 646 and the asynchronous serial communication circuit (CH1) 647 further include a reception buffer register RXBUF shown in FIG. 16(b). This reception buffer register RXBUF has an initial value of 00h, can only read values, and can store data from 00h to FFh.

Thus, in the asynchronous serial communication circuit (CH0) 646 and the asynchronous serial communication circuit (CH1) 647, data is set in the reception baud rate setting register RPR so as to be the same as the transmission speed of the incoming data, and the parity When the presence/absence setting register RPEN is set to 0, the data shown in FIG. 18(a) can be received. That is, the asynchronous serial communication circuit (CH0) 646 and the asynchronous serial communication circuit (CH1) 647 store the start bit length of "L" level, the data of 8 bits length, and the stop bit length of "H" level in one frame ( It is possible to receive data in the communication format (see timing T10 section). This 8-bit data is then stored in the reception buffer register RXBUF.

On the other hand, in the asynchronous serial communication circuit (CH0) 646 and the asynchronous serial communication circuit (CH1) 647, data is set in the reception baud rate setting register RPR so that the transmission speed is the same as the transmission speed of the incoming data, and the parity When the presence/absence setting register RPEN is set to 1, the data shown in FIG. 18(b) can be received. That is, the asynchronous serial communication circuit (CH0) 646 and the asynchronous serial communication circuit (CH1) 647 input the start bit length of "L" level, 8-bit length data, parity bit, and stop bit length of "H" level. It is possible to receive data in a communication format of one frame (see timing T11 section). This 8-bit data is then stored in the reception buffer register RXBUF. Note that if the parity bit on the transmitting side is set to even parity, 0 is set to the parity odd-even setting register REVEN, and if it is set to odd parity, 1 is set to the parity odd-even setting register REVEN. That will happen.

By the way, the asynchronous serial communication circuit (CH0) 646 and the asynchronous serial communication circuit (CH1) 647 further include a transmission prescaler register TXPRE as shown in FIG. 17(a). , as shown in FIG. 17(a), consists of 16 bits, from the least significant bit (0th bit) to the 12th bit consists of a transmission baud rate setting register TPR that can set the transmission baud rate, and the 13th bit is , the unused 14th bit consists of a parity setting register TPEN that can set the presence or absence of parity, and the most significant bit (15th bit) is a parity odd-even setting register TEVEN that can set whether parity is odd or even parity. It consists of

The transmission baud rate setting register TPR has an initial value of 0000h, can read and write values, and can set the transmission baud rate from 0000h to 1FFFh. The transmission baud rate (bps) is calculated as the internal clock (clock generated by the clock generation circuit 640 shown in FIG. 15) frequency/(transmission baud rate setting register TPR x 32), and is calculated in the same way as the reception baud rate (bps). Ru.

On the other hand, the parity presence/absence setting register TPEN has an initial value of 0 and allows reading and writing of values. When 0 is set, no parity is set, and when 1 is set, parity is set. Further, the parity odd-even setting register TEVEN has an initial value of 0 and allows reading and writing of values. When 0 is set, even parity is set, and when 1 is set, odd parity is set.

Furthermore, the asynchronous serial communication circuit (CH0) 646 and the asynchronous serial communication circuit (CH1) 647 have a built-in transmitting buffer register TXBUF shown in FIG. The value is 00h, and only values can be written, and data from 00h to FFh can be stored.

In this way, the asynchronous serial communication circuit (CH0) 646 and the asynchronous serial communication circuit (CH1) 647 operate as shown in FIG. The data shown in (a) can be transmitted. That is, the asynchronous serial communication circuit (CH0) 646 and the asynchronous serial communication circuit (CH1) 647 store the start bit length of "L" level, the data of 8 bits length, and the stop bit length of "H" level in one frame ( It is possible to transmit data in a communication format (see timing T10 section). Note that this 8-bit length data is stored in the transmission buffer register TXBUF.

On the other hand, when the parity presence/absence setting register TPEN is set to 1, the asynchronous serial communication circuit (CH0) 646 and the asynchronous serial communication circuit (CH1) 647 can transmit the data shown in FIG. 18(b). . That is, the asynchronous serial communication circuit (CH0) 646 and the asynchronous serial communication circuit (CH1) 647 input the start bit length of "L" level, 8-bit length data, parity bit, and stop bit length of "H" level. It is possible to transmit data in a communication format of one frame (see timing T11 section). Note that this 8-bit long data is data stored in the transmission buffer register TXBUF, and the parity bit is even parity if 0 is set in the parity odd-even setting register REVEN, and 1 is set in the parity odd-even setting register REVEN. is set, it is odd parity.

By the way, as shown in FIG. 15, the one-chip microcomputer 600 has a built-in synchronous serial communication circuit 648 to enable serial communication. This synchronous serial communication circuit 648 has a built-in communication setting register SPIFM shown in FIG. 19(a). This communication setting register SPIFM consists of 8 bits, as shown in FIG. It consists of a frequency ratio setting register CLK, and from the most significant bit (7th bit) to the 4th bit consists of a data length setting register LENG that can set the data length.

The initial value of this synchronous clock frequency division ratio setting register CLK is 00h, and values can be read and written, and when 01h is set, the internal clock (the clock generated by the clock generation circuit 640 shown in FIG. 15) is set to 1. When the frequency is divided by /2 and 02h is set, the internal clock (the clock generated by the clock generation circuit 640 shown in FIG. 15) is divided by 1/4 and 09h is set. When the internal clock (the clock generated by the clock generation circuit 640 shown in FIG. 15) is divided by 1/512 and 0Ah is set, the internal clock (the clock generated by the clock generation circuit 640 shown in FIG. 15) is clock) is divided into 1/1024.

That is, as shown in FIG. 15, the frequency-divided clock frequency-divided according to the value set in the synchronous clock frequency division ratio setting register CLK is synchronized with the synchronous clock 649 built in the one-chip microcomputer 600. The signal is input to the serial communication circuit 648, and is output from the synchronous serial communication circuit 648 together with the transmission data. Note that if a value other than 01h to 0Ah is set in the synchronous clock frequency division ratio setting register CLK, no clock is output from the synchronous clock 649.

On the other hand, the data length setting register LENG can set the format of communication data, and when the initial value is 00h, values can be read and written, and when 01h is set, the data length is set to 1 bit. ..., 08h is set, the data length is set to 8 bits.

On the other hand, the synchronous serial communication circuit 648 further includes a transmission data register TRBUF shown in FIG. 19(b). This transmission data register TRBUF has an initial value of 00h, can only write values, and can store data from 00h to FFh. Note that the data stored in the transmission data register TRBUF is transferred to a transmission shift register (not shown), and is output in synchronization with the divided clock output from the synchronization clock 649.

On the other hand, the synchronous serial communication circuit 648 further includes a reception data register REBUF shown in FIG. 19(c). The reception data register REBUF has an initial value of 00h, can only read values, and can store data from 00h to FFh. Note that when synchronous serial data is received, the received data is stored in this reception data register REBUF. Note that data is stored in this receiving data register REBUF in synchronization with the frequency-divided clock transmitted from the transmitting side.

On the other hand, the synchronous serial communication circuit 648 further includes a transmission/reception status register SPIST shown in FIG. 19(d). As shown in FIG. 19(d), this transmission/reception status register SPIST is read-only and consists of 8 bits, and the lowest bit (0th bit) is a transmitting flag register indicating whether data is being transmitted or not. SPTMT, the first bit consists of a transmission shift register flag register TRSHF that indicates whether the data to be transmitted has been transferred to a transmission shift register (not shown), and the second bit is as shown in FIG. 19(b). It consists of a transmission register flag register TRREF that indicates whether data is stored in the transmission data register TRBUF shown in FIG. 19(c), and the third bit indicates whether data is stored in the reception data register REBUF shown in FIG. It is composed of a receiving register flag register REREF that indicates whether or not the data is received, and the bits from the 4th bit to the most significant bit (7th bit) are unused.

This transmitting flag register SPTMT is set to "1" when data is being transmitted, and is set to "0" when data is not being transmitted.

On the other hand, the transmission shift register flag register TRSHF is set to "0" if the data to be transmitted has not been transferred to the transmission shift register (not shown), and if the data to be transmitted has already been transferred to the transmission shift register (not shown). In this case, "1" is set.

On the other hand, the transmission register flag register TRREF is set to "0" when no data is stored in the transmission data register TRBUF shown in FIG. 19(b), and the transmission data register TRREF is set to "0". If data is stored in TRBUF, "1" is set.

On the other hand, the reception register flag register REREF is set to "0" when no data is stored in the reception data register REBUF shown in FIG. 19(c), and If data is stored in REBUF, "1" is set.

Thus, the one-chip microcomputer 600 configured as described above transmits predetermined data to the payout/launch control board 70 by serial transmission using the asynchronous serial communication circuit (CH0) 646 shown in FIG. , the asynchronous serial communication circuit (CH1) 647 is used to transmit predetermined data to the sub-control board 80 by serial transmission. Although the synchronous serial communication circuit 648 is not used in this embodiment, it may be used when serially transmitting predetermined data to the payout/launch control board 70 or the sub-control board 80.

<Payout/launch control board: Description of payout control one-chip microcomputer>
Here, the payout/launch control board 70 will be explained in detail using FIG. 20. Note that the sub-control board 80 is equipped with a serial communication circuit similar to the payout/launch control board 70, so a description thereof will be omitted. Further, the same components as the one-chip microcomputer 600 shown in FIG. 15 are denoted by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 20, the payout/launch control board 70 includes a payout control CPU 700a, a payout control ROM 700b that stores a payout program that describes a series of payout control procedures, and a payout control ROM 700b that functions as a work area, buffer memory, etc. It is equipped with a payout control one-chip microcomputer 700 mainly composed of a RAM 700c. This payout control one-chip microcomputer 700 further has an external bus interface 701 built in, and this external bus interface 701 controls the direction of the address bus, data bus, and each control signal.

Further, as shown in FIG. 20, the payout control one-chip microcomputer 700 has a built-in clock circuit 702, and this clock circuit 702 divides the frequency of an external clock (not shown) to A clock used inside the computer 700 is generated. Note that the synchronous clock 649 shown in FIG. 20 is a clock used inside the payout control one-chip microcomputer 700 that is frequency-divided.

Further, as shown in FIG. 20, the payout control one-chip microcomputer 700 has a built-in reset controller 703, and a WDT (watchdog timer) 703a is built inside the reset controller 703. This WDT 703a detects a program abnormality due to noise or the like and generates an abnormality reset signal. The reset controller 703 controls reset signals such as the system reset signal RST generated by the system reset generation unit 1320 (see FIG. 6) and the abnormal reset signal generated by the WDT (watchdog timer) 703a. It is.

On the other hand, the payout control one-chip microcomputer 700 has a built-in CTC (Counter Timer Circuit) 704, as shown in FIG. It generates a signal. Note that this timer interrupt signal is output to an interrupt controller 705, which will be described later.

Further, as shown in FIG. 20, the payout control one-chip microcomputer 700 has a built-in interrupt controller 705, and receives a timer interrupt signal generated by the CTC 704, as well as an asynchronous serial communication circuit 706, which will be described later. It controls interrupt signals.

On the other hand, as shown in FIG. 20, the payout control one-chip microcomputer 700 has an asynchronous serial communication circuit 706 built therein, and serial communication is possible. This asynchronous serial communication circuit 706 has a built-in serial communication baud rate setting register SCBR shown in FIG. This is a register that can be set up to FFFh. The baud rate (bps) is calculated by internal clock (clock generated by clock circuit 702 shown in FIG. 20) frequency/(serial communication baud rate setting register SCBR×16). Specifically, for example, if the internal clock (the clock generated by the clock circuit 702 shown in FIG. 20) frequency is 15 MHz and the serial communication baud rate setting register SCBR is set to 0BCh (=188), the baud rate (bps ) is 15 (MHz)/(188×16)=4986.7 (bps). Although the baud rate setting explained for the one-chip microcomputer 600 is an example in which the reception baud rate and the transmission baud rate can be set separately, this baud rate is common for both transmission and reception. Furthermore, when 000h is set in the serial communication baud rate setting register SCBR, the calculation is performed assuming that 001h is set in the serial communication baud rate setting register SCBR.

Furthermore, the asynchronous serial communication circuit 706 has a built-in serial communication setting register SCFM shown in FIG. 21(b). This serial communication setting register SCFM consists of 8 bits, as shown in FIG. The second bit consists of a parity function setting register PEN that can set whether or not to use the parity function, the second bit consists of a data length setting register FMT that can set the data length, and the third bit sets the parity function. It consists of an operation mode setting register MOD that can set the mode, the 4th and 5th bits are unused, and the 6th bit consists of a reception function setting register REN that can set whether or not to use the reception function. The 7th bit consists of a transmission function setting register TEN that can set whether or not to use the transmission function.

As shown in FIG. 21(b), this parity type setting register PTP has an initial value of 0 and allows reading and writing of values. When 0 is set, even parity is set, and when 1 is set, odd parity is set. is set to Further, the parity function setting register PEN has an initial value of 1 and allows reading and writing of values, and when set to 0, parity is set to unused, and when set to 1, parity is set to be used.

On the other hand, as shown in FIG. 21(b), the data length setting register FMT has an initial value of 1, allowing reading and writing of values, and when set to 0, the start bit length of "L" level, 8 bit length. data, the communication format is such that the stop bit length of the "H" level is 1 frame (see Figures 18 (a) and (b)), and when 1 is set, the start bit length of the "L" level is 8 bits. The communication format is such that the length of the "H" level stop bit for two pulses is one frame (see timing T12 section in FIG. 18(c)). Note that when the parity function setting register PEN is set to 0, parity is set to unused, so parity is not added to the communication format as shown in FIGS. 18(a) and 18(c). When the setting register PEN is set to 1, it is set to use parity, so parity is added to the communication format as shown in FIG. 18(b). At this time, 0 is set in the parity type setting register PTP for even parity, and 1 is set for odd parity.

In addition, as shown in FIG. 21(b), the operation mode setting register MOD has an initial value of 0, and values can be read and written. When 0 is set, it becomes normal mode, and when 1 is set, it becomes FIFO mode. becomes. That is, it is possible to set whether or not to use the receiving register 706a and the transmitting register 706b built in the asynchronous serial communication circuit 706 shown in FIG. 20 as a FIFO. Therefore, when the operation mode setting register MOD is set to 0, the reception register 706a and the transmission register 706b are not used as FIFO, and when it is set to 1, the reception register 706a and the transmission register 706b are not used as FIFO. It will be used as.

On the other hand, as shown in FIG. 21(b), the reception function setting register REN has an initial value of 0, allowing reading and writing of values, and when set to 0, the reception function is disabled and set to When received, the reception function is enabled. Note that the moment the receiving function setting register REN is set to 0, the receiving function is set to be disabled.

In addition, as shown in FIG. 21(b), the transmission function setting register TEN has an initial value of 0, allowing reading and writing of values, and when set to 0, the transmission function is disabled, and when set to 1. When this happens, the send function is enabled. Note that when the transmission function setting register TEN is set to 0, if there is data in the middle of transmission, transmission is prohibited after transmission is completed.

On the other hand, the asynchronous serial communication circuit 706 includes a serial communication setting status register SCST shown in FIG. 22(a). As shown in FIG. 22(a), this serial communication setting status register SCST is read-only and consists of 8 bits, and the least significant bit (0th bit) is a parity error flag register indicating whether or not a parity error has been detected. The first bit consists of a framing error flag register FE that indicates whether or not a framing error has been detected, and the second bit consists of a break code detection flag register BRK that indicates whether or not a break code has been detected. The first bit consists of an overrun detection flag register ORE indicating whether overrun is detected, the fourth bit consists of a noise detection flag register NF indicating whether noise is detected, and the fifth bit consists of the above-mentioned receiving register 706a. (See Figure 20) consists of a receive data flag register RDRF that indicates whether data is stored in the register 706b (see Figure 20), and the 6th bit serially transmits the data stored in the transmission register 706b (see Figure 20). It consists of a transmission data empty flag register TDBE that indicates whether or not the relevant data has been transferred to the transmission shift register 706d (see FIG. 20) used when transmitting data. It consists of a transmission completion flag register TC that indicates whether the transmission is in progress or not.

As shown in FIG. 22(a), this parity error flag register PE stores, for example, when the asynchronous serial communication circuit 706 receives data, the parity data (see FIG. 18(b)) added to the data is If the parity is an even number, the asynchronous serial communication circuit 706 counts "1" in the 8-bit length data, and if it is an even number, that is, the parity bit is 0, there is no parity error, and the corresponding asynchronous serial communication circuit 706 writes "1" in the parity error flag register PE. 0" will be set. Furthermore, if the parity is an odd number, the asynchronous serial communication circuit 706 counts "1" in the 8-bit length data, and if it is an odd number, that is, the parity bit is 1, there is no parity error, so the parity error flag register PE will be set to "0". On the other hand, if the parity is set to even parity and the parity bit is 1 when the asynchronous serial communication circuit 706 counts "1" in the 8-bit data, it is a parity error and the parity error flag register PE is set. "1" will be set. Also, if the parity is set to odd parity and the parity bit is 0 when the asynchronous serial communication circuit 706 counts "1" in the 8-bit data, it is a parity error and the parity error flag register PE is set. "1" will be set. Note that when "1" is set in the parity error flag register PE, it is assumed that an error has occurred, and the asynchronous serial communication circuit 706 outputs an interrupt request signal to the interrupt controller 705 (see FIG. 20).

On the other hand, as shown in FIG. 22(a), the framing error flag register FE indicates that a framing error has occurred if the stop bit of the data is "L" when the asynchronous serial communication circuit 706 receives the data. If the stop bit is set to "1" in the asynchronous serial communication circuit 706, and the stop bit is "H", it is assumed that no framing error has occurred and "0" is set. Note that when "1" is set in the framing error flag register FE, it is assumed that an error has occurred, and the asynchronous serial communication circuit 706 outputs an interrupt request signal to the interrupt controller 705 (see FIG. 20).

In addition, as shown in FIG. 22(a), the break code detection flag register BRK is configured so that when data is received by the asynchronous serial communication circuit 706, the data is stored in one frame (timing T10 period in FIG. 18(a), ( (See the timing T11 interval in b) and the timing T12 interval in (c)) If the value is "0", it is assumed that a break code has been detected, and "1" is set in the asynchronous serial communication circuit 706, and the value is "0" for one frame or more. ”, “0” is set as no break code detected. Note that when "1" is set in the break code detection flag register BRK, it is assumed that an error has occurred, and the asynchronous serial communication circuit 706 outputs an interrupt request signal to the interrupt controller 705 (see FIG. 20).

On the other hand, as shown in FIG. 22(a), the overrun detection flag register ORE indicates that an overrun has occurred if the previously received data processing has not been completed when the asynchronous serial communication circuit 706 receives data. "1" is set in the asynchronous serial communication circuit 706 as "1", otherwise "0" is set. Note that when the overrun detection flag register ORE is set to "1", it is assumed that an error has occurred, and the asynchronous serial communication circuit 706 outputs an interrupt request signal to the interrupt controller 705 (see FIG. 20).

Further, as shown in FIG. 22(a), when noise is detected in the asynchronous serial communication circuit 706 when data is received, the noise detection flag register NF is set to "1" in the asynchronous serial communication circuit 706. If no noise is detected, "0" is set.

On the other hand, as shown in FIG. 22(a), the reception data flag register RDRF is a reception shift register 706c ( When data is transferred from the receiving register 706a (see FIG. 20), "1" is set, and in other cases, "0" is set. Note that when "1" is set in the receive data flag register RDRF, the asynchronous serial communication circuit 706 outputs an interrupt request signal to the interrupt controller 705 (see FIG. 20).

In addition, as shown in FIG. 22(a), the transmission data empty flag register TDBE is connected to the asynchronous serial communication circuit 706 used when serially transmitting the data stored in the transmission register 706b (see FIG. 20). When the data is transferred to the built-in transmission shift register 706d (see FIG. 20), "1" is set, and in other cases, "0" is set. Note that when "1" is set in the transmission data empty flag register TDBE, the asynchronous serial communication circuit 706 transmits an interrupt request signal to the interrupt controller 705 (see FIG. 20).

On the other hand, as shown in FIG. 22(a), the transmission completion flag register TC is set to "0" when data is being transmitted from the asynchronous serial communication circuit 706, and is set to "1" when data transmission is completed. be done.

On the other hand, the asynchronous serial communication circuit 706 further includes a serial communication data register SCDT shown in FIG. 22(b). This serial communication data register SCDT has an initial value of 00h, can read and write values, and can store data from 00h to FFh. This serial communication data register SCDT functions as reception data when read, and functions as transmission data when written.

In this way, the one-chip microcomputer 600 has the asynchronous serial communication circuit (CH0) 646 and the asynchronous serial communication circuit shown in FIG. (CH1) 647 is used to serially transmit predetermined data.

<Explanation on serial communication settings>
By the way, the one-chip microcomputer 600 performs the following settings when serially transmitting predetermined data to the payout/emission control board 70.

That is, when the inside of the one-chip microcomputer 600 is reset, the asynchronous serial communication circuit (CH0) 646, the asynchronous serial communication circuit (CH1) 647, and the synchronous serial communication circuit 648 built in the one-chip microcomputer 600 It is reset regardless of whether backup processing is performed or not. Therefore, the payout control command PAY_CMD is serially transmitted to the payout/launch control board 70 using the asynchronous serial communication circuit (CH0) 646, or the payout control command PAY_CMD is sent to the transmission buffer register TXBUF shown in FIG. 17(b). If the power is cut off (power outage) in the stored state, the asynchronous serial communication circuit (CH0) 646 will not perform backup processing, so the payout control command PAY_CMD that was stored (set) before the power outage is It will not be transmitted to the payout/launch control board 70. Therefore, the payout/launch control board 70 cannot receive the payout control command PAY_CMD, and there is a problem that the payout/launch control board 70 may not be able to properly receive the payout number data.

Therefore, in this embodiment, when performing serial communication using the asynchronous serial communication circuit (CH0) 646, the control of the gaming operation is performed after the transmission time during serial communication<the voltage abnormality signal ALARM becomes "L". The following processing is performed to ensure the time required until the voltage becomes unworkable.

That is, as shown in FIG. 23, when the power of AC 24V, which is an external power source supplied from a transformer (not shown) installed in the game parlor, is cut off (see timing T20), the voltage monitoring shown in FIG. 6 occurs. The unit 1310 outputs the "L" level voltage abnormality signal ALARM 20 to 30 ms after the power is cut off (see timing T20) (see timing T21). Then, 20 ms or more after timing T21 (see timing T22), either DC5V, which is the DC voltage generated by voltage generation section 1300 shown in FIG. 6, becomes 4.5V or less, or DC12V becomes 9.6V or less. becomes. As a result, the one-chip microcomputer 600 is not supplied with a voltage capable of controlling gaming operations, and therefore cannot control gaming operations.

Therefore, in this embodiment, the serial communication The baud rate setting of the transmission baud rate setting register TPR shown in FIG. 17(a) is set as follows so that the transmission time is short.

That is, the internal clock (clock generated by the clock generation circuit 640 shown in FIG. 15) frequency is 20 MHz, and the transmission baud rate setting register TPR shown in FIG. 17(a) is set to 01F4h (=500) in order to improve noise resistance. The baud rate is set low. At this time, the transmission baud rate (bps) is calculated as 20 (MHz)/(500×32), which is 1,250 (bps). This 1,250 (bps) means that 1250 bits can be transmitted per second, so 5 bits can be transmitted in 4 ms. Then, the payout control command PAY_CMD that is serially transmitted from the one-chip microcomputer 600 to the payout/launch control board 70 using the asynchronous serial communication circuit (CH0) 646 is 8 bits, and these 8 bits are: One bit is added as a start bit and one bit is added as a parity bit, resulting in a total of 10 bits being transmitted. Therefore, if 5 bits can be transmitted in 4 ms, the transmission will be completed in two timer interrupt processes (8 ms) in the timer interrupt process that is started every 4 ms in the main control, which will be described later. In this way, the transmission time during serial communication is shorter than the time from when the voltage abnormality signal ALARM becomes "L" until the voltage becomes such that control of gaming operations cannot be executed (see timing T21 to timing T22 shown in FIG. 23). It can be for a short period of time.

As described above, even if the baud rate setting is set low to improve noise resistance, the time from when the voltage abnormality signal ALARM becomes "L" to when the voltage reaches such a level that control of gaming operations cannot be executed (Fig. 23 The serial communication is completed at timing T21 to timing T22 shown in FIG. That is, since the payout/launch control board 70 executes a backup process like the program in the main control described later, the payout operation will be performed normally as long as the serial communication is completed. Therefore, even if a power failure occurs in a situation where prize ball information to be paid out remains on the main control side, the payout operation will be performed normally.

On the other hand, if the boat rate setting is set high to increase the amount of data to be transmitted, for example, if the internal clock (the clock generated by the clock generation circuit 640 shown in FIG. 15) frequency is 20 MHz, If 32h (=50) is set in the transmission baud rate setting register TPR shown in FIG. This 12,500 (bps) means that 12,500 bits can be transmitted in 1 second, which means that 12.5 bits can be transmitted in 1 ms. Then, the payout control command PAY_CMD that is serially transmitted from the one-chip microcomputer 600 to the payout/launch control board 70 using the asynchronous serial communication circuit (CH0) 646 is 8 bits, and these 8 bits are: One bit is added as a start bit and one bit is added as a parity bit, resulting in a total of 10 bits being transmitted. Therefore, if 12.5 bits can be transmitted in 1ms, the transmission will be completed in a shorter time than both the timer interrupt processing that starts every 4ms in the main control and the timer interrupt processing that starts every 1ms in the payout control. I will do it.

As described above, even if the boat rate setting is set high to increase the amount of data to be transmitted, the voltage becomes such that control of gaming operations cannot be executed after the voltage abnormality signal ALARM becomes "L". (See timing T21 to timing T22 shown in FIG. 23), the serial communication will have been completed, so if there is a power failure while the prize ball information to be paid out remains on the main control side, Even if this occurs, the payout operation will be performed normally.

Note that in this embodiment, the settings for the asynchronous serial communication circuit (CH0) 646 have been described, but similar settings are also applied to the asynchronous serial communication circuit (CH1) 647 that serially transmits predetermined data to the sub-control board 80. It is possible to

By the way, when the WDT 643 shown in FIG. 15 generates an abnormal reset signal, the inside of the one-chip microcomputer 600 is reset, so the asynchronous serial communication circuit (CH0) 646 and the asynchronous serial communication circuit (CH1) 647, the synchronous serial communication circuit 648 will also be reset. That is, the reset is performed regardless of whether or not there is transmission data in the asynchronous serial communication circuit (CH0) 646, the asynchronous serial communication circuit (CH1) 647, and the synchronous serial communication circuit 648. Thereby, the situation where abnormal data is transmitted can be reduced. That is, when an abnormal reset occurs, there is a risk that abnormal data may be stored in the asynchronous serial communication circuit (CH0) 646, the asynchronous serial communication circuit (CH1) 647, and the synchronous serial communication circuit 648. Therefore, regardless of whether there is transmission data in the asynchronous serial communication circuit (CH0) 646, the asynchronous serial communication circuit (CH1) 647, or the synchronous serial communication circuit 648, if you reset it, abnormal data will not be transmitted. It is possible to reduce the number of cases where the

On the other hand, in this embodiment, when the player's hand comes into contact with the touch sensor of the firing handle 16, the touch sensor outputs a detection signal to the payout and firing control board 70, as shown in FIG. In response to this, the payout/emission control board 70 will transmit the detection signal to the main control board 60 (main control CPU 600a). Then, the main control board 60 (main control CPU 600a) will transmit the detection signal to the sub control board 80 as the production control command DI_CMD. This makes it possible to transmit information as to whether or not the player touched the handle 16 to play the game to the sub-control board 80. As explained above, by doing this, even if the movable accessory device 43 is moved to the front of the liquid crystal display device 41 during the customer waiting demonstration, as shown in FIG. Also, when the sub-control board 80 receives information as to whether or not the player touched the handle 16 to play the game, the sub-control board 80 causes the game ball to enter the special symbol 1 starting port 44 (see FIG. 5). Even if not, the movable accessory device 43 is controlled to return to the origin position (original position) as shown in FIG. It becomes possible to perform control so that a normal screen displaying a variable display (see image P60A shown in FIG. 24(b)) is displayed. Note that it is not possible to directly transmit the detection signal from the touch sensor of the firing handle 16 to the sub-control board 80 due to game rules.

<Explanation of count-up performance>
Next, the count-up effect will be specifically explained with reference to FIGS. 25 to 31.

When displaying the number of balls won and the like due to a jackpot on the liquid crystal display device 41, a count-up effect of the numbers is performed. This count-up performance often involves a change from the previous number of pitches to a new number of pitches. Specifically, as shown in FIG. 25(a), the liquid crystal display device 41 displays ten thousand digits "0", thousands digit "1", hundreds digit "5", tens digit "3", When "01538" indicating the ones digit "8" is displayed, if a count-up effect such as +14 count-up shown in FIG. 25(b) occurs, from "01538" shown in FIG. 25(a), This will change to "01552" shown in FIG. 25(d). At this time, a change effect will be performed to change the number from "01538" shown in FIG. 25(a) to "01552" shown in FIG. 25(d). Changes need to be made smoothly. Therefore, conventionally, variable animation control is performed to change the ones digit from "8" to "2" and the tens digit from "3" to "5". Specifically, when changing the ones digit from "8" to "2", as shown in FIG. Prepare AS1 ("2" in the illustration) and numerical information on the previous number of pitches ZS1 ("8" in the illustration), which is a variation action scenario for the previous number of pitches, and use the numerical information ZS1 on the previous number of pitches. , a fluctuation animation is performed to change the numerical information of the number of balls to new AS1. Then, in changing the tens place from "3" to "5", as shown in FIG. Now, we will prepare the numerical information ZS2 (in the illustration, "3") of the previous number of pitches, which is the change action scenario of the previous number of pitches, and create a new number from the numerical information ZS2 of the previous number of pitches. A fluctuation animation is performed to change the numerical information of the number of pitches to AS2.

However, if we prepare two pieces of information, the numerical information ZS1 and ZS2 for the previous number of pitches and the numerical information AS1 and AS2 for the new number of pitches, and try to perform a fluctuating animation that matches them, the control burden increases. The problem was that it was growing. That is, when performing a fluctuating animation in which the ones digit changes from "8" to "2" and the tens digit changes from "3" to "5", the area displayed on the liquid crystal display device 41 is determined in advance. . Specifically, as shown in FIGS. 26(a) to 26(d), four scenes and objects L0 and L1 are prepared, numerical information ZS1 and ZS2 of the previous number of pitches is set in object L0, and New numerical information AS1, AS2 about the number of pitches is set in the object L1. In this way, a fluctuating animation is performed. That is, in the scene shown in FIG. 26A, the numerical information ZS1 and ZS2 of the previous number of pitches set in the object L0 is displayed in the center of the liquid crystal display device 41. Next, in the scene shown in FIG. 26(b), more than half of the upper half of the numerical information ZS1 and ZS2 of the previous number of pitches set in the object L0 is displayed on the lower side of the liquid crystal display device 41, and The lower half of the new number of pitches numerical information AS1, AS2 is displayed on the upper side of the liquid crystal display device 41. Next, in the scene shown in FIG. 26(c), the upper part of the numerical information ZS1 and ZS2 of the previous number of balls set in the object L0 is displayed slightly on the lower side of the liquid crystal display device 41, and the upper part of the numerical information ZS1 and ZS2 set in the object L0 is Numerical information AS1, AS2 about the new number of pitches is displayed on the upper side of the liquid crystal display device 41. Next, in the scene shown in FIG. 26(d), the new numerical information AS1, AS2 of the number of pitches set in the object L1 is displayed in the center of the liquid crystal display device 41.

In this way, the variation animation will be performed. However, when such control is performed, it is necessary to set the previous number of pitches numerical information ZS1, ZS2 and the new number of pitches numerical information AS1, AS2 in the objects L0, L1. This will increase the control burden.

Therefore, in this embodiment, the following processing is performed in order to solve the above problems. That is, as shown in FIG. 27(a), the liquid crystal display device 41 displays the tenth place "0", the thousands place "1", the hundreds place "5", the tens place "3", and the ones place " When "01538" indicating "8" is displayed, if a count-up effect such as +14 count-up shown in FIG. 27(b) occurs, from "01538" shown in FIG. 27(a) to FIG. 27(d). ) will change to "01552" shown in (). At this time, when changing the ones place from "8" to "2" and the tens place from "3" to "5", as shown in FIGS. 27(c-1) and (c-2), After displaying a common high-speed fluctuation animation KAI of the same size as the unchanging number on the liquid crystal display device 41, as shown in FIG. ), the tens digit is changed to "5" (new number of pitches numerical information AS2). In this way, it is possible to break the relationship between the previous number of balls and the new number of balls, and change the number without giving the player a sense of discomfort.

More specifically, as shown in FIGS. 28(a-1) to (a-4), four scenes and objects X1 to X3 and L1 are prepared. Then, the common high-speed fluctuation animation KAI shown in FIG. 28(b-1) is set in the scene shown in FIG. 28(a-1) by the VDP 803 (see FIG. 6). As a result, a common high-speed fluctuation animation KAI is displayed in the center of the liquid crystal display device 41.

Next, the common high-speed fluctuation animation KAIa shown in FIG. 28(b-2) is set in the scene shown in FIG. 28(a-2) by the VDP 803 (see FIG. 6). As a result, the common high-speed fluctuation animation KAIa is displayed in the center of the liquid crystal display device 41. Note that this common high-speed fluctuation animation KAIa is displayed more enlarged than the common high-speed fluctuation animation KAI shown in FIG. 28(b-1) (than the numbers that do not change).

Next, the common high-speed fluctuation animation KAI shown in FIG. 28(b-3) is set in the scene shown in FIG. 28(a-3) by the VDP 803 (see FIG. 6). As a result, a common high-speed fluctuation animation KAI is displayed in the center of the liquid crystal display device 41.

Next, the VDP 803 (see FIG. 6) sets new pitch count information AS1 shown in FIG. 28(b-4) in the scene shown in FIG. 28(a-4). As a result, new numerical information AS1 about the number of pitches is displayed in the center of the liquid crystal display device 41.

In this way, if you display a common high-speed fluctuation animation no matter what the previous pitch count number is, the scenario will be the common high-speed fluctuation animation KAI ⇒ enlarged display. It is sufficient to prepare only 10 scenarios of common high-speed fluctuation animation KAIa⇒common high-speed fluctuation animation KAI⇒new number of pitches numerical information “0” to “9”. Therefore, it is no longer necessary to prepare the numerical information ZS1 and ZS2 of the previous number of pitches as in the conventional case, thereby reducing the control burden. Furthermore, by displaying the common high-speed fluctuation animation KAI on the liquid crystal display device 41, it is possible for the player to see the update of the accumulated display count value in a natural expression.

In addition, in this embodiment, an example was shown in which the enlarged common high-speed fluctuation animation KAIa is displayed on the liquid crystal display device 41, but the invention is not limited to this, and only the common high-speed fluctuation animation KAI may be continued to be displayed. Also good. However, by displaying the common high-speed fluctuating animation KAIa that is enlarged, the display can be varied, thereby preventing a situation where the player's interest is diminished.

On the other hand, in this embodiment, after displaying the common high-speed fluctuation animation KAI, the numerical information of the new number of pitches is displayed, but the invention is not limited to this. 4) may be used. That is, when the common high-speed fluctuation animation KAI shown in FIG. 28 (b-1) is set by the VDP 803 (see FIG. 6) in the scene shown in FIG. 28 (c-1), the object located behind it The new number of pitches numerical information AS1 shown in FIG. 28(b-4) is set in L1. In other words, the common high-speed fluctuation animation KAI is displayed on the liquid crystal display device 41, superimposed on the new number of pitches numerical information AS1 shown in FIG. 28(b-4). In this way, the player can only see the common high-speed fluctuation animation KAI.

Then, in that state (with the new number of pitches numerical information AS1 set behind it), the VDP 803 (see FIG. 6) changes the scene shown in FIG. ) is set, and then the common high-speed fluctuation animation KAI shown in FIG. 28(b-3) is set in the scene shown in FIG. 28(c-3). After that, when the display of the high-speed fluctuation animation KAI is erased by the VDP 803 (see FIG. 6), as shown in FIG. 28 (b-4) set in the object L1, as shown in FIG. The new number of pitches numerical information AS1 will be displayed on the liquid crystal display device 41.

Even with this arrangement, it is no longer necessary to prepare the numerical information ZS1 and ZS2 of the previous number of pitches as in the conventional case, thereby reducing the control burden. Furthermore, by displaying the common high-speed fluctuation animation KAI on the liquid crystal display device 41, it is possible for the player to see the update of the accumulated display count value in a natural expression.

Incidentally, in the present embodiment, an example has been described from the time when the count-up effect such as +14 count-up shown in FIG. 27(b) occurs until the end. While the common high-speed fluctuation animation KAI shown in 2) is being displayed on the liquid crystal display device 41, a new count-up effect may occur. In such a case, as shown in FIG. 29, in a scenario where the new number of pitches numerical information becomes "2" (new number of pitches numerical information AS1), the common information shown in FIG. 29(a) After the high-speed fluctuation animation KAI is displayed on the liquid crystal display device 41, the enlarged common high-speed fluctuation animation KAI shown in FIG. 29(b) is displayed on the liquid crystal display device 41, and then in FIG. 29(b-1) The common high-speed fluctuation animation KAI shown in FIG.

However, a new count-up effect occurs, and the new number of pitches' numerical information is "2" (new number of pitches' numerical information AS1), and the new number of pitches' numerical information is "5" (new number of pitches). If the numerical information for the number of pitches becomes AS2), the new numerical information for the number of pitches becomes "2" (new numerical information for the number of pitches AS1) in a scenario where the new numerical information for the number of pitches becomes "2" (the new numerical information for the number of pitches AS1). 5" (new number of pitches numerical information AS2) is overwritten. Specifically, after the enlarged common high-speed fluctuation animation KAI shown in FIG. 29(b) is displayed on the liquid crystal display device 41, the common high-speed fluctuation animation KAI shown in FIG. 29(c) is displayed on the liquid crystal display device 41. will be displayed. After that, the enlarged common high-speed fluctuation animation KAIa shown in FIG. 29(d) is displayed on the liquid crystal display device 41, and the common high-speed fluctuation animation KAI shown in FIG. 29(e) is displayed on the liquid crystal display device 41. After that, new numerical information AS2 of the number of pitches shown in FIG. 29(f) will be displayed on the liquid crystal display device 41.

In this way, since the display time of the common high-speed fluctuation animation is only increased, a new count-up effect can be executed without giving the player a sense of discomfort. Furthermore, since the scenario is simply overwritten, the control method is also simplified.

On the other hand, in this embodiment, when a count-up effect such as +14 count-up shown in FIG. However, as shown in FIG. However, it may be possible to display a low-speed fluctuation animation that allows you to visually see that the number is increasing one by one. That is, as shown in FIG. 30(a), the liquid crystal display device 41 displays the tens digit "0", the thousands digit "1", the hundreds digit "0", the tens digit "1", and the ones digit "1". When "01018" indicating "8" is displayed, if a count-up effect such as +14 count-up shown in FIG. 30(b) occurs, the display changes from "01018" shown in FIG. 30(a) to FIG. ) will change to "01032" shown in (). At this time, when changing the tens place from "1" to "3", the VDP803 (see Figure 6) is used to change the tens place from "1" to "2" at a low speed, as shown in Figure 30 (c-2). The fluctuation animation is displayed on the liquid crystal display device 41, and then, as shown in FIG. 30(d-2), the changed number “2” is displayed on the liquid crystal display device 41. Thereafter, the VDP 803 (see FIG. 6) causes the liquid crystal display device 41 to display a low-speed fluctuation animation that changes from "2" to "3" as shown in FIG. 30(e-2). As shown in 2), the changed number "3" is displayed on the liquid crystal display device 41. On the other hand, when changing the ones digit from "8" to "2", the VDP 803 (see FIG. 6) performs the following steps until the tens digit changes to "3" as shown in FIG. 30 (f-2). The common high-speed fluctuation animation KAI is repeatedly displayed on the liquid crystal display device 41 as shown in FIGS. 30(c-1) to (f-1). Thereafter, as shown in FIG. 30(g), new numerical information on the number of pitches (in the figure, "2") is displayed on the liquid crystal display device 41.

By doing this, it is possible to display on the liquid crystal display device 41 a common high-speed fluctuation animation for the ones digit, and a low-speed fluctuation animation that increases by one for the tens digit. At this time, in order to display the common high-speed fluctuation animation KAI on the liquid crystal display device 41, as shown in FIGS. "2") may be superimposed behind the common high-speed fluctuation animation KAI. In addition, after displaying the common high-speed fluctuation animation KAI on the liquid crystal display device 41 repeatedly for a predetermined number of times or for a predetermined time until the tens digit changes to "3", a low speed variation animation KAI that changes the ones digit to "2" is displayed on the liquid crystal display device 41. A fluctuation animation may be performed to display new numerical information on the number of pitches ("2" in the figure) on the liquid crystal display device 41, as shown in FIG. 30(g).

On the other hand, in the present embodiment, an example of a count-up effect has been shown, but the invention is not limited thereto, and can also be applied to effects in which the count of a timer or the like is subtracted. That is, when performing an effect that subtracts the count of a timer or the like, a timer that displays up to the second decimal place is often used on the liquid crystal display device 41, as shown in FIG. 31(a). In this case, if the speed at which the count is subtracted and the numbers change is the same for all digits, it will give the player a sense of discomfort. Therefore, as shown in FIG. 31(a), the common high-speed fluctuation animation KAI is displayed on the liquid crystal display device 41 for the second decimal place where the change is large. Then, for the first decimal place where the change is small, a low-speed fluctuation animation is displayed on the liquid crystal display device 41 such that the player can visually see how the digits are subtracted one by one. Specifically, as shown in FIG. 31(b), a low-speed fluctuation animation in which the first decimal place digit subtracts one from "3" to "2" is displayed on the liquid crystal display device 41. In this way, changes in numbers can be shown to the player in an easy-to-understand manner, and the control burden can be reduced.

Note that the common high-speed fluctuation animation KAI explained in this embodiment does not need to be an animation using all numbers from 0 to 9, as it is only necessary for the player to understand the change, and for example, "1⇒ It is also possible to repeatedly display only specific numbers such as 8⇒4⇒9⇒5.

Further, in this embodiment, an example is shown in which the common high-speed fluctuation animation KAI is applied only to digits whose numbers change, but the invention is not limited thereto, and may be applied to digits whose numbers do not change.

<Explanation of background change effects>
Next, the background change effect will be specifically explained with reference to FIGS. 32 to 34.

Background changes (mode changes) are often made as a result of preview effects. If the background changes do not change at all, the player will feel the game is monotonous, while if the background changes frequently, the player may not be able to understand the nature of the game and may become confused. Furthermore, in cases where a reach effect occurs due to a change in the background, if the background information displayed after the reach effect is not properly managed, there is a possibility that the background before the background change will be displayed.

Therefore, in this embodiment, the following processing is performed in order to solve the above problems. That is, tables such as those shown in FIGS. 32(a) to (e) are used. This point will be explained in detail below.

The table HK_TBL shown in FIG. 32(a) is stored in the sub control ROM 800b (see FIG. 6), and stores the number of changes after the background change and the distribution table to be referred to.

To be more specific, the table HK_TBL shown in FIG. 32(a) is used as the reference distribution table for the variation of the special symbol after the background change and for the variation of the special symbol from the 1st to the 19th rotation. Table FR_TBL1 will be used. Then, in the variation of the special symbol from the 20th to the 39th rotation, the second distribution table FR_TBL2 is used as the distribution table to be referred to. Furthermore, in the variation of the special symbol from the 40th to the 59th rotation, the third distribution table FR_TBL3 will be used as the distribution table to be referred to. Furthermore, in the variation of the special symbol after the 60th rotation, the fourth distribution table FR_TBL4 will be used as the distribution table to be referred to.

By the way, the first distribution table FR_TBL1 referred to in the variation of special symbols in the 1st to 19th rotations is as shown in FIG. 32(b). Specifically, if the production control command DI_CMD, which is the lottery result of the special symbol sent from the main control board 60 (main control CPU 600a), is a normal variation (miss), the winning result will be won without any background change. There is. Then, if the production control command DI_CMD, which is the lottery result of the special symbol transmitted from the main control board 60 (main control CPU 600a), is a normal reach (miss), the winning is made without any background change. Furthermore, if the production control command DI_CMD, which is the lottery result of the special symbol transmitted from the main control board 60 (main control CPU 600a), is SP reach (miss), the winning result is made without any background change. Furthermore, if the performance control command DI_CMD, which is the special symbol lottery result transmitted from the main control board 60 (main control CPU 600a), is a normal reach (win), the winning will occur without any background change. Furthermore, if the performance control command DI_CMD, which is the lottery result of the special symbol transmitted from the main control board 60 (main control CPU 600a), is SP reach (win), the winning is made without any background change.

Thus, the first distribution table FR_TBL1 is a distribution table in which the distribution values for which background changes are executed are all "0" (the background changes are not won).

On the other hand, the second distribution table FR_TBL2 referred to in the variation of the special symbols from the 20th to the 39th rotation is as shown in FIG. 32(c). Specifically, if the production control command DI_CMD, which is the lottery result of the special symbol sent from the main control board 60 (main control CPU 600a), is a normal fluctuation (miss), the probability of spring, summer, and autumn is as shown in the figure. , winter, or no background change. If the performance control command DI_CMD, which is the lottery result of the special symbol sent from the main control board 60 (main control CPU 600a), is normal reach (miss), spring, summer, autumn, winter, background, etc. It is now possible to win one without any change. Furthermore, if the performance control command DI_CMD, which is the lottery result of the special symbol sent from the main control board 60 (main control CPU 600a), is SP reach (miss), the probability shown in the figure is spring, summer, autumn, winter, It is designed to win either without background change. Furthermore, if the performance control command DI_CMD, which is the lottery result of the special symbol sent from the main control board 60 (main control CPU 600a), is normal reach (win), the probabilities shown are spring, summer, autumn, winter, etc. It is designed to win either without background change. Furthermore, if the production control command DI_CMD, which is the lottery result of the special symbol sent from the main control board 60 (main control CPU 600a), is SP reach (win), spring, summer, autumn, winter with the probability shown in the figure. , with no background change.

Thus, the second distribution table FR_TBL2 is a distribution table in which it is difficult to win due to background changes, as shown in the illustrated probability.

On the other hand, the third distribution table FR_TBL3 referred to in the variation of the special symbols from the 40th to the 59th rotation is as shown in FIG. 32(d). Specifically, if the production control command DI_CMD, which is the lottery result of the special symbol sent from the main control board 60 (main control CPU 600a), is a normal fluctuation (miss), the probability of spring, summer, and autumn is as shown in the figure. , winter, or no background change. If the performance control command DI_CMD, which is the lottery result of the special symbol sent from the main control board 60 (main control CPU 600a), is normal reach (miss), spring, summer, autumn, winter, background, etc. It is now possible to win one without any change. Furthermore, if the performance control command DI_CMD, which is the lottery result of the special symbol sent from the main control board 60 (main control CPU 600a), is SP reach (miss), the probability shown in the figure is spring, summer, autumn, winter, It is designed to win either without background change. Furthermore, if the performance control command DI_CMD, which is the lottery result of the special symbol sent from the main control board 60 (main control CPU 600a), is normal reach (win), the probabilities shown are spring, summer, autumn, winter, etc. It is designed to win either without background change. Furthermore, if the production control command DI_CMD, which is the lottery result of the special symbol sent from the main control board 60 (main control CPU 600a), is SP reach (win), spring, summer, autumn, winter with the probability shown in the figure. , with no background change.

Thus, the third distribution table FR_TBL3 is a distribution table in which it is easy to win based on the background change, as shown in the illustrated probability.

On the other hand, the fourth distribution table FR_TBL4, which is referred to in the variation of special symbols from the 60th rotation, is as shown in FIG. 32(e). Specifically, if the production control command DI_CMD, which is the lottery result of the special symbol sent from the main control board 60 (main control CPU 600a), is a normal fluctuation (miss), the probability of spring, summer, and autumn is as shown in the figure. , it is set to be won sometime in winter. If the production control command DI_CMD, which is the lottery result of the special symbol sent from the main control board 60 (main control CPU 600a), is normal reach (miss), the probability shown in the figure is that it is spring, summer, autumn, or winter. It is now possible to win the election. Furthermore, if the performance control command DI_CMD, which is the lottery result of the special symbol sent from the main control board 60 (main control CPU 600a), is SP reach (miss), the probability shown in the illustration is that the performance control command DI_CMD is the lottery result of the special symbol. It looks like you'll be elected to something. Furthermore, if the production control command DI_CMD, which is the lottery result of the special symbol sent from the main control board 60 (main control CPU 600a), is normal reach (win), the probability shown in the figure is that of spring, summer, autumn, and winter. It looks like you'll be elected to something. Furthermore, if the production control command DI_CMD, which is the lottery result of the special symbol sent from the main control board 60 (main control CPU 600a), is SP reach (win), spring, summer, autumn, winter with the probability shown in the figure. It is possible to win one of the following.

Thus, the fourth distribution table FR_TBL4 is a distribution table whose distribution value is such that the background change is always executed (the background change is always won).

Therefore, if the first distribution table FR_TBL1, which is a distribution table in which the distribution values for which background changes are executed are all "0" (no background changes are won), and the lottery is performed, the control There is no need to perform controls such as not changing the background as a preview effect, thereby reducing the control burden. Furthermore, in the debugging work related to the background change lottery, which is a preview performance, it is only necessary to check the distribution table, so that the number of man-hours required for debugging can be reduced.

Although the present embodiment has been described using a background change as an example, the present invention is not limited to this and can be applied to any kind of preview presentation.

By the way, the columns (offset values) of the first distribution table FR_TBL1 to fourth distribution table FR_TBL4 shown in FIG. 32 are production control commands DI_CMD, which are the special symbol lottery results transmitted from the main control board 60 (main control CPU 600a). Based on. Based on this content, after a branching variation pattern lottery is performed on the sub-control board 80 side, the subsequent notice performance is performed using the variation pattern managed on the sub-control board 80 side as an offset value. will be exposed. This will be explained below using a specific example.

The sub-control variation pattern distribution table SUB_FR_TBL shown in FIG. 33(a) is stored in the sub-control ROM 800b (see FIG. 6), and is the lottery result of special symbols sent from the main control board 60 (main control CPU 600a). A production control command DI_CMD and a variation pattern on the sub-control side are stored.

To be more specific, if the performance control command DI_CMD, which is the special symbol lottery result sent from the main control board 60 (main control CPU 600a), is a normal variation (miss), the winning pattern is won without any change in the variation pattern. It looks like this. Then, when the performance control command DI_CMD, which is the lottery result of the special symbol sent from the main control board 60 (main control CPU 600a), is normal reach (miss), the fluctuation pattern is normal reach 1 (miss) with the probability shown. , Normal Reach 2 (missing). Furthermore, if the performance control command DI_CMD, which is the lottery result of the special symbol sent from the main control board 60 (main control CPU 600a), is SP reach (miss), the fluctuation pattern will be SP reach 1 (miss) with the probability shown. You can win either SP Reach 2 (lost) or SP Reach 2 (lost). Furthermore, if the performance control command DI_CMD, which is the lottery result of the special symbol sent from the main control board 60 (main control CPU 600a), is normal reach (win), the fluctuation pattern is normal reach 1 (win) with the probability shown. ), Normal Reach 2 (win). Furthermore, if the performance control command DI_CMD, which is the lottery result of the special symbol sent from the main control board 60 (main control CPU 600a), is SP reach (win), the fluctuation pattern is SP reach 1 with the probability shown. (Win) or SP Reach 2 (Win).

Thus, by using such a sub-control variation pattern distribution table SUB_FR_TBL, the variation pattern on the sub-control side is determined. The results become the columns (offset values) of the left symbol lottery distribution table HC_FR_TBL shown in FIG. 33(b) and the symbol change notice table ZH_TBL shown in FIG. 33(c). Specifically, in the left symbol lottery distribution table HC_FR_TBL shown in FIG. 33(b), in the case of a normal variation (missing) variation pattern, the left symbol displayed on the liquid crystal display device 41 is 1 to 8 with the probability shown in the figure. Win one of the following. In the case of the normal reach 1 (miss) variation pattern, the left symbol displayed on the liquid crystal display device 41 will win any one of 1 to 8 with the probability shown in the illustration, and in the case of the normal reach 2 (miss) variation pattern, the probability shown in the illustration The left symbol displayed on the liquid crystal display device 41 has a probability of winning one of 1 to 8. Furthermore, in the case of the SP reach 1 (miss) variation pattern, the left symbol displayed on the liquid crystal display device 41 will win any one of 1 to 8 with the probability shown in the figure, and in the case of the SP reach 2 (miss) variation pattern, The left symbol displayed on the liquid crystal display device 41 will win any one of 1 to 8 with the probability shown. Furthermore, in the case of the normal reach 1 (win) fluctuation pattern, the left symbol displayed on the liquid crystal display device 41 will win any one of 1 to 8 with the probability shown in the illustration, and in the case of the normal reach 2 (win) fluctuation pattern, the left symbol displayed on the liquid crystal display 41 will win as shown in the probability. The left symbol displayed on the liquid crystal display device 41 will win any one of 1 to 8 with a probability of . Furthermore, in the case of the SP reach 1 (win) fluctuation pattern, the left symbol displayed on the liquid crystal display device 41 will win any one of 1 to 8 with the probability shown in the figure, and in the case of the normal reach 2 (win) fluctuation pattern, The left symbol displayed on the liquid crystal display device 41 will win any one of 1 to 8 with the probability shown.

On the other hand, in the symbol change notice table ZH_TBL shown in FIG. 33(c), in the case of a normal variation (missing) variation pattern, the winning symbol does not change to another symbol. In the case of the normal reach 1 variation (missing) variation pattern, the probability shown is that the symbol will either not change to another symbol or it will change, and in the case of the normal reach 2 variation (missing) variation pattern, the probability shown will be different. The winner is whether the symbol does not change or changes. Furthermore, in the case of the SP reach 1 variation (missing) variation pattern, the probability shown is that the symbol will not change to another symbol or it will change, and in the case of the SP reach 2 variation (missing) variation pattern, the probability shown is as shown. , the winner is whether it does not change to another symbol or it changes. Furthermore, in the case of the normal reach 1 variation (win) variation pattern, the probability shown is that the symbol will not change to another symbol or the symbol will change, and in the case of the normal reach 2 variation (win) variation pattern, the probability shown is as shown. The winner is whether the symbol does not change to another symbol or it changes. Furthermore, in the case of the SP reach 1 variation (win) variation pattern, the probability shown is that the symbol will not change to another symbol or will change, and in the case of the SP reach 2 variation (win) variation pattern, the probability shown is as shown. Then, the winner is whether it doesn't change to a different pattern or it changes.

In this way, if a winning symbol changes to another symbol using the symbol change notice table ZH_TBL shown in FIG. 33(c), a lottery is conducted using the changed symbol lottery distribution table HZC_FR_TBL shown in FIG. 33(d). becomes. Note that the column pattern of this changing symbol lottery distribution table HZC_FR_TBL is a row (variation) that is won by lottery using the left symbol lottery distribution table HC_FR_TBL shown in FIG. 33(b).

Specifically, the changing symbol lottery distribution table HZC_FR_TBL shown in FIG. 33(d) selects "3" when the left symbol of "1" is won in the left symbol lottery distribution table HC_FR_TBL shown in FIG. 33(b). Either the symbol changes to the left symbol of , or the symbol changes to the left symbol of "7" to win. Then, when the left symbol of "2" is won in the left symbol lottery distribution table HC_FR_TBL shown in FIG. 33(b), whether it changes to the left symbol of "1" or the left symbol of "3", Either the left symbol of ``5'' or the left symbol of ``7'' will win. Furthermore, when the left symbol of "3" is won in the left symbol lottery distribution table HC_FR_TBL shown in FIG. 33(b), it is won without any change. Furthermore, when the left symbol of "4" is won in the left symbol lottery distribution table HC_FR_TBL shown in FIG. 33(b), does it change to the left symbol of "1" or the left symbol of "3"? , either the symbol changes to the left symbol of "5" or the left symbol of "7" wins. Furthermore, when the left symbol of "5" is won in the left symbol lottery distribution table HC_FR_TBL shown in FIG. 33(b), does it change to the left symbol of "1" or to the left symbol of "3"? , either the symbol changes to the left symbol of "5" or the left symbol of "7" wins. Furthermore, when the left symbol of "6" is won in the left symbol lottery distribution table HC_FR_TBL shown in FIG. 33(b), does it change to the left symbol of "1" or to the left symbol of "3"? , either the symbol changes to the left symbol of "5" or the left symbol of "7" wins. Furthermore, when the left symbol "7" is won in the left symbol lottery distribution table HC_FR_TBL shown in FIG. 33(b), it is won without any change. Furthermore, when the left symbol of "8" is won in the left symbol lottery distribution table HC_FR_TBL shown in FIG. 33(b), does it change to the left symbol of "1" or to the left symbol of "3"? , either the symbol changes to the left symbol of "5" or the left symbol of "7" wins.

In this way, a preview effect is performed using a table as shown in FIG. 33.

Thus, the determined fluctuation pattern is set as an offset value, and the left symbol lottery distribution table HC_FR_TBL shown in FIG. 33(b) and the symbol change notice table ZH_TBL shown in FIG. 33(c) are created based on the offset value. By performing a lottery using , it is possible to select a table according to the offset value, thereby reducing the control burden.

Furthermore, by conducting a lottery in the variation symbol lottery distribution table HZC_FR_TBL shown in FIG. 33(d) using the rows (variations) won by lottery using the left symbol lottery distribution table HC_FR_TBL shown in FIG. 33(b). , it is possible to select a table according to the row (variation), thereby reducing the control burden.

By the way, when changing the background (mode change) as described above, we tried to manage the data that manages the background information (for example, spring: 0, summer: 1, autumn: 2, winter: 3) with one background data. In this case, if you win a background change lottery using the table shown in Figure 32 and rewrite the background data when the background changes, there is a problem that the background will suddenly change when the decorative pattern starts changing. Ta. In particular, it was necessary to be careful when changing the background, which takes time, such as when the shutter closes and then opens when the background changes. This point will be specifically explained using screen examples shown in FIGS. 34(a-1) to 34(a-5). The screen examples shown in FIGS. 34(a-1) to 34(a-5) are conventional screen examples in which the background changes from spring to summer. That is, as shown in FIG. 34(a-1), the liquid crystal display device 41 displays a stopped decorative pattern (see image P100) in the center of the screen, and the number of balls pending starting (image P100) is displayed in the lower left corner of the screen. (see image P101) is displayed, a resident symbol (see image P102) is displayed in the lower right corner of the screen, and the background is a spring screen. In addition, this resident pattern is a reduced number shown by the decorative pattern that is variably displayed, and is, in principle, variably displayed in synchronization with the decorative pattern.

Next, as shown in FIG. 34(a-2), the decorative pattern changes (see image P103), an effect such as a scene change occurs due to reach, etc., and the left shutter located on the left side of the screen (see image P106a) Assume that an effect occurs in which the screen closes with the right shutter located on the right side of the screen (see image P106b). At this time, originally, the left shutter (image P106a) should have a decorative pattern corresponding to the spring background (see image P100), a background as it is in spring, and a number of starting pending pitches (see image P101) corresponding to the spring background. (see image P106b) and a screen hidden by the right shutter (see image P106b) is displayed on the liquid crystal display device 41. However, when managing with one background data, the spring background changes to the summer background, as shown in Figure 34 (a-2), and a decorative pattern corresponding to the summer background (see image P103) The number of pending pitches to start (see image P104) according to the background of the game is displayed on the liquid crystal display device 41 to such an extent that the player can visually check it through the gap between the left shutter (see image P106a) and the right shutter (see image P106b). I end up. Note that the resident symbol (see image P102) is displayed on the liquid crystal display device 41 without being hidden by the left shutter (see image P106a) and the right shutter (see image P106b).

Next, from the state shown in FIG. 34(a-2), as shown in FIG. 34(a-3), except for the resident symbols (see image P102), the left shutter (see image P106a) and the right shutter (see image P106b) ) is displayed on the liquid crystal display device 41.

Next, as shown in FIG. 34(a-4), the left shutter (see image P106a) and the right shutter (see image P106b) are opened, and from the gap between the left shutter (see image P106a) and the right shutter (see image P106b) , a summer background, a decorative pattern corresponding to the summer background (see image P103), and the number of starting pending pitches corresponding to the summer background (see image P104) are displayed on the liquid crystal display device 41. As shown in FIG. 34(a-5), the left shutter (see image P106a) and right shutter (see image P106b) are not displayed on the liquid crystal display device 41, and the summer background and the summer background are not displayed. The corresponding decorative pattern (see image P103), the number of starting pending balls corresponding to the summer background (see image P104), and the resident pattern (see image P102) will be displayed on the liquid crystal display device 41.

However, originally, only in the case shown in FIG. 34(a-4) would a summer background, a decorative pattern corresponding to the summer background (see image P103), and a starting holding ball corresponding to the summer background be displayed. The number (see image P104) is displayed on the liquid crystal display device 41, but when managed with one background data, the left shutter (see image P106a) and right shutter are displayed as shown in FIG. 34 (a-2). (See image P106b), the liquid crystal display device 41 displays a summer background, a decorative pattern corresponding to the summer background (see image P103), and the number of starting pending pitches corresponding to the summer background (see image P104). could have been displayed. Therefore, there was a problem of inappropriate background display.

Therefore, in this embodiment, the following processing is performed in order to solve the above problems. That is, two sets of first background data (current background) and second background data (background after change) are prepared, and the sub-control CPU 800a transfers the data at an appropriate timing. This point will be specifically explained using screen examples shown in FIGS. 34(b-1) to 34(b-5). If the background change lottery is won using the table shown in FIG. 32 and the background changes from spring to summer, the sub-control CPU 800a sets the first background data to 0 (=spring), and the second Set the background data to 1 (=summer). At this time, since the first background data is data indicating the current background, the VDP 803 (see FIG. 6) displays the data on the liquid crystal display device 41 as shown in FIG. 34(b-1) based on this data. Display the spring screen as the background. At this time, a decorative pattern (see image P100) corresponding to the spring background is displayed in the center of the screen of the liquid crystal display device 41, and the number of starting pending pitches (see image P101) corresponding to the spring background is displayed in the lower left corner of the screen. A resident symbol (see image P102) is displayed in the lower right corner of the screen.

Next, since the first background data remains set to 0 (=spring), the VDP 803 (see FIG. 6) displays the background on the liquid crystal display device 41 as shown in FIG. 34(b-2). An image in which the left shutter (see image P106a) and right shutter (see image P106b) are closed is displayed while the spring screen is displayed. As a result, as shown in FIG. 34(b-3), the screen where the non-resident symbols (see image P102) are hidden by the left shutter (see image P106a) and the right shutter (see image P106b) is displayed on the liquid crystal display device 41. Is displayed. At this time, the sub-control CPU 800a sets 1 (=summer) set in the second background data to the first background data. As a result, 1 (=summer) is set in the first background data.

Next, since the first background data is set to 1 (=summer), the VDP 803 (see FIG. 6) is set to the left shutter (see image P106a) and the right shutter, as shown in FIG. 34 (b-4). When the shutter (see image P106b) is opened, a summer screen is displayed as the background. At this time, the liquid crystal display device 41 displays the number of balls on hold for starting depending on the summer background (see image P104) and the decorative pattern (see image P103) corresponding to the summer background.

Next, since the first background data remains set to 1 (=summer), the VDP 803 (see FIG. 6) displays the background on the liquid crystal display device 41 as shown in FIG. 34 (b-5). While the summer screen is displayed, the left shutter (see image P106a) and right shutter (see image P106b) are not displayed, and the summer screen is displayed as the background. At this time, the liquid crystal display device 41 displays the number of starting pending balls corresponding to the summer background (see image P104), the decorative pattern corresponding to the summer background (see image P103), and the resident pattern (see image P102). Is displayed.

In this way, data can be transferred at an appropriate timing, so that an appropriate background display can be performed. Furthermore, background control processing can also be simplified.

In addition, in this embodiment, when closing the left shutter (see image P106a) and right shutter (see image P106b), the number of pitches pending at start (see image P101) corresponding to the spring background is hidden, and the left shutter (see image P106a) is closed. ) and the right shutter (see image P106b), the number of pending pitches to start (see image P104) corresponding to the summer background is displayed, so the player is made aware that the background has changed. It can be made easier.

In addition, in this embodiment, the number of starting pending balls is displayed on the liquid crystal display device 41 according to the background, but the display is not limited thereto, and the display of the starting pending ball number can be made common for each background. At this time, as shown in FIGS. 34(c-2) to (c-4), the number of pending pitches at start (see image P110) is hidden using the left shutter (see image P106a) and right shutter (see image P106b). Make sure not to. That is, as shown in FIGS. 34(c-1) to (c-5), the number of pending balls at start (see image P110) remains displayed on the liquid crystal display device 41. In this way, it becomes possible to execute a pre-read suspension change notice for the winning starting suspension ball without affecting the background transition situation.

<Explanation of production control commands in rescue games and games with special electric support symbols>
Next, the effect control commands in the rescue game and the special electric support symbol game will be explained.

As explained above, in the relief game, as shown in FIG. 9(b), the number of time savings in the second time saving game state (state with low electricity support) exceeds 100, and in the game with the special electricity support symbol, As shown in FIG. 9(c), the number of time savings in the second time saving game state (state with low electricity support) has become possible to exceed 100 times.

On the other hand, in the conventional game, as shown in FIG. 9(a), the number of times of time saving in the time saving game state (state with low electricity support) is up to 100 times. Therefore, the effect control command DI_CMD sent from the main control board 60 (main control CPU 600a) to the sub control board 80 (sub control CPU 800a) should be one command (2 bytes). That is, as a command mechanism, the production control command DI_CMD is composed of two bytes: an upper byte and a lower byte. The upper byte consists of 80H to FFH where the 7th bit (most significant bit) is 1, and the lower byte consists of 01H to 7FH where the 7th bit (most significant bit) is 0. Thereby, by the sub-control CPU 800a determining whether the 7th bit is 1 or 0, the sub-control CPU 800a can determine whether the production control command DI_CMD is the upper byte or the lower byte. Therefore, when the sub-control CPU 800a receives the production control command DI_CMD, if the command is missing or abnormal due to noise etc., it can detect that the combination of the upper and lower bytes is not correct, Therefore, by controlling abnormal commands, it is possible to prevent problems from occurring.

Therefore, if the number of time saving times is 100, the production control command DI_CMD could be expressed by 8001H to 64H with one command. That is, the upper byte 80H is a type indicating that the transmission content is the number of time reductions, and the lower byte indicates the number of time reductions from 1 (01H) to 100 (64H).

However, in games with special electric support symbols, it is now possible to save more than 100 times, so for example, in the case of 1000 times, the number that can be expressed in the lower byte of one command is as explained above. In order to prevent any malfunction from occurring, it is necessary to set the 7th bit (most significant bit) of the lower byte to 0, so the number ranges from 01H to 7FH (1 time to 127 times). Therefore, since the number of digits increases beyond this point, it is necessary to use two commands.

By the way, in the case of two commands, if you want to send the command 1000 times, you can think of a method of dividing 1000=03E8H expressed in hexadecimal into an upper byte and a lower byte and transmitting them as 2 commands as 8003H and 81E8H, respectively. Note that 80xxH is a type command indicating that the transmission content is the upper byte of the time saving number, and 81xxH is a type command indicating that the transmission content is the lower byte of the time saving number.

However, in 81E8H, the 7th bit (most significant bit) of the lower byte is 1, so it is impossible to control abnormal commands and prevent problems from occurring. Therefore, it is possible to divide 1000 = "00111" and "1101000" expressed in binary into 7 bits so that the 7th bit (most significant bit) of the lower byte becomes 0. However, in this case, the main control CPU 600a performs division processing, and the sub-control CPU 800a performs recombination processing, which poses a problem in that a control burden is imposed.

Therefore, in this embodiment, the way of holding data when making two commands is that the lower byte of the first command is a decimal thousands and hundreds place (00 to 99), and the lower byte of the second command is a decimal number. The main control CPU 600a generates an effect control command DI_CMD that is the tens and ones digits (00 to 99), and sends it to the sub-control board 80 (sub-control CPU 800a). The sub-control CPU 800a that receives the command multiplies the numerical value of the lower byte of the first command by 100, and adds the numerical value of the lower byte of the second command thereto. As a result, it is possible to receive the number data consisting of the original 2-byte data. In addition, when the received sub-control CPU 800a uses the VDP 803 to display numbers on the liquid crystal display device 41, the number of the first command is set to the thousands and hundreds digits, and the number of the second command is set to the digits of tens and ones. It will be better if you just display it as a digit.

By doing this, it is possible to not only make the command structure easier to understand, but also to reduce the control burden.

To explain in more detail using a specific example, if the number of time saving times is 1000, it can be divided into "10" and "00", and the first command can be expressed as 800BH and the second command as 8101H. Note that 0BH = 11, 01H = 01, which is different from "10" and "00", but this may cause a problem if the data is all 0 bytes, so the command adds 1 to the actual value. It is expressed as 01H to 64H.

Thus, the sub-control CPU 800a that receives such a command subtracts 1 from 0BH of the lower byte of the first command, making it 10, and subtracts 1 from 01H of the lower byte of the second command, making it 00. Then, the sub control CPU 800a adds the first command: 10×100+second command: 00, the value obtained by subtracting 1 from the lower byte of the first command, multiplied by 100, and the value obtained by subtracting 1 from the lower byte of the second command. This allows the sub-control CPU 800a to receive the content indicating the number of time reductions of 1000 times. In addition, when displaying numbers on the liquid crystal display device 41 using the VDP803, the number obtained by subtracting 1 from the lower byte of the first command is used as the number in the thousands and hundreds, and the value obtained by subtracting 1 from the lower byte of the second command is used. It will be displayed as numbers in the tens and ones place.

Further details of the above processing method will be described later.

By the way, in the present embodiment, the explanation is given using the number of times of time saving as an example, but the present invention is not limited to this, and the variation of the special symbol is executed a predetermined number of times (for example, 1000 times) in the rescue game shown in FIG. 9(b), It is also used for the performance control command DI_CMD when counting the number of changes in the special symbol until the transition to the 2-hour saving game state (state with low power support) and transmitting it to the sub-control CPU 800a.

<Main control: Program description>
Here, the outline of the program stored in the main control ROM 600b (see FIG. 6) processed by the main control board 60 will be explained in more detail by referring to FIGS. 35 to 55. do.

<Main control: Description of main processing>
First, when the power is turned on to the pachinko gaming machine 1, a power-on signal is sent to each control board to indicate that the DC voltage generated by the voltage generation section 1300 of the power supply board 130 (see FIG. 6) has been turned on. In response to the signal, the main control CPU 600a (see FIG. 6) reads the program stored in the main control ROM 600b (see FIG. 6), and performs the main control main processing shown in FIG. At this time, the main control CPU 600a first sets itself to an interrupt disabled state (step S1).

Next, the main control CPU 600a performs stack pointer setting processing to set the value of the stack pointer inside the main control CPU 600a in correspondence with the final address of the normal stack area (step S2).

Next, the main control CPU 600a clears the WDT 643 shown in FIG. 15 (step S3), and clears the output port that outputs the firing control signal (step S4).

Next, the main control CPU 600a sets the startup waiting time of the sub-control board 80 (step S5), decrements (-1) the set waiting time (step S6), and clears the WDT 643 shown in FIG. 15 (step S5). S7).

Next, the main control CPU 600a checks whether the set waiting time has become "0" (step S8), and if it has not become "0" (step S8:≠0), returns to the process of step S7. , is "0" (step S8:=0), the process advances to step S9.

Next, the main control CPU 600a acquires the voltage abnormality signal ALARM (see FIG. 6) outputted from the power supply board 130 (voltage monitoring unit 1310) (see FIG. 6) twice, and uses the voltage abnormality signal ALARM acquired twice. After confirming whether the levels match, the voltage abnormality signal ALARM is stored in an internal register of the main control CPU 600a (not shown), and the level of the voltage abnormality signal ALARM is confirmed (step S9). If the voltage abnormality signal ALARM is at the "L" level (step S10: YES), the process returns to step S9, and if the voltage abnormality signal ALARM is at the "H" level (step S10: NO), The process advances to step S11. That is, the main control CPU 600a repeats the same process until the voltage abnormality signal ALARM changes to a normal level (ie, "H" level) (steps S9 to S10). In this way, by acquiring the voltage abnormality signal ALARM twice, an accurate signal can be read.

Next, the main control CPU 600a permits data writing to the main control RAM 600c (step S11), and initializes the work area of the main control RAM 600c (step S12). Specifically, the power supply abnormality confirmation counter is set to 00H, and the system operation status is set to 01H. Then, the main control CPU 600a sets data in the reception baud rate setting register RPR (see FIG. 16(a)) to set the reception baud rate (bps), and also sets the reception baud rate (bps) in the parity presence/absence setting register RPEN (see FIG. 16(a)). Set the data, set whether parity is present or not, and if parity is set, set data in the parity odd-even setting register REVEN (see Figure 16(a)), and set whether parity is even or odd. I do. In addition, data is set in the transmission baud rate setting register TPR (see FIG. 17(a)) to set the transmission baud rate (bps), and data is set in the parity presence/absence setting register TPEN (see FIG. 17(a)). Settings are made as to whether parity is present or not, and when parity is set, data is set in the parity odd-even setting register TEVEN (see FIG. 17(a)), and even parity or odd parity is set. Furthermore, the main control CPU 600a sets the frequency division ratio of the synchronous clock in the synchronous clock frequency division ratio setting register CLK (see FIG. 19(a)), and sets the frequency division ratio of the synchronous clock in the data length setting register LENG (see FIG. 19(a)). , set the data length.

Thus, by making such settings, the one-chip microcomputer 600 serially transmits predetermined data to the payout/emission control board 70 using the asynchronous serial communication circuit (CH0) 646 shown in FIG. It becomes possible to transmit predetermined data to the sub control board 80 by serial transmission using the asynchronous serial communication circuit (CH1) 647.

According to the present embodiment, when setting the reception baud rate and transmission baud rate (bps), the main control CPU 600a (see FIG. 6) performs initial settings based on the power being turned on to the pachinko gaming machine 1, or The reception baud rate and transmission baud rate (bps) are set without determining whether the initial settings are due to the internal reset of the one-chip microcomputer 600 caused by an abnormal reset signal. Thereby, the situation where abnormal data is transmitted can be reduced. That is, when an abnormal reset occurs, there is a risk that abnormal data may be stored in the asynchronous serial communication circuit (CH0) 646 and the asynchronous serial communication circuit (CH1) 647. Therefore, it is possible to determine whether the initial settings are due to the power being turned on to the asynchronous serial communication circuit (CH0) 646 and the pachinko gaming machine 1, or the initial settings are due to the internal reset of the one-chip microcomputer 600 due to an abnormal reset signal. By setting the baud rate without making a judgment, it is possible to reduce the possibility of sending abnormal data.

Further, the main control CPU 600a performs a process of setting initial values in the transmission buffer register TXBUF (see FIG. 17(b)) and the transmission data register TRBUF (see FIG. 19(b)) in step S12. In this way, it is possible to reduce the situation in which abnormal data is transmitted due to the influence of noise or the like immediately after serial communication is started. That is, when the power is turned on to the pachinko gaming machine 1, the transmission buffer register TXBUF (see FIG. 17(b)) and the transmission buffer register TXBUF (see FIG. 17(b)) are The trust data register TRBUF (see Figure 19(b)) will be initialized, but by explicitly initializing it again in the program, it is possible to prevent abnormalities from occurring due to the influence of noise etc. immediately after serial communication starts. It is possible to reduce situations in which undesirable data is transmitted.

Next, the main control CPU 600a transmits a processing command (performance control command DI_CMD) for displaying a standby screen on the liquid crystal display device 41 to the sub-control board 80 (step S13).

Next, the main control CPU 600a clears the WDT 643 shown in FIG. 15 (step S14), and checks whether a signal indicating that the power has been turned on (power-on signal) has come from the payout control board 70 (step S15). . If the power-on signal has not come (step S15: OFF), the process returns to step S14, and if the power-on signal has come (step S15: ON), the process advances to step S16.

Next, the main control CPU 600a acquires the level data of the RAM clear switch 620 and the setting key switch 630, and saves it to the work area of the normal RAM area 600ca (see FIG. 7(a)) of the main control RAM 600c (step S16). .

Next, as shown in FIG. 2, the main control CPU 600a sends a door open signal indicating whether the upper opening/closing door 7 and the lower opening door 8 are opened, and a RAM clear switch evacuated to the work area of the main control RAM 600c. 620 and the setting key switch 630 are acquired (step S17), and it is confirmed whether they are all turned on (step S18). If all are turned on (step S18: YES), the main control CPU 600a performs a setting switching process (step S19).

<Main control: Main processing: Explanation regarding setting switching processing>
Here, this setting switching process will be specifically explained with reference to FIG. 37.

First, the main control CPU 600a transmits a setting switching start command (production control command DI_CMD) indicating that the setting is being changed to the sub-control board 80 (step S50).

Next, the main control CPU 600a clears the backup flag (step S51). Note that this backup flag is data indicating whether or not backup processing has been executed when a voltage drop due to a power outage or the like is detected in the power supply abnormality check processing shown in FIG. 38. Moreover, this backup flag is cleared in order to detect in step S21 shown in FIG. 36, which will be described later, a case where the main control RAM 600c is not backed up normally due to a power outage due to some reason during the setting switching process. It is.

Next, the main control CPU 600a sets the system operation status to 02H (step S52), and sets the probability setting value for generating a special gaming state advantageous to the player stored in the main control RAM 600c (see FIG. 6). It is acquired and set in the W register (step S53). To explain specifically, if the set value is, for example, "1" to "6", the set value "1" to "6" will correspond to the value "00H" to "05H" on the program, It will be set in the W register.

Next, the main control CPU 600a compares the value set in the W register with the set maximum value of the probability of generating a special gaming state advantageous to the player (for example, "05H" corresponding to "6") (step S54). . Then, if the value set in the W register is larger than the set maximum value of the probability of generating a special gaming state advantageous to the player (for example, "05H" corresponding to "6"), the main control CPU 600a (step S55 :YES), it is determined that it is an abnormal value, and 00H is set in the W register (step S56).

On the other hand, if the value set in the W register is smaller than the set maximum value of the probability of generating a special gaming state advantageous to the player (for example, "05H" corresponding to "6") (step S55: NO), it is a normal value. It is determined that this is the case, and the process proceeds to step S57.

Next, the main control CPU 600a sets to ON a security signal output to a hall computer (not shown) used for managing the game island of the game hall via an external terminal (not shown), and outputs the security signal as shown in the figure. The signal is output to the hall computer (not shown) via an external terminal (step S57).

Next, the main control CPU 600a sets 00H to the LED common port (step S58).

Next, the main control CPU 600a outputs the value set in the W register to the LED data port (step S59).

Next, the main control CPU 600a sets the LED common port that displays the set value to ON (step S60).

Next, the main control CPU 600a sets a predetermined value in a register in the main control CPU 600a so that a wait of 4 ms is applied, and performs a countdown process (step S61). Note that this process is performed by waiting at least 4 ms after the previous acquisition of the switch level when checking changes in the level data of the RAM clear switch 620 (see Figure 6) and the setting key switch 630 (see Figure 6). This is a process to confirm that the change in level data is not due to irregularities such as noise. Furthermore, when checking the change in the voltage abnormality signal in the subsequent power abnormality check process and counting the power abnormality confirmation counter, by waiting 4 ms, the "L" level of the voltage abnormality signal becomes noise. This is also a process to confirm that the level data is not due to irregularities such as.

Next, the main control CPU 600a performs a power supply abnormality check process (step S62). This power supply abnormality check process will be specifically explained with reference to FIG. 38.

<Main control: Main processing: Explanation regarding power supply abnormality check processing>
As shown in FIG. 38, the main control CPU 600a acquires the voltage abnormality signal ALARM (see FIG. 6) outputted from the power supply board 130 (voltage monitoring unit 1310) (see FIG. 6) twice (step S80), It is checked whether the levels of the voltage abnormality signal ALARM obtained twice match (step S81). If they match (step S81: YES), the main control CPU 600a checks the level of the voltage abnormality signal ALARM (step S82), and if they do not match (step S81: NO), the process returns to step S80.

Next, if the voltage abnormality signal ALARM is at the "H" level (step S82: OFF), the main control CPU 600a clears the power abnormality confirmation counter (step S83), and ends the power abnormality check process.

On the other hand, if the level of the voltage abnormality signal ALARM is "L" level (step S82: ON), the main control CPU 600a increments (+1) the power abnormality confirmation counter (step S84), and sets the value of the power abnormality confirmation counter. Confirm (step S85). If the value of the power abnormality confirmation counter is not 2 or more (step S85: NO), the power abnormality check process ends.

On the other hand, if the value of the power abnormality confirmation counter is 2 or more (step S85: YES), the main control CPU 600a transmits a power cut command (effect control command DI_CMD) indicating that the power has been cut off to the sub control board 80. (Step S86).

Next, the main control CPU 600a checks the value of the system operation status (step S87). If the value of the system operation status is 02H, it is determined that the setting change process is in progress (step S87: YES), and the process proceeds to step S89 without setting the backup flag to ON. In this way, it is possible to detect in step S21 shown in FIG. 36, which will be described later, a case where the main control RAM 600c is not backed up normally due to power cut-off for some reason during the setting switching process.

On the other hand, if the value of the system operation status is not 02H, it is determined that the setting change process is not in progress (step S87: NO), and the backup flag is set to ON (step S88).

Next, the main control CPU 600a disables data writing to the main control RAM 600c (step S89), and clears the output data of all output ports (step S90). Then, timer interrupts are prohibited (step S91), and infinite loop processing is repeated to wait for the voltage to drop.

<Main control: Main processing: Explanation regarding setting switching processing>
Thus, after completing the power abnormality check process (step S62) through the above-described processes, the main control CPU 600a calculates the following from the previous and current level data of the RAM clear switch 620 and level data of the setting key switch 630. Switch edge data of the RAM clear switch 620 signal and switch edge data of the setting key switch 630 signal are created (step S63). Note that the main control CPU 600a stores the created edge data in the main control RAM 600c.

Next, the main control CPU 600a checks the edge data stored in the main control RAM 600c, and if the setting key switch 630 is ON (step S64: NO), the process proceeds to step S65, and the setting key switch 630 is turned OFF. If so (step S64: YES), the process advances to step S67.

Next, if the RAM clear switch 620 is ON (step S65: NO), the main control CPU 600a increments (+1) the value of the W register (step S66), and returns to the process of step S54.

On the other hand, if the RAM clear switch 620 is OFF (step S65: NO), the process returns to step S57.

In this way, the above process is repeated until the setting key switch 630 is turned off. When the setting key switch 630 is turned off, the main control CPU 600a stores the value of the W register in the main control RAM 600c (see FIG. 6). (step S67).

Next, the main control CPU 600a outputs a setting confirmation display to the LED data port (step S68).

Next, the main control CPU 600a transmits a setting switching end command (production control command DI_CMD) reflecting the setting value to the sub-control board 80 (step S69).

<Main control: Description of main processing>
Thus, after completing the setting switching process (step S19) shown in FIG. 35 through the above-described process, the main control CPU 600a proceeds to the process of step S26 shown in FIG. 36.

On the other hand, the main control CPU 600a checks whether the signals of the RAM clear switch 620 and the setting key switch 630 are all turned on (step S18), and if they are not all turned on (step S18). :NO), the main control CPU 600a performs the process of step S20 shown in FIG.

That is, the main control CPU 600a uses the setting value (for example, "00H" corresponding to "1" to "6") of the probability of generating a special gaming state advantageous to the player stored in the main control RAM 600c (see FIG. 6). ” to “05H”) and check whether it is less than or equal to the maximum setting value (for example, “05H” corresponding to “6”) (step S20). If it is less than the set maximum value (step S20: YES), it is confirmed whether the backup flag is set to ON (step S21).

<Main control: Main processing: Explanation regarding RAM error processing>
If it is not less than the set maximum value (step S20: NO), or if the backup flag is not set to ON (step S21: NO), the main control CPU 600a causes the sub-control board 80 to write a RAM message indicating that there is a RAM error. An error command (production control command DI_CMD) is transmitted (step S22).

Next, the main control CPU 600a outputs an error display to the LED data port (step S23).

Next, the main control CPU 600a performs a power supply abnormality check process (step S24), returns to the process of step S23, and repeats the process. Note that this power abnormality check process is the same process as the power abnormality check process shown in FIG.

<Main control: Description of main processing>
On the other hand, if the backup flag is set to ON (step S21: YES), the signal of the RAM clear switch 620 is checked (step S25).

<Main control: Main processing: Explanation regarding RAM clear processing>
When the signal of the RAM clear switch 620 is ON (step S25: YES) or when the setting switching process shown in FIG. The normal RAM area and the normal stack area of the main control RAM 600c are cleared without clearing the area (step S26). At this time, a relief count counter, which will be described later, is cleared (0000H is set).

Next, the main control CPU 600a sets the RAM clear notification timer to 30 seconds (30s) (step S27), and connects the hall computer (not shown) used for managing the game island of the game hall via an external terminal (not shown). A timer for outputting a security signal is set to 30 seconds (step S28).

Next, the main control CPU 600a sets initial values in a part of the main control RAM 600c (step S29), and proceeds to the process of step S41. Note that when setting this initial value, an initial value is set in a relief frequency counter to be described later.

<Main control: Description of main processing>
On the other hand, if the signal of the RAM clear switch 620 is OFF (step S25: NO), the main control CPU 600a sends a door open signal indicating whether the upper opening/closing door 7 and the lower opening door 8 are open, and a setting key. The signals of the switches 630 are acquired (step S30), and it is confirmed whether all of them are turned on (step S31). If all are not turned on (step S31: NO), the process advances to step S40.

<Main control: Main processing: Explanation regarding setting confirmation processing>
On the other hand, if all are ON (step S31: YES), the main control CPU 600a transmits a setting value command (effect control command DI_CMD) reflecting the setting value to the sub-control board 80 (step S32).

Next, the main control CPU 600a sets a timer to 30 seconds (30s) to output a security signal to a hall computer (not shown) used for managing the game island of the game hall via an external terminal (not shown). (Step S33).

Next, the main control CPU 600a sets to ON a security signal output to a hall computer (not shown) used for managing the game island of the game hall via an external terminal (not shown), and Then, a security signal is output to the hall computer (not shown) for 30 seconds set by the timer (step S34).

Next, the main control CPU 600a outputs the set value to the LED data port (step S35).

Next, the main control CPU 600a sets a predetermined value in a register in the main control CPU 600a so that a wait of 4 ms is applied, and performs a countdown process (step S36).

Next, the main control CPU 600a performs a power supply abnormality check process (step S37). Note that this power abnormality check process is the same process as the power abnormality check process shown in FIG.

Next, the main control CPU 600a creates switch edge data of the setting key switch 630 signal from the previous and current level data of the setting key switch 630 (step S38). Note that the main control CPU 600a stores the created edge data in the main control RAM 600c.

Next, the main control CPU 600a checks the edge data stored in the main control RAM 600c (step S39), and if the setting key switch 630 is ON (step S39: NO), the process returns to step S34.

<Main control: Description of main processing>
On the other hand, if the setting key switch 630 is OFF (step S39: YES), initial values of the backup flag, error detection timer, etc. are set in a part of the main control RAM 600c (step S40).

Next, the main control CPU 600a transmits to the sub-control board 80 a command (effect control command DI_CMD) indicating whether to recover from a power failure by clearing the RAM or by backing up (step S41). In addition, when transmitting a command (effect control command DI_CMD) indicating whether to recover from a power failure due to backup to the sub-control board 80, the sub-control board sends a relief count command based on the value of the relief count counter described later as the effect control command DI_CMD. 80.

Next, the main control CPU 600a performs a gaming state notification information update process to update the gaming state notification information (step S42).

Next, the main control CPU 600a sets internal function registers (step S43). Specifically, the firing control signal is set to ON and transmitted to the payout control board 70. Thereby, the payout control board 70 controls the firing control board 71 to start its operation. Further, settings are made for the CTC 644 (see FIG. 15), which is provided inside the main control CPU 600a and has a function of creating a pulse output of a constant period, a function of time measurement, and the like. That is, the main control CPU 600a sets the time constant register of the CTC 644 so that a timer interrupt is periodically generated every 4 ms.

Thus, the above-mentioned processing becomes the initial processing in the main control main processing.

Next, the main control CPU 600a calculates performance such as the total number of game balls fired into the game area 40 including the number of winning balls and the number of non-winning balls, with interruptions to itself set to a prohibited state (step S44). The prize ball winning number management process 1 is executed (step S45). Then, the main control CPU 600a performs various random number counter update processes (step S46), returns to the interrupt enabled state (step S47), returns to step S44, and loops in which the processes of steps S44 to S47 are repeated. Perform processing. Note that this loop processing and interrupt processing, which will be described later, are regular processing.

According to the present embodiment, when the power is turned on again after the power is cut off for some reason during the setting change, if the setting switching process (step S19) shown in FIG. 35 is not performed, the steps from step S22 to The RAM becomes abnormal as shown in the process of S24, and only when the setting switching process (step S19) shown in FIG. 35 is performed, a transition to the normal gaming state is made. Furthermore, as shown in step S57 shown in FIG. 37, during the setting change, the security signal is output from the external terminal without monitoring the time, and after the setting change, the security signal is outputted from the external terminal. As shown in steps S33 and S34, the security signal is output from the external terminal for a predetermined period of time by time monitoring. Note that time monitoring is not performed during setting changes because the time required for setting change operations is variable depending on the operator, so if time monitoring is performed, there is a risk that the output of the security signal may stop even during the operation. This is because the processing load increases if a process is included to extend the monitoring time if the device is in operation.

Thus, in the past, if an abnormality occurred in the values in the RAM due to a power outage, there was a possibility that the game would be restarted from the setting change state, with the setting values still potentially affecting the game. However, by performing the processing as in this embodiment, it is possible to reduce the possibility that the game will be restarted, although there is a possibility that the game will be affected.

In addition, in the process of this embodiment, when the power is turned on again after the power is cut off for some reason during the setting change, if the setting switching process (step S19) shown in FIG. 35 is not performed, the steps from step S22 to In the power supply abnormality check process, the main control CPU 600a clears the output data of the output port, but does not set the backup flag to ON so that the RAM becomes abnormal as shown in the process of S24. In addition, when clearing the output data of the output port, the main control CPU 600a clears the output data of the output port (for example, LED data port or LED common port) used when changing settings, and also clears the output data of the output port used when changing settings. It also clears the output data of the output ports that are missing.

In addition, in this embodiment, the setting value of the probability of generating a special gaming state advantageous to the player (for example, the setting value of "00H" to "05H" corresponding to "1" to "6") is set in six levels. Although we have shown an example in which the setting value can be changed, even if there is only one level of setting value (for example, the setting value of ``00H'' corresponding to ``1''), in order to standardize parts and programs, it is possible to have the setting change function as described above. It's okay to do so. At this time, in the setting switching process shown in FIG. 37, even if the setting value stored in the W register is incremented by 1 in step S66, the maximum setting value will be "00H" corresponding to "1", and the In step S56 shown in 37, a process is performed in which the value of the W register becomes "00H". This makes it possible to execute the setting change process using the same program that would be used when there are multiple setting values. In this way, even if the main control CPU 600a overwrites the set value stored in the main control RAM 600c (see FIG. 6) in step S67 shown in FIG. 37, the value remains constant and does not change. There's nothing to do. This makes it possible to share parts and programs.

<Main control: Explanation of timer interrupt processing>
Next, with reference to FIG. 39, a timer interrupt program that interrupts the above-described main processing and is started every 4 ms will be described.

When this timer interrupt occurs, a save process is executed to save the contents of the register group in the main control CPU 600a to the stack area of the main control RAM 600c (step S100), and then a voltage abnormality check process is executed (step S101). This voltage abnormality check process is the same process as the power supply abnormality check process shown in FIG.

Next, the main control CPU 600a controls the special symbol 1 starting port switch 44a (see FIG. 6), the special symbol 2 starting port switch 45a (see FIG. 6), the normal symbol starting port switch 47a (see FIG. 6), and the upper right general Winning port switch 48a1 (see Fig. 6), upper left general winning port switch 48b1 (see Fig. 6), middle left general winning port switch 48c1 (see Fig. 6), lower left general winning port switch 48d1 (see Fig. 6), and out port. ON/OFF signals of various switches including the switch 49a (see FIG. 6) and the big prize opening switch 46c (see FIG. 6) are input, and the ON/OFF signal level and its rise are input to the work area in the main control RAM 600c. The state is stored (step S102). At this time, the main control CPU 600a will transmit information as to whether or not the player touched the handle 16 to play the game to the sub-control board 80 as the production control command DI_CMD. As a result, as shown in FIG. 24(a), even if the movable accessory device 43 moves to the front of the liquid crystal display device 41 during the customer waiting demonstration, the sub control board 80 By receiving the information as to whether or not the user has played the game by touching the handle 16, the sub-control board 80 can cause the game ball to enter the special symbol 1 starting hole 44 (see FIG. 5) as shown in FIG. 24(b). As shown in the figure, the movable accessory device 43 is controlled to return to the origin position (original position), and the liquid crystal display device 41 displays a normal screen (which stops the customer waiting demonstration and displays a variable display of special symbols). It becomes possible to perform control so that the image P60A shown in FIG. 24(b) is displayed. Note that when transmitting the information as to whether or not the player touched the handle 16 to play the game to the sub-control board 80 as the production control command DI_CMD, the one-chip microcomputer 600 uses the asynchronous serial communication circuit ( It will be transmitted to the sub control board 80 by serial transmission using CH1) 647. Therefore, at this time, the main control CPU 600a stores the data to be transmitted in the transmission buffer register TXBUF (see FIG. 17(b)). Moreover, at this time, if the big winning a prize opening switch 46c (see FIG. 6) is ON, a counter for counting the winning and dispensing balls due to the big winning is updated.

Next, the main control CPU 600a performs timer subtraction processing for various timers (normal symbol fluctuation timer, normal symbol accessory timer, etc.) that manage the time of each gaming operation (step S103).

Next, the main control CPU 600a performs random number management processing (step S104). Specifically, processing is performed to update the random numbers of the normal symbols, special symbols, etc. used in the lottery.

Next, the main control CPU 600a performs error management processing (step S105). In addition, the error management process is performed when the supply of game balls stops, or when the game balls are jammed, the special symbol 1 starting port switch 44a (see FIG. 6), the special symbol 2 starting port switch 45a (see FIG. 6), Normal symbol starting opening switch 47a (see Figure 6), upper right general winning opening switch 48a1 (see Figure 6), upper left general winning opening switch 48b1 (see Figure 6), middle left general winning opening switch 48c1 (see Figure 6), lower left This is to determine whether there is any abnormality inside the device, such as disconnection of the general winning opening switch 48d1 (see Figure 6), the out opening switch 49a (see Figure 6), or the big winning opening switch 46c (see Figure 6). be. In addition, when some kind of error occurs, a command (production control command DI_CMD) corresponding to the error will be transmitted to the sub-control board 80. At this time, the one-chip microcomputer 600 transmits data to the sub-control board 80 by serial transmission using the asynchronous serial communication circuit (CH1) 647 shown in FIG. Therefore, at this time, the main control CPU 600a stores the data to be transmitted in the transmission buffer register TXBUF (see FIG. 17(b)).

Next, the main control CPU 600a executes prize ball management processing (step S106). This prize ball management process outputs a payout control command PAY_CMD for causing the payout/launch control board 70 (see FIG. 6) to perform a payout operation. At this time, the one-chip microcomputer 600 will transmit to the payout/emission control board 70 by serial transmission using the asynchronous serial communication circuit (CH0) 646 shown in FIG. Therefore, at this time, the main control CPU 600a stores the data to be transmitted in the transmission buffer register TXBUF (see FIG. 17(b)). Further, a command (performance control command DI_CMD) corresponding to the value of the counter that counts the number of balls acquired and put out due to the jackpot is transmitted to the sub-control board 80. Thereby, the sub-control CPU 800a transmits information corresponding to the received counter value to the VDP 803, and a command list regarding images (videos) to be displayed on the liquid crystal display device 41. As a result, the VDP 803 generates image (video) data to display an image based on the command list, and sends the generated image (video) data to the liquid crystal display device 41. , images such as those shown in FIGS. 27 to 31 will be displayed.

Next, the main control CPU 600a executes normal symbol processing (step S107). This normal symbol processing is to execute a winning/failure lottery of the regular symbols, and to determine the variation pattern of the regular symbols and the stop display state of the regular symbols based on the lottery results. Note that the details of this process will be described later.

Next, the main control CPU 600a executes normal electric accessory management processing (step S108). In this normal electric accessory management process, a signal related to the control of the ordinary electric accessory solenoid 45c (see FIG. 6) necessary for the generation of a normal electric accessory opening game is generated based on the lottery result of the normal symbol processing (step S107). It is something that

Next, the main control CPU 600a executes special symbol processing (step S109). In this special symbol processing, a special symbol lottery is executed, and a variation pattern of the special symbol and a stop display mode of the special symbol are determined based on the result of the lottery. Note that the details of this process will be described later.

Next, the main control CPU 600a executes special electric accessory management processing (step S110). This special electric accessory management process mainly performs the setting process necessary to control the execution of the winning game corresponding to the winning lottery result when the jackpot lottery result is a "big hit" or "small win". be. At this time, a signal related to the control of the special electric accessory solenoid 46b (see FIG. 6) is also generated. Note that when the jackpot lottery result is a "big win" or "small win", a command related thereto (performance control command DI_CMD) is transmitted to the sub control board 80. In addition, in the process of step S110, the main control CPU 600a sets an initial value to a relief number counter, which will be described later, when the jackpot processing starts or when the jackpot processing ends. At this time, the one-chip microcomputer 600 transmits data to the sub-control board 80 by serial transmission using the asynchronous serial communication circuit (CH1) 647 shown in FIG. Therefore, at this time, the main control CPU 600a stores the data to be transmitted in the transmission buffer register TXBUF (see FIG. 17(b)).

Next, the main control CPU 600a performs right-handed hitting notification information management processing (step S111). In this right-handed hitting notification information management process, situations where right-handed hitting is advantageous, such as when the opening/closing member 45b is opened a predetermined number of times and for a predetermined time, or when the opening/closing door 46a is opened and a big prize opening (not shown) is opened. In this step, a process is performed to display a "firing position guidance performance (right-handed hitting notification performance)" that notifies a right-handed hitting instruction. Note that when a right-handed hitting notification performance is performed, a command (performance control command DI_CMD) regarding the right-handed hitting notification performance is transmitted to the sub-control board 80 in this right-handed hitting notification information management process. In addition, in the right-handed hitting notification information management process, in the normal gaming state (state without low power support), when the player plays right-handed, a command (performance control command DI_CMD) related to left-handed hitting warning notification is sent to the sub-control board 80. Sent. As a result, a warning notification such as displaying on the liquid crystal display device 41 an image urging the player to "play left-handed" is executed. However, as shown in FIG. 9(b), when the special symbol miss variation is executed a predetermined number of times (for example, 1000 times) and the transition to the second time-saving gaming state (state with low power support) occurs, the second If the player hits the right hand due to a change in the special symbol before shifting to the time-saving gaming state (state with low power support), a command related to the left-hand hitting warning notification (production control command DI_CMD) is sent to the sub-control board 80. Otherwise, a command regarding the left-handed hitting warning notification (performance control command DI_CMD) is transmitted to the sub-control board 80, and the sub-control CPU 800a is controlled not to issue the left-handed hitting warning notification. As a result, it is possible to prevent a situation that reduces the interest of a player who knows the number of times it will take to shift to the second time-saving gaming state (state with low power support) shown in FIG. 9(b). At this time, the one-chip microcomputer 600 transmits data to the sub-control board 80 by serial transmission using the asynchronous serial communication circuit (CH1) 647 shown in FIG. Therefore, at this time, the main control CPU 600a stores the data to be transmitted in the transmission buffer register TXBUF (see FIG. 17(b)).

Next, the main control CPU 600a executes LED management processing (step S112).

Next, the main control CPU 600a executes external terminal management processing (step S113). In this external terminal management process, a hall computer (not shown) used for managing the game island of the game hall is provided with information such as the number of winnings, the number of changes in special symbols, and winning balls detected in the winning opening during the winning game. Predetermined game information, such as time-saving game state information and security information, is output from an external terminal (not shown). At this time, in the second time-saving game state (state with low power support) shown in FIG. 9(b), the time-saving game state information is output from an external terminal (not shown) together with the state transition information, or Alternatively, after the state transition information is output from an external terminal (not shown), the time saving game state information is output from an external terminal (not shown). Then, in the first time-saving game state (state with low power support) shown in FIG. 9(b) and the first time-saving game state (state with low power support) shown in FIG. 9(c), together with the jackpot information, The time-saving gaming state information is output from an external terminal (not shown), or after the jackpot information is output from the external terminal (not shown), the time-saving gaming state information is output from the external terminal (not shown). . In this way, the second time-saving game state (state with low power support) shown in FIG. 9(b) and the second time-saving game state (state with low power support) shown in FIG. 9(c) In this case, since the information did not go through a hit, it is possible to distinguish between those that went through a hit and those that did not go through a hit, so by performing the above processing, the hole side processes the information appropriately. becomes possible. Note that the state transition information is output based on the later-described relief activation flag being set to ON.

Next, the main control CPU 600a performs solenoid management processing (step S114). At this time, the main control CPU 600a checks the signal related to the control of the normal electric accessory solenoid 45c (see FIG. 6) generated in the ordinary electric accessory management process (step S108), and also checks the signal related to the control of the ordinary electric accessory solenoid 45c (see FIG. 6), and also performs the special electric accessory management process (step S108). The signal related to the control of the special electric accessory solenoid 46b (see FIG. 6) generated in step S110) is confirmed. Based on this signal, the operation/stop of the normal electric accessory solenoid 45c or the special electric accessory solenoid 46b is controlled, and the opening/closing member 45b (see FIG. 5) is opened or closed, or the grand prize opening (not shown) is opened or closed. The opening/closing door 46a (see FIG. 5) operates to open or close.

Next, the main control CPU 600a performs out-of-use area processing (step S115). In this process, the performance display value calculated in the prize ball winning number management process 1 of step S45 shown in FIG. 36 is displayed on the measurement/setting display device 610 (see FIG. 6). Furthermore, in a gaming machine certification test (sight shooting test), processing is performed to update the sight shooting test signal used when outputting various signals related to the game to the testing machine.

Next, the main control CPU 600a clears the WDT 643 shown in FIG. 15 (step S116), returns it to the interrupt enabled state (step S117), restores the contents of the register saved in the stack area of the main control RAM 600c, and interrupts the timer interrupt. (Step S118). This causes the interrupt processing routine to return to the main processing (see FIG. 35).

Thus, as shown in FIG. 23, 20 to 30 ms (see timing T21) after the power is cut off (see timing T20), the voltage abnormality signal ALARM becomes "L" level, and then the first When the timer interrupt occurs, the one-chip microcomputer 600 is supplied with a voltage (DC12V, DC5V) that can execute the control of the gaming operation shown in FIG. 23, so steps S100 to S118 shown in FIG. Processing will be carried out. As shown in FIG. 23, since the voltage (DC12V, DC5V) that can control the gaming operation is no longer supplied 20ms or more after timing T21 (see timing T22), the second timer interrupt will occur. At this time, when the voltage abnormality check process of step S101 shown in FIG. 39 is executed, the value of the power abnormality confirmation counter becomes 2 or more, so the processes of steps S86 to S91 shown in FIG. 38 are executed, and the infinite loop process is performed. The process is repeated and waits for the voltage to drop. Therefore, at the first timer interrupt, the main control CPU 600a stores the data to be transmitted in the transmission buffer register TXBUF (see FIG. 17(b)), but at the second timer interrupt, the main control CPU 600a The data to be transmitted will not be stored in the register TXBUF (see FIG. 17(b)).

Therefore, data to be transmitted is not stored (set) in the transmission buffer register TXBUF (see FIG. 17(b)) other than the first timer interrupt after the power is turned off. Therefore, the transmission time during serial communication is longer than the time from when the voltage abnormality signal ALARM becomes "L" until the voltage becomes such that control of gaming operations cannot be executed (see timing T21 to timing T22 shown in FIG. 23). If the baud rate is set in the transmission baud rate setting register TPR shown in Figure 17(a) so that the time is short, the data stored (set) in the transmission buffer register TXBUF (see Figure 17(b)) will be , the serial communication will be completed by the time it takes for the voltage to reach a level that makes it impossible to control the gaming operation (see timing T21 to timing T22 shown in FIG. 23). As a result, even if a power failure occurs in a situation where prize ball information to be paid out remains on the main control side, the payout operation will be performed normally.

In addition, the main control CPU 600a stores (sets) data to the effect that the backup processing is to be performed due to power shutdown in the transmission buffer register TXBUF (see FIG. 17(b)) at the first timer interrupt after power shutdown. Therefore, it is possible to transmit to the payout/launch control board 70 and the sub-control board 80 that the main control board 60 has been powered off and has entered backup processing. This allows these control boards to execute processing in preparation for power cutoff.

On the other hand, if the boat rate is set high in order to increase the amount of data to be transmitted, as mentioned above, for example, 12.5 bits can be transmitted in 1 ms, so the first timer interrupt will cause the transmission buffer register TXBUF (Fig. 17(b)) is stored (set) when the second timer interrupt occurs after serial transmission starts and the value of the power supply abnormality confirmation counter is 2 or more (step S85 shown in FIG. 38: Serial communication will be completed until YES). Even with this arrangement, even if a power failure occurs in a situation where prize ball information to be paid out remains on the main control side, the payout operation will be performed normally.

On the other hand, as explained in the timer interrupt processing shown in FIG. 39, within one timer interrupt processing, the one-chip microcomputer 600 uses the asynchronous serial communication circuit (CH0) 646 shown in FIG. When transmitting the payout control command PAY_CMD to the payout/launch control board 70, only one payout control command PAY_CMD is stored (set) in the transmission buffer register TXBUF (see FIG. 17(b)). On the other hand, within one timer interrupt process, the one-chip microcomputer 600 transmits the production control command DI_CMD to the sub-control board 80 by serial transmission using the asynchronous serial communication circuit (CH1) 647 shown in FIG. In doing so, a plurality of production control commands DI_CMD will be stored (set) in the transmission buffer register TXBUF (see FIG. 17(b)).

Therefore, if only one payout control command PAY_CMD is stored (set) in the transmission buffer register TXBUF (see FIG. 17(b)) in one timer interrupt process, it will be possible to With the timer interrupt, one payout control command PAY_CMD can be sent, so that unsent commands will not continue to be stored (set) in the transmission buffer register TXBUF (see FIG. 17(b)). . Therefore, even if the one-chip microcomputer 600 is reset due to the power being cut off, the unsent payout control command PAY_CMD is not stored (set) in the transmission buffer register TXBUF (see FIG. 17(b)). Therefore, by clearing the unsent payout control command PAY_CMD, it is possible to prevent a situation where the player is disadvantaged.

<Main control: Description of normal symbol processing>
Next, with reference to FIG. 40, the above normal symbol processing will be explained in detail.

As shown in FIG. 40, in the normal symbol processing, first, it is confirmed whether or not the passing of a game ball is detected at the normal symbol starting port 47 (see FIG. 5) consisting of a gate. The signal level of the normal symbol starting port switch 47a (see FIG. 6) is confirmed (step S150). When the passage of the game ball is detected (step S150: YES), the main control CPU 600a stores the number of starting pending balls of the normal symbol in order to judge whether the starting pending ball number of the normal symbol is, for example, 4 or more. The main control RAM 600c is checked (step S151). At that time, if the starting pending ball number of the normal symbol is less than 4 (step S151:≠MAX), 1 is added to the starting pending ball number of the normal symbol (step S152). Thereafter, the main control CPU 600a stores the random number value for normal symbol hit judgment used for the normal symbol winning/failure lottery in the main control RAM 600c in which the start pending ball count of the normal symbol is stored (step S153), and then steps S154. Proceed to processing.

On the other hand, if the passage of the game ball is not detected in step S150 (step S150: NO), and if it is determined in step S151 that the number of balls on hold for starting the normal symbol is 4 or more (step S151:= MAX), the processing in steps S152 to S153 is not performed and the process proceeds to step S154.

When proceeding to the process of step S154, the main control CPU 600a checks whether the normal symbol per operation flag is set to ON, that is, whether 5AH is set to the normal symbol per operation flag (step S154). If 5AH is set in the normal symbol hit activation flag (step S154: ON), it is determined that the normal symbol is winning, and after updating the display data of the normal symbol (step S163), the normal symbol processing is performed. finish.

On the other hand, if 5AH is not set in the normal symbol per operation flag (step S154: OFF), the processing state indicating the behavior of the normal symbol, that is, the value of the normal symbol operation status flag is confirmed (step S155). If the normal symbol operation status flag is 00H, the main control CPU 600a determines that the normal symbol is in a state before the start of fluctuation, proceeds to step S156, and determines whether or not the starting pending ball count of the normal symbol is 0. Confirm (step S156).

The main control CPU 600a checks the main control RAM 600c in which the starting pending ball count of the normal symbol is stored, and if it is determined to be 0 (step S156: = 0), updates the display data of the normal symbol. After doing so (step S163), the normal symbol processing ends. On the other hand, if it is determined that it is not 0 (step S156:≠0), the number of starting pending balls of the normal symbol is subtracted by 1 (step S157).

Thereafter, the main control CPU 600a uses the normal symbol hit determination table NPP_TBL shown in FIG. 51(a) to perform a hit determination of a random value corresponding to the number of start pending balls of the normal symbol stored in the main control RAM 600c. That is, the main control CPU 600a determines that if the normal symbol probability change flag indicating the gaming state is OFF, the random value is the lower limit value (in the illustration, 249) It is determined whether or not it is below the upper limit value (250 in the illustration), and if it is above the lower limit value and below the upper limit value, the normal symbol hit determination flag is set to 5AH and turned ON. In other cases, the normal symbol hit determination flag is turned OFF.

On the other hand, if the normal symbol probability variation flag indicating the gaming state is ON, the random number value is equal to or higher than the lower limit value (4 in the illustration) of the normal symbol hit determination table NPP_TBL (probability variation state) shown in FIG. 51(a). It is determined whether or not it is below a value (250 in the illustration), and if it is above the lower limit and below the upper limit, the normal symbol hit determination flag is set to 5AH and turned ON. In other cases, processing is performed to set the normal symbol hit determination flag to OFF (step S158).

Then, the main control CPU 600a determines a stop symbol (normal symbol stop symbol) based on the lottery result determined in the random number lottery process (step S159).

Next, the main control CPU 600a checks whether the normal symbol time reduction flag that shortens the variation time of the normal symbol is set to ON, and if it is set to ON, sets the variation time in the normal symbol variation timer accordingly. However, if it is set to OFF, a process of setting a normal variation time to the normal symbol variation timer is performed (step S160).

In addition, in this embodiment, an example has been described in which the winning probability of a normal symbol is high probability state in the electric support state. In the second time-saving game state, the second time-saving game state is transferred to the second time-saving game state without going through a jackpot, so there is a possibility that the rules may prohibit the winning probability of the normal symbol from becoming a high probability state. In that case, the winning probability of the normal symbols remains the same as in the normal game state, and a normal symbol time-saving game state is created in which the fluctuation time of the normal symbols is shortened. As a result, even if the normal symbols do not become in a high probability state, the variation time of the normal symbols is shortened, the frequency of drawing of the normal symbols increases, and it becomes easier for the normal symbols to win. Furthermore, when transitioning to the first time-saving game state, the winning probability of the normal symbol may be set to a high probability state, and when transitioning to the second time-saving gaming state, the winning probability of the normal symbol may not be changed from the normal gaming state. . On the other hand, the winning probability of the normal symbol may not be changed from the normal gaming state in either the case of transitioning to the first time-saving gaming state or the case of transitioning to the second time-saving gaming state.

Next, the main control CPU 600a shifts the storage area of the main control RAM 600c in which the random number value used for the winning/failure lottery of the normal symbol corresponding to the number of start pending balls of the normal symbol is stored (step S161). In other words, assuming that the maximum number of pending balls at the start of a normal symbol can be held at 4, the random value used for the winning/failure lottery of the normal symbol corresponding to the number of pending balls at the start of the normal symbol, 4, is set to the number of pending balls at the start of the normal symbol, 3. Shifts to the main control RAM 600c in which the random value used for the winning/failure lottery of the corresponding normal symbol was stored, and transfers the random value used for the winning/failure lottery of the normal symbol corresponding to the starting pending ball number 3 of the normal symbol to the start/failure lottery of the normal symbol. Shifts to the main control RAM 600c in which the random value used for the lottery for the normal symbol corresponding to the number of pending balls 2 is stored, and the random value used for the lottery for the regular symbol corresponding to the number of pending balls 2 for the start of the normal symbol is stored. is shifted to the main control RAM 600c in which the random number value used for the winning/failure lottery of the normal symbol corresponding to the number of starting pending balls of the normal symbol 1 was stored.

After this process, the main control CPU 600a sets the normal symbol operation status flag used in step S155 to 01H, and the random value used for the lottery of the normal symbol corresponding to the starting pending ball number 4 of the normal symbol is set to 01H. Processing is performed to set 00H in the stored main control RAM 600c (step S162).

After the main control CPU 600a finishes the process of step S162, it updates the display data of the normal symbol (step S163), and ends the normal symbol process.

On the other hand, in step S155, the main control CPU 600a determines that the normal symbol is in a processing state indicating the behavior of the normal symbol, that is, if the value of the normal symbol operation status flag is 01H, the main control CPU 600a determines that the normal symbol is changing. After making a judgment, the process proceeds to step S164, and it is confirmed whether or not the normal symbol variation timer is 0 (step S164). If the normal symbol variation timer is not 0 (step S164:≠0), the display data of the normal symbol is updated (step S163), and the normal symbol processing is finished. Then, if the normal symbol fluctuation timer is 0 (step S164:=0), the main control CPU 600a sets the normal symbol operation status flag used in step S155 to 02H, and keeps the winning/failure lottery result of the normal symbol constant. In order to maintain the time, a time of about 600 ms, for example, is set in the normal symbol variation timer (step S165).

After finishing the process of step S165, the main control CPU 600a updates the display data of the normal symbol (step S163), and ends the normal symbol process.

On the other hand, if the main control CPU 600a determines in step S155 that the normal symbol is in a processing state indicating the behavior of the normal symbol, that is, if the value of the normal symbol operation status flag is 02H, the main control CPU 600a determines that the normal symbol is displayed during the confirmation time (normal It is determined that the symbol fluctuation has ended and the symbol is stopped), and the process proceeds to step S166, where it is checked whether the normal symbol fluctuation timer is 0 or not (step S166). If the normal symbol variation timer is not 0 (step S166:≠0), the display data of the normal symbol is updated (step S163), and the normal symbol processing is finished. Then, if the normal symbol fluctuation timer is 0 (step S166:=0), the main control CPU 600a sets the normal symbol operation status flag used in step S155 to 00H (step S167), and determines whether the normal symbol is hit. It is confirmed whether the flag is set to ON (5AH is set) (step S168).

As a result, if the normal symbol hit determination flag is set to OFF (5AH is not set) (step S168: OFF), the main control CPU 600a updates the display data of the normal symbol (step S163), Finish normal pattern processing. Then, if the normal symbol hit determination flag is set to ON (5AH is set) (step S168: ON), the main control CPU 600a turns on the normal symbol hit activation flag used in step S154 (sets 5AH). After setting (step S169), the normal symbol processing ends.

<Main control: Explanation of special symbol processing>
Next, the above special symbol processing will be explained in detail with reference to FIGS. 41 to 50.

As shown in FIG. 41, in the special symbol processing, first, the special symbol 1 starting port switch 44a (see FIG. 6) of the special symbol 1 starting port 44 (see FIG. 5) is used to activate the incoming game ball (winning ball). It is confirmed whether or not it has been detected (step S200), and furthermore, the game ball (winning ball) is detected using the special symbol 2 starting port switch 45a (see FIG. 6) of the special symbol 2 starting port 45 (see FIG. 5). It is confirmed whether or not it has been detected (step S201).

<Main control: Special symbol processing: Explanation of starting port check processing>
To explain this process in detail using FIG. 42, the main control CPU 600a checks whether the game ball has entered the special symbol 1 starting hole 44 or the special symbol 2 starting hole 45 (winning), that is, the special The level of the special symbol 1 starting port switch 44a of the symbol 1 starting port 44 or the special symbol 2 starting port switch 45a of the special symbol 2 starting port 45 is confirmed (step S250). As a result, if the ball entering the game ball (winning) is not detected (step S250: NO), the special symbol processing ends.

On the other hand, if it is detected that a game ball enters (wins) (step S250: YES), the main control CPU 600a determines whether a predetermined number of starting pending balls, which is a trigger for changing the special symbol, is stored in the main control RAM 600c. (Step S251). If the number of starting pending balls is less than 4 (step S251:≠MAX), 1 is added (+1) to the starting number of pending balls (step S252).

Next, the main control CPU 600a stores the random number used when stopping the special symbol, the random number for the variation pattern, and the random number for jackpot determination in the main control RAM 600c, which stores the number of starting pending balls that trigger the variation of the special symbol. (step 253).

Next, the main control CPU 600a checks the current gaming state (whether or not the special symbol jackpot determination flag is set to ON, etc.), and determines whether or not pre-reading is prohibited (step S254). Then, if the pre-reading is not prohibited (step S254: NO), the main control CPU 600a acquires the random number value for jackpot determination used for the lottery of the special symbol stored in the main control RAM 600c in step S253 (step S255). ), and further obtains a starting opening winning random number determination table (not shown) (step S256).

Next, the main control CPU 600a performs a jackpot lottery using the random number value for jackpot determination acquired in step S255 and the random number determination table (not shown) at the time of starting opening prize winning acquired in step S256, and further performs the jackpot lottery. The type of jackpot (rank up bonus hit, normal jackpot, etc.) is determined using the random number value for the special symbol stored in the main control RAM 600c in step S253, and the variation pattern is determined using the random number value for the variation pattern. Then, a special symbol start opening winning command is generated accordingly (step S257). In addition, at this time, not only the jackpot lottery, but also the small winning lottery and special electric support symbol lottery, and either use the random number for the special symbol explained above, or use a random number different from the random number for the special symbol. The type of small hit and the type of special electric support symbol may be determined by using the random number value for the fluctuation pattern, and the fluctuation pattern may be determined using the random number value for the fluctuation pattern, and a special symbol starting opening winning command may be generated accordingly.

Next, the main control CPU 600a generates a starting pending addition command of the lower byte according to the special symbol starting opening winning command generated above (step S258).

On the other hand, the main control CPU 600a determines whether the process of step S258 is finished, or whether the number of starting pending balls of special symbol 1 or 2 is 4 or more in step S251 (step S251:=MAX), or whether the pre-reading If it is in the prohibited state (step S254: YES), a starting pending addition command of the upper byte corresponding to the increased number of starting pending pitches is generated (step S259).

Next, the main control CPU 600a combines the low-order byte start-pending addition command generated in step S258 and the high-order byte start-pending addition command generated in step S259, and then outputs the start-pending addition command (effect The control command DI_CMD) is transmitted to the sub-control board 80 (step S260).

<Main control: Explanation of special symbol processing>
In this way, when the processing of step S200 and step S201 shown in FIG. It is confirmed whether there is one (step S202). If 5AH is set in the special symbol small hit activation flag (step S202: ON), it is determined that the special symbol is in a small hit, and after updating the display data of the special symbol (step S208), the special symbol is activated. Finish the pattern processing.

On the other hand, if 5AH is not set in the special symbol jackpot activation flag (step S202: OFF), check whether the special symbol jackpot activation flag is set to ON, that is, whether 5AH is set in the special symbol jackpot activation flag. is confirmed (step S203). If 5AH is set in the special symbol jackpot activation flag (step S203: ON), it is determined that the special symbol is hitting the jackpot, and after updating the display data of the special symbol (step S208), the special symbol is processed. finish.

On the other hand, if 5AH is not set in the special symbol jackpot operation flag (step S203: OFF), the processing state indicating the behavior of the special symbol, that is, the value of the special symbol operation status flag is confirmed (step S204). To explain in more detail, if the value of the special symbol operation status flag is 00H or 01H, the main control CPU 600a indicates that the special symbol is on standby (the special symbol has not been varied and is in a standby state for the next variation). ), and special symbol variation start processing is performed (step S205).

<Main control: Special symbol processing: Explanation of special symbol fluctuation start processing>
This process will be described in detail with reference to FIG. 43. The main control CPU 600a checks whether or not the starting pending ball count, which is a trigger for changing the special symbol, is 0 (step S300). That is, the main control CPU 600a checks whether or not it is stored in the main control RAM 600c, and if it is determined that the starting pending ball count is 0 (step S300: = 0), the value of the special symbol operation status flag is 00H. It is confirmed whether or not (step S301). If the value of the special symbol operation status flag is 00H (step S301: YES), the special symbol variation start process is ended.

On the other hand, if the value of the special symbol operation status flag is not 00H (step S301: NO), the main control CPU 600a transmits the customer waiting demonstration command as the performance control command DI_CMD to the sub control board 80 (see FIG. 6) (step S302).

Next, the main control CPU 600a sets the special symbol operation status flag to 00H (step S303), and ends the special symbol variation start process.

On the other hand, if the main control CPU 600a determines that the number of starting pending balls is not 0 (step S300: ≠ 0), it subtracts 1 (-1) from the starting pending ball number (step S304), and controls the starting pending subtraction command. The command DI_CMD is sent to the sub control board 80 (sub control CPU 800a) (step S305).

Next, the main control CPU 600a confirms the value of a rescue number counter, which will be described later, and transmits a rescue number command as an effect control command DI_CMD to the sub-control board 80 (sub-control CPU 800a) (step S306). Thereby, the sub-control CPU 800a can grasp how many times the special symbol deviation variation shown in FIG. 9(b) has been executed. Therefore, as shown in FIG. 9(b), before the special symbol deviation variation is executed a predetermined number of times (for example, 1000 times) and the transition to the second time-saving gaming state (state with low power support), If the power is cut off (power outage), when the power is turned on again and the game is resumed, the sub-control CPU 800a will display on the liquid crystal display device 41 the number of times remaining up to the predetermined number of times (for example, 1000). The background image (video) used when returning to play is different from the background image (video) when returning to play, or some of the lighting of the decorative lamps is controlled to be different from the lighting of the decorative lamps when returning to play. be able to. In addition, as shown in FIG. 9(b), the special symbol is changed a predetermined number of times (for example, 1000 times), and before the transition to the second time-saving gaming state (state with low power support), the power supply If the power has been cut off (power outage), when the power is turned on again and the game is resumed, the sub-control CPU 800a will repeat the above-mentioned predetermined number of times (for example, 1000 times) in the variation of the special symbol in the first rotation after returning to the game. It can be controlled to perform effects according to the number of times remaining.

<Main control: Special symbol processing: Explanation of sending relief number of commands>
This process will be described in detail with reference to FIG. 44. The main control CPU 600a acquires the value (2-byte data) of a relief count counter, which will be described later (step S350).

Next, the main control CPU 600a checks the value of the acquired relief counter (step S351). If the value is 0 (step S351: YES), the process of sending the relief count command is finished.

On the other hand, if the value is not 0 (step S351: NO), the main control CPU 600a divides the obtained value of the rescue counter by 100. Then, the main control CPU 600a stores the divided quotient in the L register inside the main control CPU 600a, and stores the remainder in the H register inside the main control CPU 600a (step S352).

Next, the main control CPU 600a adds (+1) to the L register and adds (+1) to the H register (step S353).

Next, the main control CPU 600a stores DBH in the D register inside the main control CPU 600a, and stores the value of the L register in the E register inside the main control CPU 600a. Then, the main control CPU 600a transmits the value of the DE register to the sub-control board 80 (sub-control CPU 800a) as the first rescue count command 1 (effect control command DI_CMD) (step S354).

Next, the main control CPU 600a stores the DCH in the D register inside the main control CPU 600a, and stores the value of the H register in the E register inside the main control CPU 600a. Then, the main control CPU 600a transmits the value of the DE register to the sub-control board 80 (sub-control CPU 800a) as the second command, the relief count command 2 (effect control command DI_CMD) (step S355), and sends the relief count command. Finish processing.

Thus, by doing this, the sub control CPU 800a subtracts 1 from the lower byte of the first command and subtracts 1 from the lower byte of the second command. Then, the value of the lower byte of the first command, which has been subtracted by 1, is multiplied by 100, and the value of the lower byte of the second command, which has been subtracted by 1, is added. Thereby, the sub-control CPU 800a can grasp how many times the special symbol deviation variation shown in FIG. 9(b) has been executed. Also, when displaying numbers on the liquid crystal display device 41 using the VDP803, subtract 1 from the lower byte of the first command to the thousands and hundreds digits, and subtract 1 from the lower byte of the 2nd command. It will be displayed as numbers in the tens and ones place.

By doing this, it is possible to not only make the command structure easier to understand, but also to reduce the control burden.

<Main control: Special symbol processing: Explanation of special symbol fluctuation start processing>
In this way, after completing the above-mentioned process of transmitting the relief number command (step S306), the main control CPU 600a checks the value of the special symbol time reduction number counter, which will be described later, and sends the time reduction number command as the production control command DI_CMD to the sub. It is transmitted to the control board 80 (sub control CPU 800a) (step S307). In response to this, the sub-control CPU 800a either does not display the current number of time reductions on the liquid crystal display device 41 until the number of time reductions falls below a predetermined number of time reductions, or displays a fixed number of times, such as 100 times, on the liquid crystal display device 41. A command list regarding images (video) is sent to the VDP 803. As a result, the VDP 803 generates image (video) data to display an image based on the command list, and sends the generated image (video) data to the liquid crystal display device 41. In this case, either the current number of time saving times is not displayed, or a fixed number of times, such as 100 times, is displayed. Then, when the predetermined number of time reductions has been reached, the sub-control CPU 800a transmits the received time reduction number information to the VDP 803, a command list regarding images (videos) to be displayed on the liquid crystal display device 41. As a result, the VDP 803 generates image (video) data to display an image based on the command list, and sends the generated image (video) data to the liquid crystal display device 41. The current number of time reductions will be displayed.

<Main control: Special symbol processing: Explanation of time saving number of times command transmission>
This process will be described in detail with reference to FIG. 45. The main control CPU 600a acquires the value (2-byte data) of a special symbol time saving counter described later (step S360).

Next, the main control CPU 600a checks the value of the acquired special symbol time saving counter (step S361). If the value is 0 (step S361: YES), the process of transmitting the time saving number of times command is completed.

On the other hand, if the value is not 0 (step S361: NO), the main control CPU 600a checks whether the value of the acquired special symbol time saving counter exceeds 100 (step S362). If the value exceeds 100 (step S362: YES), the main control CPU 600a stores DDH in the D register inside the main control CPU 600a, and stores 7FH in the E register inside the main control CPU 600a. Then, the main control CPU 600a transmits the value of the DE register to the sub-control board 80 (sub-control CPU 800a) as a time-saving frequency command (effect control command DI_CMD) (step S363), and ends the process of transmitting the time-saving frequency command. In response to this, the sub control CPU 800a can confirm that the number of time reductions is not less than the predetermined number of time reductions (100), and therefore either does not display it on the liquid crystal display device 41 or displays a fixed number of times such as 100 times on the liquid crystal display. A command list related to images (video) to be displayed on the device 41 is transmitted to the VDP 803. As a result, the VDP 803 generates image (video) data to display an image based on the command list, and sends the generated image (video) data to the liquid crystal display device 41. In this case, either the current number of time saving times is not displayed, or a fixed number of times, such as 100 times, is displayed.

On the other hand, if the value is 100 or less (step S362: NO), the main control CPU 600a stores DDH in the D register inside the main control CPU 600a, and stores the special symbol time saving in the E register inside the main control CPU 600a. Stores the value of the lower byte of the number of times counter. Then, the main control CPU 600a transmits the value of the DE register to the sub-control board 80 (sub-control CPU 800a) as a time-saving frequency command (effect control command DI_CMD) (step S364), and ends the process of transmitting the time-saving frequency command.

<Main control: Special symbol processing: Explanation of special symbol fluctuation start processing>
In this way, after completing the process of transmitting the time saving number command as described above (step S307), the main control CPU 600a transmits the random value used when stopping the special symbol, the random value for the fluctuation pattern, and the random value for jackpot determination (see FIG. 42). (see step S253) is stored in the main control RAM 600c (step S308), and the memory area in the main control RAM 600c in which the random number used for the lottery of the special symbol corresponding to the start pending 4 is stored is shifted. 0 is set in the area (step S309).

Next, the main control CPU 600a performs a hit determination process (step S310).

<Main control: Special symbol processing: Explanation of hit determination processing>
To explain this process in detail using FIG. 46, the main control CPU 600a acquires the random number value for jackpot determination from the main control RAM 600c in which the random number value for jackpot determination (see step S253 in FIG. 42) is stored (see step S253 in FIG. 42). Step S370).

Next, the main control CPU 600a acquires the address of the hit determination table corresponding to the changing special symbol. That is, the addresses of the special symbol jackpot determination table SDH_TBL shown in FIG. 51(b) and the special symbol small hit determination table SDP_TBL shown in FIG. 51(c) are acquired (step S371).

Next, the main control CPU 600a changes the acquired address to the address where the determination value is stored (step S372).

Next, the main control CPU 600a acquires information as to whether the determination value is different for each setting value (step S373), and confirms the value of the acquired information (step S374). If the acquired value is "0" (step S374:=0), the process advances to step S377, and if the acquired value is not "0" (step S374:≠0), the main control CPU 600a Setting values of the probability of generating a special gaming state advantageous to the player stored in the RAM 600c (see FIG. 6) (for example, setting values of "00H" to "05H" corresponding to "1" to "6") (step S375).

Next, the main control CPU 600a changes the address to the address where the determination value corresponding to the acquired setting value is stored (step S376). For example, when acquiring the judgment value of the upper limit when the gaming state is normal (low certainty state), if the obtained setting value is "1", the address where the judgment value "10164" of setting value 1 is stored If the setting value is "6", the address address where the judgment value "10200" of the setting value 6 is stored is changed, and the address address that refers to the data in the judgment table is changed.

Next, the main control CPU 600a obtains the determination value from the current address. For example, if it is related to a jackpot and the information on whether the judgment value differs for each set value is "000H", a judgment value of "10000" is acquired, and the information on whether the judgment value differs for each setting value is "000H". 001H" and the set value is "1", a determination value of "10164" is obtained (step S377).

Next, the main control CPU 600a changes the address address to the first address address where the next determination value is stored (step S378), and compares the acquired random number value for jackpot determination with the acquired determination value (step S379).

Next, if the acquired random number value for jackpot determination is not smaller than the acquired determination value (step S380: NO), the main control CPU 600a returns to the process of step S373, and determines that the acquired random number value for jackpot determination is less than the acquired determination value. The processes from step S373 to step S380 are repeated until it becomes smaller (step S380: YES).

Next, if the acquired random value for jackpot determination becomes smaller than the acquired determination value (step S380: YES), the main control CPU 600a acquires a special symbol jackpot determination flag and a special symbol small hit determination flag according to the gaming state. (Step S381), the hit determination process ends.

<Main control: Special symbol processing: Explanation of special symbol fluctuation start processing>
After completing the hit determination process (step S310) as described above, the main control CPU 600a performs the special electric support symbol hit determination process (step S311). In addition, this process is a process of performing a lottery using random numbers for jackpot determination when playing a game with special electric support symbols without also using them as small winning symbols.

<Main control: Special symbol processing: Explanation of special electric support symbol hit determination processing>
To explain this process in detail using FIG. 47, the main control CPU 600a acquires the random number value for jackpot determination from the main control RAM 600c in which the random number value for jackpot determination (see step S253 in FIG. 42) is stored (see step S253 in FIG. 42). Step S390).

Next, the main control CPU 600a acquires the address of the special electric support winning symbol determination table corresponding to the changing special symbol. Here, the address of the special electric support symbol determination table D_RNDJDG2 shown in FIG. 48 corresponding to the changing special symbol 1 is acquired. The special electric support symbol hit determination table data corresponding to the special electric support symbol hit determination table TDS_TBL shown in FIG. 51(d) is shown in FIG. This special electric support symbol hit determination table will be explained with reference to FIG. 48. This special electric support symbol hit determination table stores determination values and values of special electric support symbol hit determination flags.

Specifically, as can be easily understood by referring to the special electric support symbol hit determination table TDS_TBL shown in FIG. 51(d), the lower limit of the determination value is "30001".
DW 30000
DB 000H
is programmed.

Also, as can be easily understood by referring to the special electric support symbol hit determination table TDS_TBL shown in FIG. 51(d), the upper limit of the determination value is "30218", so
DW 30218
DB 05AH
is programmed.

On the other hand, regarding this special electric support symbol hit determination table, as shown in FIG. 48, the upper limit value (65535) of the random number value for jackpot determination is programmed as follows.
DW 65535
DB 000H

Therefore, if the determination value for winning the special electric support symbol does not overlap with the winning determination value range for either the jackpot or the small win, it can be used in the win determination process of step S310 shown in FIG. 43. This means that a lottery can be held using the random numbers for jackpot determination.

In this way, the main control CPU 600a acquires the address of the special electric support symbol hit determination table as described above (step S391).

Next, the main control CPU 600a changes the acquired address to the address where the determination value shown in FIG. 48 is stored (step S392).

Next, the main control CPU 600a obtains the determination value shown in FIG. 48 from the current address (step S393).

Next, the main control CPU 600a changes the address address to the first address address where the next determination value is stored (step S394), and compares the acquired random number value for jackpot determination with the acquired determination value (step S395).

Next, if the acquired random number value for jackpot determination is not smaller than the acquired determination value (step S396: NO), the main control CPU 600a returns to the process of step S393, and determines that the acquired random number value for jackpot determination is less than the acquired determination value. The processes from step S393 to step S396 are repeated until it becomes smaller (step S396: YES).

Next, if the acquired random value for jackpot determination becomes smaller than the acquired determination value (step S396: YES), the main control CPU 600a acquires the special electric support symbol hit determination flag shown in FIG. 48 (step S397), The special electric support symbol hit determination process ends.

<Main control: Special symbol processing: Explanation of special symbol fluctuation start processing>
Thus, after completing the special electric support symbol hit determination process (step S311) as described above, the main control CPU 600a stores the random value used when stopping the special symbol stored in the main control RAM 600c in step S253 of FIG. Using this, a stop symbol of the special symbol is generated (step S312).

Next, the main control CPU 600a prepares to shift to a gaming state such as a normal state, a time saving state, a variable probability state, a variable probability state, etc. (step S313). In addition, here, among the normal symbol time saving flag, normal symbol probability variable flag, special symbol time saving flag, and special symbol probability variable flag, which are set after the jackpot when it becomes a jackpot, turn on the flag according to the gaming state after the transition. Prepare the flag data for this in advance. In addition, the number of time reductions to be set in the special symbol time reduction number counter and the number of probability changes to be set in the special symbol probability variation number counter will also be prepared.

Next, the main control CPU 600a generates a special symbol variation pattern using the random value for variation pattern stored in the main control RAM 600c in step S253 of FIG. 42, and generates a variation pattern of the generated special symbol variation pattern. The command is sent to the sub-control board 80 (sub-control CPU 800a) as a production control command DI_CMD (step S314). At this time, the main control CPU 600a refers to the variation pattern tables shown in FIGS. 10 to 13. That is, first, the main control CPU 600a refers to the table TBL shown in FIG. 10(a). In the normal gaming state, the variable pattern table NOR_TBL shown in FIG. 10(b) is used as the variable pattern table to be referred to. Furthermore, in the first time-saving game state shown in FIG. 9(b) or the first time-saving game state shown in FIG. 9(c), in the variation of the special symbols from the 1st to the 79th rotation, as shown in FIG. 11(a) The variation pattern table JT1_TBL1 shown in FIG. The fluctuation pattern table JT1_TBL3 shown in FIG. 12(a) is used. Furthermore, in the second time saving game state shown in FIG. 9(b) or the second time saving gaming state shown in FIG. 9(c), the fluctuation of the special symbol in the first rotation is as shown in FIG. 12(b). The fluctuation pattern table JT2_TBL1 is used, and the fluctuation pattern table JT2_TBL2 shown in FIG. The variation pattern table JT2_TBL3 shown in No. 13 is selected. Therefore, a variation pattern of the special symbol is generated according to the variation pattern table selected in this way, and the variation pattern command of the generated variation pattern of the special symbol is used as the production control command DI_CMD, and the sub control board 80 ( It is transmitted to the sub control CPU 800a). In response to this, the sub-control CPU 800a executes the variation of the special symbol a predetermined number of times (for example, 1000 times) as shown in FIG. ), when the special symbol changes for a predetermined number of times (for example, 1000 times), the time-saving rush performance is not executed, and immediately after the transition to the second time-saving gaming state (state with low power support), for example. When the special symbol changes for the 1001st time, a time-saving effect such as displaying an image urging the player to "hit right" on the liquid crystal display device 41 is executed.

In addition, as shown in FIG. 9(b), when transitioning to the second time-saving game state (state with low power support), even if the special symbol lottery is won and the jackpot is reached, the liquid crystal display 41, a time-saving effect including a right-handed hitting notification such as displaying an image urging the player to ``hit right'' is first executed, and the presentation changes midway through.

Furthermore, the variation of the special symbol reaches a predetermined number of times (for example, 100 times) from the first time saving state (state with low voltage support) shown in FIG. 9(c) or FIG. 9(b), and the normal gaming state ( When returning to the state (with no low voltage support), the sub-control CPU 800a displays a result effect on the liquid crystal display device 41 (win ○○ times, control to display the number of acquired ○○○ points, etc.). However, when the special symbol changes from the second time-saving game state (state with low power support) shown in FIG. ), or when the special symbol changes reach a predetermined number of times (for example, 1000 times) from the second time-saving game state (state with low power support) shown in FIG. 9(b), the normal game state (low power support state) When returning to the state (without electric support), since the variation pattern is selected using the same variation pattern table as before the final variation, the variation pattern command for executing the result presentation is not sent to the sub-control CPU 800a. The sub-control CPU 800a controls the liquid crystal display device 41 so that the result effect is not displayed after a predetermined number of final fluctuations.

In addition, in this step S314, the main control CPU 600a will set a variation time to the special symbol variation timer.

Next, the main control CPU 600a sets the special symbol fluctuation flag to 5AH and turns it on (step S315).

Next, the main control CPU 600a generates a symbol designation command for designating a special symbol to be displayed on the liquid crystal display device 41 (step S316), and sends the generated symbol designation command to the sub control board 80 (sub control board 80) as an effect control command DI_CMD. A process of transmitting the information to the control CPU 800a) is performed (step S317).

Next, the main control CPU 600a sets the special symbol operation status flag to 02H (step S318), and ends the special symbol variation start process.

<Main control: Explanation of special symbol processing>
On the other hand, as shown in FIG. 41, when the value of the special symbol operation status flag is 02H, the main control CPU 600a determines that the special symbol is changing (indicating that the special symbol is currently changing), and Processing during symbol variation is performed (step S206).

<Main control: Special symbol processing: Explanation of special symbol fluctuation processing>
To explain this process in detail using FIG. 49, the main control CPU 600a first determines whether the variation time set in the special symbol variation timer in step S314 of FIG. 43 has elapsed, that is, whether it has reached 0. is confirmed (step S400). If the special symbol fluctuation timer is not 0 (step S400: NO), the main control CPU 600a ends the special symbol fluctuation processing.

On the other hand, if the special symbol fluctuation timer is 0 (step S400: YES), the main control CPU 600a transmits the symbol confirmation command as the production control command DI_CMD to the sub-control board 80 (sub-control CPU 800a) (step S401).

Next, the main control CPU 600a sets the special symbol operation status flag to 03H, and sets the special symbol fluctuation flag to 00H. Furthermore, the main control CPU 600a sets the special symbol fluctuation timer to, for example, about 500 ms in order to maintain the winning/failure lottery result of the special symbol for a certain period of time (step S402). After that, the main control CPU 600a ends the special symbol variation process.

<Main control: Explanation of special symbol processing>
On the other hand, as shown in FIG. 41, when the value of the special symbol operation status flag is 03H, the main control CPU 600a determines that the special symbol is being confirmed (indicating that the special symbol has finished changing and is stopped). It is determined and processing is performed during the special symbol confirmation time (step S207).

<Main control: Special symbol processing: Explanation of processing during special symbol confirmation time>
To explain this process in detail using FIG. 50, the main control CPU 600a first determines whether the variation time set in the special symbol variation timer in step S314 of FIG. 43 has elapsed, that is, whether it has reached 0. is confirmed (step S450). If the special symbol fluctuation timer is not 0 (step S450≠0), the main control CPU 600a ends the process during the special symbol confirmation time.

On the other hand, if the special symbol fluctuation timer is 0 (step S450 = 0), the main control CPU 600a sets the special symbol operation status flag to 01H (step S451), and checks whether the special symbol jackpot determination flag is set to ON. (Whether 5AH is set) is confirmed (step S452). If the special symbol jackpot determination flag is set to ON (if 5AH is set) (step S452: YES), the special symbol jackpot determination flag is set to 00H, and the special symbol jackpot activation flag is set to 5AH. Then, the normal symbol time saving flag is set to 00H, the normal symbol probability change flag is set to 00H, the special symbol time saving flag is set to 00H, and the special symbol probability change flag is set to 00H. Furthermore, processing is performed to set 0000H in the special symbol time saving frequency counter and 00H in the special symbol probability variation frequency counter, which will be described later (step S453).

Next, the main control CPU 600a sets the relief number counter to 0000H, and sets the relief activation flag to 0FFH, which indicates that the special symbol miss variation has been executed a predetermined number of times (for example, 1000 times) in the relief game (step S454). ). After that, the main control CPU 600a ends the process during the special symbol confirmation time.

On the other hand, if the special symbol jackpot determination flag is not set to ON (if 5AH is not set) (step S452: NO), the main control CPU 600a determines whether the special symbol small hit determination flag is set to ON ( 5AH is set (step S455). If the special symbol small hit determination flag is set to ON (if 5AH is set) (step S455: YES), the special symbol small hit determination flag is set to 00H, and the special symbol small hit activation flag is set to 5AH. is set (step S456). In addition, if the small winning symbol and the special electric support symbol are used together, in preparation for the transition to the second time-saving game state, turn on the normal symbol time-saving flag, the normal symbol probability change flag, and the special symbol time-saving flag (set 5AH). ) and set the number of time reductions in the special symbol time reduction counter. Alternatively, in step S110 shown in FIG. 39, when the jackpot process starts or when the jackpot process ends, the normal symbol time saving flag, the normal symbol probability change flag, and the special symbol time saving flag are turned ON (5AH is set), Set the number of time saving times in the special symbol time saving number counter. On the other hand, if the small hit symbol and the special electric support symbol are not used together, if the special electric support symbol hit determination flag is set to ON as in step S455, the special electric support symbol determination flag is set to 00H, In preparation for shifting to a second time-saving game state, a normal symbol time-saving flag, a normal symbol probability change flag, and a special symbol time-saving flag are turned ON (5AH is set), and the number of time-saving times is set in a special symbol time-saving number counter.

After finishing the process of step S456, or if the special symbol small hit determination flag is not set to ON (if 5AH is not set) (step S455: NO), the main control CPU 600a executes the special symbol time saving process. It is checked whether the value of the number counter is 0 or not (step S457).

If the value of the special symbol time saving number counter is not 0 (step S457: NO), the value of the special symbol time saving number counter is subtracted by 1 (-1) (step S458), and the main control CPU 600a again calculates the special symbol time saving number of times. It is checked whether the value of the counter is 0 or not (step S459). If the value of the special symbol time reduction counter is 0 (step S459: YES), the normal symbol time reduction flag is set to 00H, the normal symbol probability change flag is set to 00H, and the normal symbol time reduction flag is set to 00H. Set. Furthermore, an initial value is set in the relief frequency counter (step S460).

After completing the process of step S460, or if the value of the special symbol time reduction counter is 0 (step S457: YES), or if the value of the special symbol time reduction counter is not 0 (step S459: NO), the main The control CPU 600a checks whether the value of the special symbol probability variation counter is 0 or not (step S461). If the value of the special symbol probability variation counter is 0 (step S461: YES), the process moves to step S465.

On the other hand, if the value of the special symbol probability variation counter is not 0 (step S461: NO), the main control CPU 600a subtracts 1 (-1) from the value of the special symbol probability variation counter (step S462), and again It is checked whether the value of the probability variation counter is 0 (step S463). If the value of the special symbol probability variation counter is not 0 (step S463: NO), the process moves to step S465.

On the other hand, if the value of the special symbol probability change count counter is 0 (step S463: YES), the main control CPU 600a sets the normal symbol time saving flag to 00H, sets the normal symbol probability variation flag to 00H, and sets the special symbol time saving flag to 00H. 00H is set to 00H, and the special symbol probability change flag is set to 00H (step S464), and the process moves to step S465.

Next, the main control CPU 600a checks whether the special symbol probability change flag is ON (set to 5AH) (step S465). If the special symbol probability change flag is set to ON (if set to 5AH) (step S465: YES), the main control CPU 600a ends the process during the special symbol confirmation time.

On the other hand, if the special symbol probability change flag is not set to ON (if not set to 5AH) (step S465: NO), the main control CPU 600a determines whether or not the relief activation flag is set to ON (5AH is set). is confirmed (step S466). If the relief activation flag is set to ON (if set to 5AH) (step S466: YES), the main control CPU 600a finishes the process during the special symbol confirmation time.

On the other hand, if the relief activation flag is not set to ON (if not set to 5AH) (step S466: NO), the main control CPU 600a checks whether the value of the relief number counter is 0 or not (step S467). ). If the value of the relief number counter is 0 (step S466: YES), the main control CPU 600a ends the process during the special symbol confirmation time.

On the other hand, if the value of the relief count counter is not 0 (step S467: NO), the value of the relief count counter is subtracted by 1 (-1) (step S468), and the main control CPU 600a again sets the value of the relief count counter to 0 (step S467: NO). It is confirmed whether or not it is 0 (step S469). If the value of the relief count counter is not 0 (step S469: NO), the main control CPU 600a ends the process during the special symbol confirmation time. On the other hand, if the value of the relief number counter is 0 (step S469: YES), the main control CPU 600a turns on the special symbol time reduction flag (sets 5AH) and sets the number of time reduction in the special symbol time reduction number counter. Further, the main control CPU 600a turns on the relief activation flag (sets 5AH), turns on the right-handed state flag (sets 5AH) (step S470), and ends the process during the special symbol confirmation time. As described above, when the relief activation flag is set to ON, in step S113 shown in FIG. 39, the state transition information is output from an external terminal (not shown).

After the relief count counter is set to 0000H and cleared in step S26 shown in FIG. 36, an initial value is set in step S29 shown in FIG. Then, in the normal game state, counting is executed in step S468 shown in FIG. 50, and the second time-saving game state (special symbol time-saving flag ON state) shown in FIG. 9(b) or FIG. 9(c) In this case, as shown in step S466: YES in FIG. 50, the relief count counter is not cleared (0000H is not set) and counting is not performed. Furthermore, when the second time-saving game state (the state where the special symbol time-saving flag is ON) shown in FIG. 9(b) or FIG. 9(c) ends, the relief count counter is set in step S460 shown in FIG. , an initial value is set according to the state of the relief activation flag, and in the normal game state shifted from the second time-saving game state shown in FIG. 9(b) or FIG. 9(c), step S468 shown in FIG. Counting will be performed at As a result, the value of the relief counter is set and counting is performed at an appropriate location, so unnecessary processing can be omitted, thereby simplifying the processing.

<Main control: Explanation of special symbol processing>
Thus, after completing any one of the processes in step S205, step S206, and step S207 shown in FIG. 41, the main control CPU 600a updates the display data of the special symbol (step S208), and then finishes the special symbol process. .

Incidentally, in this embodiment, an example is shown in which the relief count counter is subtracted, but it may be incremented. This point will be explained in detail using FIG. 52. Note that the same processes as those described above are given the same reference numerals, and the description thereof will be omitted.

<Main control: Special symbol processing: Explanation of processing during special symbol confirmation time (modified example)>
As shown in FIG. 52, if the special symbol probability change flag is not set to ON (if not set to 5AH) (step S465: NO), the main control CPU 600a adds the value of the relief number counter (+1). (Step S500), and it is checked whether the value of the relief count counter has reached the number of relief reaches (for example, 1000) (Step S501). If the number of relief arrivals (for example, 1000) has been reached (step S501: YES), the process of step S470 is performed and the process during the special symbol confirmation time is ended.

On the other hand, if the number of rescue attempts (for example, 1000) has not been reached (step S501: NO), the main control CPU 600a checks whether the value of the rescue number counter is 0000H (step S502). If the value of the rescue number counter is not 0000H (step S502: NO), the process during the special symbol confirmation time ends.

On the other hand, if the value of the relief number counter is 0000H (step S502: YES), the value of the relief number counter is subtracted (-1) (step S503), and the process during the special symbol confirmation time is ended. The reason why the value of the relief counter is subtracted (-1) in step S503 is as follows. That is, unless the special symbol probability is changing, the relief number counter adds a value (+1). Therefore, after the value of the relief count counter reaches the relief count, the relief count counter continues to count up to FFFFH, which is the upper limit of 2 bytes, unless there is a jackpot. Therefore, if the count value of the relief counter is added (+1) when it is FFFFH, the count value becomes 0000H, so in order to return it to FFFFH, it is subtracted (-1) (0000H-0001H=FFFFH). ).

However, even in this case, the same effect as described above can be achieved.

By the way, in either case of subtracting or adding the relief number counter, once the relief activation flag is set to ON (set to 5AH), the special symbol jackpot determination flag is set to ON (set to 5AH) (step S452: YES) Unless a jackpot is hit, the relief activation flag remains ON. Therefore, if the power is cut off (power outage) and the power is turned on again to return to the game, the relief activation flag is ON, and it is not in the second time-saving game state (state with low power support), in other words, the second time-saving game When the state (state with low power support) has ended and the normal gaming state has been entered, the relief activation flag remains ON even if the special symbol loses fluctuation is executed a predetermined number of times (for example, 1000 times). Therefore, the second time-saving game state (state with low electricity support) will not be entered. Therefore, a command indicating this is sent to the sub control board 80 as the production control command DI_CMD in step S41 shown in FIG. This makes it possible for the sub-control CPU 800a to recognize this fact, thereby making it possible to notify the player.

Furthermore, the transmission of the relief number command shown in FIG. 44 and the time reduction number command transmission shown in FIG. 45 can also be performed as shown in FIGS. 53 and 54. This point will be specifically explained below.

<Main control: Special symbol processing: Explanation of sending relief count command (modified example)>
As shown in FIG. 53, first, the main control CPU 600a checks whether the relief activation flag is ON (step S510). If the relief activation flag is ON (step S510: YES), the process of sending the relief count command is completed. In other words, if the relief activation flag is ON, this indicates that the special symbol has been changed a predetermined number of times (for example, 1000 times). There is no need to send it to the CPU 800a). Therefore, if the relief activation flag is ON (step S510: YES), it is not necessary to send an unnecessary command to the sub-control board 80 (sub-control CPU 800a) if the process is finished without sending the relief count command. The load on the sub-control board 80 (sub-control CPU 800a) can be reduced.

On the other hand, if the relief activation flag is not ON (step S510: NO), the main control CPU 600a stores the value of the relief frequency counter (2-byte data) in the HL register inside the main control CPU 600a (step S511). .

Next, the main control CPU 600a checks whether the value of the relief count counter stored in the HL register is 0 (step S512). If the value is 0 (step S512: YES), the process of sending the relief count command is finished.

On the other hand, if the value is not 0 (step S512: NO), data division processing is performed (step S513).

<Main control: Special symbol processing: Explanation of data division processing>
To explain this process in detail using FIG. 55, the main control CPU 600a divides the value of the HL register by 100. Then, the main control CPU 600a stores the divided quotient in the L register inside the main control CPU 600a, and stores the remainder in the H register inside the main control CPU 600a (step S550).

Next, the main control CPU 600a adds (+1) to the L register, adds (+1) to the H register (step S551), and ends the data division process.

<Main control: Special symbol processing: Explanation of sending relief count command (modified example)>
Thus, after completing the data division process (step S513) as described above, the main control CPU 600a stores DBH in the D register inside the main control CPU 600a, and stores the L register in the E register inside the main control CPU 600a. Store the value of . Then, the main control CPU 600a transmits the value of the DE register to the sub-control board 80 (sub-control CPU 800a) as the first command, the rescue count command 1 (effect control command DI_CMD) (step S514).

Next, the main control CPU 600a stores the DCH in the D register inside the main control CPU 600a, and stores the value of the H register in the E register inside the main control CPU 600a. Then, the main control CPU 600a transmits the value of the DE register to the sub-control board 80 (sub-control CPU 800a) as the second command, the relief count command 2 (effect control command DI_CMD) (step S515), and sends the relief count command. Finish processing.

Thus, by doing this, the sub control CPU 800a subtracts 1 from the lower byte of the first command and subtracts 1 from the lower byte of the second command. Then, the value of the lower byte of the first command, which has been subtracted by 1, is multiplied by 100, and the value of the lower byte of the second command, which has been subtracted by 1, is added. Thereby, the sub-control CPU 800a can grasp how many times the special symbol deviation variation shown in FIG. 9(b) has been executed. Also, when displaying numbers on the liquid crystal display device 41 using the VDP803, subtract 1 from the lower byte of the first command to the thousands and hundreds digits, and subtract 1 from the lower byte of the 2nd command. It will be displayed as numbers in the tens and ones place.

Even with this arrangement, it is possible to not only make the command structure easier to understand, but also to reduce the control burden.

<Main control: Special symbol processing: Explanation of time saving number of times command transmission (modified example)>
On the other hand, in a modification of the time saving number command transmission, as shown in FIG. Step S520).

Next, the main control CPU 600a checks whether the value of the special symbol time saving counter stored in the HL register is 0 or not (step S521). If the value is 0 (step S521: YES), the process of transmitting the time saving number of times command is completed.

On the other hand, if the value is not 0 (step S521: NO), data division processing shown in FIG. 55 is performed (step S522).

Next, the main control CPU 600a stores DDH in the D register inside the main control CPU 600a, and stores the value of the L register in the E register inside the main control CPU 600a. Then, the main control CPU 600a transmits the value of the DE register to the sub-control board 80 (sub-control CPU 800a) as the first command time saving number command 1 (effect control command DI_CMD) (step S523).

Next, the main control CPU 600a stores DEH in the D register inside the main control CPU 600a, and stores the value of the H register in the E register inside the main control CPU 600a. Then, the main control CPU 600a transmits the value of the DE register to the sub-control board 80 (sub-control CPU 800a) as the second command, the time-saving frequency command 2 (effect control command DI_CMD) (step S524), and sends the time-saving frequency command. Finish processing.

Thus, by doing this, the sub control CPU 800a subtracts 1 from the lower byte of the first command and subtracts 1 from the lower byte of the second command. Then, the value of the lower byte of the first command, which has been subtracted by 1, is multiplied by 100, and the value of the lower byte of the second command, which has been subtracted by 1, is added. As a result, the sub-control CPU 800a can grasp the number of time-savings in the second time-saving game state (state with low electricity support) shown in FIGS. 9(b) and 9(c). Also, when displaying numbers on the liquid crystal display device 41 using the VDP803, subtract 1 from the lower byte of the first command to the thousands and hundreds digits, and subtract 1 from the lower byte of the 2nd command. It will be displayed as numbers in the tens and ones place.

Even in this case, not only can the command structure be made easier to understand, but also the control burden can be reduced.

In addition, as shown in Figure 55, if the process of dividing 2-byte data into the thousands and hundreds places is made into a subroutine, the number of time-savings can be reduced compared to the specification that sends the thousands and hundreds places and the tens and ones places with two commands. In this case, it can be used as a common subroutine with the rescue count command, thereby reducing the program capacity.

<Processing details of sub-control board>
Next, the method of processing the effects shown in FIGS. 25 to 34 will be specifically explained with reference to the processing contents (outline of the program) of the sub-control board 80 shown in FIGS. 56 to 60.

First, when the power is turned on to the pachinko game machine 1, a power-on signal indicating that the power has been turned on is sent from the power supply board 130 (see FIG. 6) to each control board. Upon receiving the signal, the sub control CPU 800a performs the main processing shown in FIG. 56.

<Sub control: Main processing>
As shown in FIG. 56, first, the sub control CPU 800a initializes internally provided registers and sets the input/output direction of the input/output port. Further, data transmitted from the output port set in the output direction is set to be serially transferred (step S1000).

Next, the sub-control CPU 800a initializes a memory area in the sub-control RAM 800c that stores the production control command DI_CMD received from the main control board 60 (see FIG. 6) (step S1001). Then, the sub-control CPU 800a performs interrupt permission setting processing for the input port that receives the interrupt signal from the main control board 60 (step S1002).

Next, the sub-control CPU 800a initializes a memory area in the sub-control RAM 800c used as a work area and a stack area (step S1003), and issues an initialization command to the sound LSI 801 (see FIG. 6). As a result, the sound LSI 801 initializes the register provided therein (step S1004).

Next, the sub-control CPU 800a determines whether an abnormality has occurred in the motor (not shown) that operates the upper, left, right, and upper left movable accessories 43a to 43d (see FIG. 5). ) Check the memory area in the sub control RAM 800c where the motor data for operating the motor is stored. If abnormal data is stored, the sub-control CPU 800a issues a command to return the motor to its home position. As a result, the upper, left, right, and upper left movable accessories 43a to 43d return to their initial positions (step S1005).

Next, the sub-control CPU 800a sets up a CTC (Counter Timer Circuit) provided therein, which has a function of creating a pulse output of a constant period, a function of time measurement, and the like. That is, the sub control CPU 800a sets the time constant register of the CTC so that a timer interrupt is periodically generated every 1 ms (step S1006).

Next, the sub-control CPU 800a performs a checksum operation, which is an 8-bit addition operation, on the work area of the sub-control RAM 800c (step S1007), and uses the checksum operation value and a memory backup (see step S1015) to be described later. The calculated checksum value is compared with the checksum calculation value stored in the sub-control RAM 800c, and it is confirmed whether or not they match (step S1008). If they do not match (step S1008: NO), a process is performed to clear all areas in the sub control RAM 800c (step S1009).

On the other hand, if there is a match (step S1008: YES) or after completing the process in step S1009, the sub-control CPU 800a cancels the watchdog timer function (not shown) (step S1010), and hardware such as the sub-control CPU 800a and VDP 803 A refresh is executed (step S1011).

Next, the sub-control CPU 800a reads the production control command DI_CMD received from the main control board 60 (see FIG. 6) stored in the memory area in the sub-control RAM 800c, and outputs a production pattern according to the content to the sub-control CPU 800a. It is determined by lottery from among a large number of performance patterns stored in advance in the control ROM 800b (step S1012). At this time, the sub control CPU 800a performs a lottery using the sub control fluctuation pattern distribution table SUB_FR_TBL shown in FIG. 33(a), and based on the lottery result, the left symbol lottery distribution table HC_FR_TBL shown in FIG. A lottery is conducted using the symbol change notice table ZH_TBL shown in (c). Then, the sub-control CPU 800a uses the symbol change notice table ZH_TBL shown in FIG. 33(c) to perform the changing symbol lottery distribution shown in FIG. A lottery will be held using table HZC_FR_TBL.

Thus, the determined fluctuation pattern is set as an offset value, and the left symbol lottery distribution table HC_FR_TBL shown in FIG. 33(b) and the symbol change notice table ZH_TBL shown in FIG. 33(c) are created based on the offset value. By performing a lottery using , it is possible to select a table according to the offset value, thereby reducing the control burden.

On the other hand, the sub-control CPU 800a refers to the table HK_TBL shown in FIG. 32(a), and refers to the first distribution table FR_TBL1 shown in FIG. 32(b) in the variation of special symbols in the 1st to 19th rotations after the background change. Then, a lottery will be held. At this time, no matter what the fluctuation pattern is, the winning result is made without any background change.

Further, the sub-control CPU 800a performs a lottery with reference to the second distribution table FR_TBL2 shown in FIG. 32(c) in the variation of the special symbol from the 20th to the 39th rotation after the background change. Then, the sub-control CPU 800a performs a lottery with reference to the third distribution table FR_TBL3 shown in FIG. 32(d) in the variation of the special symbol from the 40th to the 59th rotation after the background change. Further, the sub-control CPU 800a performs a lottery with reference to the fourth distribution table FR_TBL4 shown in FIG. 32(e) in the variation of the special symbol starting from the 60th rotation after the background change. At this time, no matter what the variation pattern, the background change is always executed.

Therefore, if we prepare the first distribution table FR_TBL1, which is a distribution table in which the distribution values for which background changes are executed are all "0" (no winnings for background changes), and perform the lottery, the control There is no need to perform controls such as not changing the background as a preview effect, thereby reducing the control burden. Furthermore, in the debugging work related to the background change lottery, which is a preview performance, it is only necessary to check the distribution table, so that the number of man-hours required for debugging can be reduced.

On the other hand, when a 2-byte data command is sent, the sub control CPU 800a subtracts 1 from the lower byte of the first command, and subtracts 1 from the lower byte of the second command. Then, the value of the lower byte of the first command, which has been subtracted by 1, is multiplied by 100, and the value of the lower byte of the second command, which has been subtracted by 1, is added.

Next, the sub-control CPU 800a performs a process of analyzing the input contents of the setting button 15 or the effect button device 13 acquired in the timer interrupt process described later (step S1013). Specifically, analysis is performed to determine whether the setting button 15 or the production button device 13 is pressed by the player, the moment it is released, or whether it remains pressed.

Next, the sub-control CPU 800a controls the operation of the upper, left, right, and upper left movable accessories 43a to 43d (see FIG. 5) and the decorative lamp board 90 ( Control is performed to turn on or off decorative lamps such as LED lamps (see FIG. 6), control the speaker 17, and control the image displayed on the liquid crystal display device 41 (step S1014). At this time, if the background change lottery is won, the sub-control CPU 800a sets the current background in the first background data and sets the changing background in the second background data. Then, the sub-control CPU 800a counts the VSYNC interrupt signal, and as shown in FIG. When reaching , the changing background set in the second background data is set in the first background data.

Next, the sub-control CPU 800a performs a checksum operation, which is an 8-bit addition operation, on the work area of the sub-control RAM 800c, and performs memory backup processing to store the checksum operation value in the sub-control RAM 800c (step S1015).

Next, the sub control CPU 800a checks whether a VSYNC interrupt signal has been transmitted from the VDP 803 to the sub control CPU 800a (step S1016). If the VSYNC interrupt signal is not transmitted (step S1016: NO), the sub control CPU 800a repeatedly executes the process of step S1016 until the VSYNC interrupt signal is transmitted. (Step S1016: YES), the process returns to step S1007 again, and the processes of steps S1007 to S1016 are repeated.

<Sub-control: Data analysis processing>
Next, with reference to FIG. 57, the data analysis process in step S1014 of the main process will be described in detail. First, the sub-control CPU 800a selects performance scenario data PS_DATA (see FIG. 7(a)) corresponding to the performance pattern determined by lottery in step S1012 from the performance scenario table PR_TBL, and stores it in the selected performance scenario data PS_DATA. Based on various data (frame data PS_DATA10, control code data PS_DATA11, coordinate data PS_DATA12, pixel calculation data PS_DATA13, scaling data PS_DATA14) stored in the 1-layer data PS_DATA1, the VDP 803 displays an image on the liquid crystal display device 41. A command list for generating data is generated (step S1050). At this time, a command list for generating image data to be displayed on the liquid crystal display device 41 as described using FIGS. 9(b) and 9(c) is also generated. Furthermore, a command list for generating image data to be displayed on the liquid crystal display device 41 as described using FIGS. 27 to 31 is also generated. Further, image data corresponding to the contents set in the first background data, as specific examples, are shown in FIGS. 34(b-1) to (b-5) and FIG. 34(c-1) to (c-5). A command list for generating image data to be displayed on the liquid crystal display device 41 as described above is also generated.

Next, the sub control CPU 800a inputs data indicating that the pressing effect of the effect button device 13 is valid or the setting button 15 to the button data PS_DATA113 (see FIG. 7(c)) stored in the selected effect scenario data PS_DATA. If data indicating that the continuous hit effect is valid is stored, the data is stored in a memory area in the sub control RAM 800c.

Further, the sub-control CPU 800a generates a control signal related to light based on the data content of the lamp data PS_DATA17 (see FIG. 7(b)) stored in the selected performance scenario data PS_DATA, and generates a control signal in the sub-control RAM 800c. Perform processing to store in . At this time, a control signal related to the light for lighting the decorative lamp as described using FIGS. 9(b) and 9(c) is also generated.

Further, the sub control CPU 800a controls the upper, left, right, and upper left movable accessories 43a based on the data content of the movable accessory data PS_DATA16 (see FIG. 7(b)) stored in the selected production scenario data PS_DATA. - 43d is determined, and motor data for the motor (not shown) of the movable accessory device 43 is generated in accordance with the determined operation content.

Furthermore, the sub control CPU 800a generates a control signal regarding sound based on the data content of the sound data PS_DATA15 (see FIG. 7(b)) stored in the selected performance scenario data PS_DATA (step S1051).

In this way, the sub-control CPU 800a repeatedly performs the processes of steps S1050 and S1051 until all the data based on the effect pattern determined by lottery in step S1012 shown in FIG. 56 has been generated (step S1052: NO). When all data has been generated (step S1052: YES), the process advances to step S1053.

Next, the sub-control CPU 800a performs button activation processing based on the content stored in the sub-control RAM 800c in step S1051 and the input content of the setting button 15 or production button device 13 processed in step S1013 shown in FIG. (Step S1053).

<Sub control: Command reception interrupt processing>
Next, with reference to FIG. 58, a description will be given of the processing when the production control command DI_CMD and the interrupt signal are transmitted from the main control board 60 during the execution of such main processing.

As shown in FIG. 58, when the sub-control CPU 800a receives the interrupt signal, it executes a saving process to save the contents of each register to the stack area in the sub-control RAM 800c (step S1100). Thereafter, the sub-control CPU 800a reads the register of the input port that received the production control command DI_CMD (step S1101), and calculates a pointer indicating the address of the command transmission/reception memory area in the sub-control RAM 800c (step S1102).

After that, the sub-control CPU 800a again reads the register of the input port that received the production control command DI_CMD (step S1103), and checks whether the value read in step S1101 and the value read in step S1103 match. Check. If they do not match (step S1104: NO), the process advances to step S1107, and if they match (step S1104: YES), the production control command received from the main control board 60 is sent to the address corresponding to the pointer calculated above. DI_CMD is stored (step S1105). Note that this stored performance control command DI_CMD will be read out by the sub control CPU 800a during the process of step S1012 shown in FIG.

Next, the sub-control CPU 800a updates the pointer indicating the address of the command transmission/reception memory area in the sub-control RAM 800c (step S1106), and restores the register saved in the process of step S1100 (step S1107). Thereby, the process returns to the main process shown in FIG. 56.

<Sub control: timer interrupt processing>
Next, with reference to FIG. 59, a description will be given of a process when a timer interrupt occurs every 1 ms, which is set in the process of step S1006 (see FIG. 56) of the main process.

As shown in FIG. 59, when a timer interrupt occurs every 1 ms, the sub-control CPU 800a executes a saving process to save the contents of each register to the stack area in the sub-control RAM 800c (step S1150).

Next, the sub-control CPU 800a acquires the data of the setting button 15, the data of the production button device 13, the motor data of the movable accessory device 43, etc. twice (step S1151), and determines whether the data acquired twice match. It is confirmed whether or not (step S1152). If the data do not match (step S1152: NO), the sub-control CPU 800a repeats the process of step S1151 until the data match, and if they match (step S1152: YES), the sub-control CPU 800a transfers the matched data to the sub-control RAM 800c. (step S1153).

Next, the sub control CPU 800a receives a signal from the setting button 15 or the effect button device 13 (step S1154). This received signal will be analyzed in the button analysis process of step S1013 shown in FIG.

Next, the sub-control CPU 800a transmits the light-related control signal stored in the sub-control RAM 800c in step S1051 shown in FIG. 57 to the decorative lamp board 90 (see FIG. 6) (step S1155). Note that a control signal necessary to turn on or off the identification lamp device 50A (see FIG. 5) will also be transmitted.

Next, the sub control CPU 800a restores the register saved in the process of step S1150 (step S1156). Thereby, the process returns to the main process shown in FIG. 56.

<Sub control: Command list>
Here, the command list generated in step S1050 shown in FIG. 57 will be explained in detail using FIG. 60.

This command list is a command string that lists instructions for the VDP 803 (command parser 8035), but the contents and order of the entries differ depending on whether it is an instruction to draw a video or a still image. differ.

When instructing the VDP 803 to draw a moving image, the initial command list shown in FIG. 60(a) and the regular command list shown in FIG. 60(b) are configured.

As shown in FIG. 60(a), the sub-control CPU 800a first generates a command to set the memory area of the DDR2SDRAM 804 in which the frame buffer area is set and the memory area in which the video data of the DDR2SDRAM 804 is stored ( Step S1200). Note that in setting the memory area of the DDR2SDRAM 804 where the frame buffer area is set, the image size data PS_DATA 112 shown in FIG. 7(c) is referred to. That is, if the size is, for example, 640×320, a memory area will be set accordingly.

Next, a command to instruct video decoding is generated (step S1201). Specifically, this is an instruction as to which moving image compressed data is to be decoded, along with the address of the CG data storage area of the game ROM 805 where the corresponding moving image is stored, the number of frames of the moving image, and the like. Note that address data PS_DATA111 shown in FIG. 7(c) is referred to for the address address of the CG data storage area where the corresponding video is stored, and the number of frames of the video is determined by frame data PS_DATA10 shown in FIG. 7(b). is referenced.

Next, a termination processing command is entered to finish generating the initial command list (step S1202).

Subsequently, the sub-control CPU 800a generates a regular command list shown in FIG. 60(b).

As shown in FIG. 60(b), this regular command list is composed of moving image drawing instructions. A command indicating at which coordinate position of the image is to be drawn is generated (step S1203). Next, the end processing command is entered to finish generating the regular command list (step S1204). Note that for command generation for this drawing instruction, frame data PS_DATA10, coordinate data PS_DATA12, pixel calculation data PS_DATA13, and scaling data PS_DATA14 shown in FIG. 7(b) are referred to.

On the other hand, when instructing the VDP 803 to draw a still image, as shown in FIG. 60(c), the sub-control CPU 800a first stores the memory area of the DDR2SDRAM 804 in which the frame buffer area is set and the still image data. A command for setting the memory area of the built-in VRAM 8040 is generated (step S1210). Note that in setting the memory area of the DDR2SDRAM 804 in which the frame buffer area is set, the image size data PS_DATA 112 shown in FIG. 8(c) is referred to. That is, if the size is, for example, 640×320, a memory area will be set accordingly.

Next, a command instructing to decode the still image is generated (step S1211). Specifically, this is an instruction as to which still image compressed data is to be decoded, together with the address and data size of the CG data storage area of the game ROM 805 in which the relevant still image is stored. Note that address data PS_DATA111 shown in FIG. 7(c) is referred to for the address address of the CG data storage area where the relevant still image is stored, and the data size is determined by image size data PS_DATA112 shown in FIG. 7(c). Referenced.

Next, a command is generated for drawing the decoded still image data at which coordinate position on the liquid crystal display device 41 and in what manner (rotation angle, reduction/enlargement, etc.) (step S1212). Next, a command for termination processing is entered to finish generating the command list regarding the still image (step S1213). Note that for command generation for this drawing instruction, frame data PS_DATA10, coordinate data PS_DATA12, pixel calculation data PS_DATA13, and scaling data PS_DATA14 shown in FIG. 7(b) are referred to.

In this way, such a command list regarding moving images and a command list regarding still images are transmitted to the VDP 803 (see FIG. 9), processed as appropriate, and then transmitted to the liquid crystal display device 41. As a result, desired images (for example, FIGS. 27 to 31, FIGS. 34(b-1) to (b-5), and FIGS. 34(c-1) to (c-5)) are displayed on the liquid crystal display device 41. It will be done.

By the way, such a command list instructs to draw a moving image and then instructs to draw a still image. That is, the sub control CPU 800a uses the effect control command DI_CMD sent from the main control CPU 600a to select one of the effects among the plural effects scenario data PS_DATA stored in the effect scenario table PR_TBL shown in FIG. 7(a). This is to select the scenario data PS_DATA, refer to the one-layer data PS_DATA1 stored in the selected performance scenario data PS_DATA in order of priority, and generate a command list. That is, according to the present embodiment, control code data such that the data PS_DATA110 (see FIG. 7(c)) indicating a moving image is referenced from the control table CH_TBL shown in FIG. 7(c) is placed in a position with a low priority. PS_DATA11 is stored, and control code data PS_DATA11 such that data PS_DATA110 (see FIG. 7(c)) indicating a still image is referenced from the control table CH_TBL shown in FIG. 7(c) is stored at a high priority position. Therefore, a command list that instructs to draw a moving image is generated first, and then a command list that instructs to draw a still image is generated. As a result, after the moving image data is drawn, the still image data is overwritten and drawn on the drawn moving image data, thereby generating image data to be displayed on the liquid crystal display device 41.

In this way, image data is generated by overwriting and drawing still image data on the drawn moving image data, so that even if the image is a compressed image, characters can be clearly displayed.

In addition, in this embodiment, the display method of the measurement/setting display device 610 is only shown as an example in which the display is lit, but the display is not limited to this, and the display on the measurement/setting display device 610 may be displayed blinking while changing the settings. You can do it like this.

Further, in this embodiment, an example was shown in which the sound LSI 801 and the VDP 803 are configured separately, but they may be integrated as one chip.

Further, in this embodiment, the frame buffer area is set in the DDR2SDRAM 804, but the frame buffer area is not limited to this, and the frame buffer area may be set in the built-in VRAM 8040.

Further, in this embodiment, an example is shown in which the sub-control CPU 800a is provided within the sub-one-chip microcomputer 800, but the sub-control CPU 800a may be provided within the VDP 803.

1 Pachinko machine
41 Liquid crystal display device (count display means)
KAI high-speed fluctuation animation

Claims (2)

count updating means for updating a predetermined count value as the game progresses;
a count display means for displaying the predetermined count value updated by the count update means in a plurality of numbers,
The count display means is
Displaying a fluctuation animation indicating that the predetermined count value is updated;
The fluctuation animation is
When displaying the updated predetermined count value on the count display means, a high-speed fluctuation animation is displayed for the first digit of a plurality of numbers, regardless of the value before the update of the predetermined count value. displaying on the count display means a low-speed fluctuation animation to the extent that a change can be visually recognized for the second digit adjacent to the first digit;
The gaming machine displays the high-speed fluctuation animation a predetermined number of times or for a predetermined time until the second digit changes to a number indicating the updated predetermined count value. The low-speed fluctuation animation is a fluctuation animation to the extent that it can be visually recognized that the numbers are changing by 1,
The high-speed fluctuation animation can be repeatedly displayed for a predetermined number of times or for a predetermined time until the second digit changes from the predetermined count value before updating to the predetermined count value after update. The gaming machine according to claim 1.

Images