JP7291640B2 - Semiconductor memory device and refresh method for semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor memory device and a refresh method for a semiconductor memory device.

In recent years, the demand for NAND flash memory has increased in storage devices such as SSD (Solid State Drive) and SD (Secure Digital) cards, mobile devices, and the like. Along with this, the capacity of NAND flash memory is increasing.

In a NAND flash memory, a phenomenon (hereinafter referred to as data deterioration) occurs in which correct data values cannot be read due to poor data retention due to physical deterioration of the gate insulating film, charge transfer due to read disturbance, and the like. In order to cope with such data deterioration, refresh processing of the memory area is performed in the NAND flash memory (for example, Patent Document 1).

The refresh process is a process of once reading data written in a block of the NAND flash memory for all pages in the block and rewriting it to another block. The refresh process is performed, for example, when deterioration of data is found during reading of data. Normally, data is read from a NAND flash memory page by page, and data is erased block by block. Since the refresh process involves erasing data, it is performed in units of blocks.

JP-A-2009-87509

The data recording methods for memory cells include the SLC (Single Level Cell) method that records 1-bit data in one memory cell, the MLC (Multiple Level Cell) method that records 2-bit data, and the 3-bit data recording method. There is a TLC (Triple Level Cell) system. In recent years, there is an increasing tendency to adopt the MLC method and the TLC method, which are capable of recording multiple bits of data in one memory cell. However, these data recording methods have the disadvantage that the number of times data can be rewritten decreases as the number of bits of data recorded in one memory cell increases. Therefore, in the MLC method and the TLC method, in order to extend the life of the NAND flash memory, it is particularly necessary to control the number of erasures to be suppressed.

As described above, due to the characteristics of the NAND flash memory, data is read in units of pages. Therefore, even if only one page in a block is degraded, the block will be refreshed. Therefore, data is copied even for normal pages in which the data is not degraded, resulting in wasteful processing. In addition, since the refresh process involves erasing data, there is a problem that the life of the NAND flash memory is shortened due to a small number of error pages.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory device capable of reducing the number of times data is erased and extending the life of the memory.

A semiconductor memory device according to the present invention comprises: a first memory unit having n blocks (where m and n are integers equal to or greater than 2) each containing m pages each composed of a plurality of cells; and a plurality of cells. and a control unit for controlling writing, reading, and erasing of data in the first storage unit and the second storage unit, wherein the control unit controls the first storage unit. error detection is performed by reading data page by page from the storage unit, and when a page including a data error is detected in the first storage unit in the error detection, error correction is performed on the data of the page including the error. When the data subjected to It is characterized by executing the refresh processing of the one block.

Further, the refresh method according to the present invention includes: a first storage unit having n blocks (m and n are integers equal to or greater than 2) each containing m pages each composed of a plurality of cells; and a control unit for controlling writing, reading, erasing, and error detection and correction processing of data, wherein the block refresh method is executed by a semiconductor memory device, wherein the first storage unit and performing error detection by reading data page by page from the memory unit, and if a page containing a data error is detected in the first storage unit in the error detection, error correction is performed on the data of the page containing the error. writing the applied data to the second storage unit; and when the data stored in a predetermined number of pages of one block in the first storage unit is written to the second storage unit and performing refresh processing of the one block.

According to the semiconductor memory device of the present invention, it is possible to extend the life of the memory by suppressing the number of times data is erased.

1 is a block diagram showing the configuration of a NAND flash control system of Example 1; FIG. 10 is a flowchart showing a processing routine for data inspection processing; FIG. 4 is a diagram schematically showing writing of data to a redundant memory; FIG. 4 is a flowchart showing a processing routine of refresh processing; FIG. 4 is a diagram schematically showing reading and writing of data in refresh processing; FIG. 11 is a block diagram showing the configuration of a NAND flash control system of Example 2; FIG. FIG. 10 is a diagram schematically showing writing of data to the second area of the NAND flash memory of Example 2; FIG. 10 is a diagram schematically showing writing of data to the second area of the NAND flash memory according to the modified example of the second embodiment;

Preferred embodiments of the present invention are described in detail below. In the following description of each embodiment and the attached drawings, substantially the same or equivalent parts are denoted by the same reference numerals.

FIG. 1 is a block diagram showing a schematic configuration of a NAND flash control system 100 according to the invention. A NAND flash control system 100 comprises a host computer 10 and a semiconductor memory device 11 .

The host computer 10 and the semiconductor memory device 11 are connected for communication with each other. The host computer 10 transmits commands to the semiconductor memory device 11 to instruct reading and writing of data. The semiconductor memory device 11 receives commands from the host computer 10 and executes data write and read operations accordingly.

The semiconductor memory device 11 has a controller 12 , a NAND flash memory 13 , a RAM (Random Access Memory) 14 and a redundant memory 15 .

The controller 12 is a control unit that controls the operation of the semiconductor memory device 11, and is composed of, for example, a CPU (Central Processing Unit). The controller 12 accesses the NAND flash memory 13, RAM 14 and redundant memory 15 and executes various data processing such as writing, reading and erasing of data.

The controller 12 also includes an ECC (Error Check and Correct) circuit and executes error detection and correction processing on data read from the NAND flash memory 13 . In this embodiment, for example, data retention failure due to physical deterioration of a gate insulating film (not shown) provided in the NAND flash memory 13, or so-called data deterioration due to charge transfer due to read disturbance, etc., is regarded as an error. detected.

The controller 12 also writes data to the redundant memory 15 and refreshes the NAND flash memory 13 based on the error detection result in the error detection and correction process.

The NAND flash memory 13 is a non-volatile semiconductor memory such as an EEPROM (Electrically Erasable Programmable Read-Only Memory). The NAND flash memory 13 has n blocks (n is an integer equal to or greater than 2) as a storage area. Each of the n blocks consists of m pages (m is an integer equal to or greater than 2). Each of the m pages consists of a plurality of cells. In this embodiment, data writing to each page is performed by the MLC (Multiple Level Cell) method in which 2-bit data is recorded in each cell.

Writing data to the NAND flash memory 13 and reading data from the NAND flash memory 13 are performed page by page. On the other hand, data stored in the NAND flash memory 13 is erased in block units. Data added with an error correction code ECC (Error Correction Code) is written in the NAND flash memory 13 .

The RAM 14 is a volatile memory that functions as cache memory in refresh processing of the NAND flash memory 13 . For example, in the refresh process, data read from the NAND flash memory 13 and redundant memory 15 are temporarily stored in the RAM 14 . Then, the data is read from the RAM 14 and written to the NAND flash memory 13 .

The redundant memory 15 is a nonvolatile semiconductor memory provided separately from the NAND flash memory 13 in the semiconductor memory device 11 . Redundant memory 15 has multiple pages each of which consists of multiple cells. Writing data to the redundant memory 15 is performed by the SLC (Single Level Cell) method in which 1-bit data is recorded for each cell.

In this embodiment, when a page whose data deterioration has progressed is detected by error detection, the data of the page is recorded in the redundant memory 15 through error correction. Thereafter, until the refresh processing of the block is performed, the data is read from the redundant memory 15 when reading the data of the page. Note that when the block is refreshed, data corresponding to the block is erased from the redundant memory 15 .

Next, processing operations of error detection processing and refresh processing of the semiconductor memory device 11 according to the present embodiment will be described with reference to the flow charts of FIGS. 2 and 4. FIG.

The controller 12 executes error detection processing for the NAND flash memory 13, for example, immediately after the semiconductor memory device 11 is powered on. The error detection processing of this embodiment is error detection and correction processing using an error correction code ECC, and is performed page by page for each of n blocks. In the following description, the n blocks of the NAND flash memory 13 are referred to as the 1st block to the nth block, and the m pages are referred to as the 1st page to the mth page.

The controller 12 sets the value of "k" indicating a block to be subjected to error detection among n blocks of the NAND flash memory 13 to k=1 (STEP 101).

The controller 12 executes data inspection on the k-th block of the NAND flash memory 13 (STEP 102). Specifically, data is sequentially read from each of the 1st to m-th pages, and error detection and correction is performed on the read data, thereby detecting the presence or absence of deterioration in the data of each page.

The controller 12 determines whether or not a page with degraded data is found as a result of data inspection (error detection and correction processing) (STEP 103).

If it is determined that a page with deteriorated data has been found (STEP 103: Yes), the controller 12 writes the error-corrected data of the page in the NAND flash memory 13 to the redundant memory 15 (STEP 104). On the other hand, if it is not determined that a page with degraded data has been found (STEP103: No), the process proceeds to STEP107.

FIG. 3 is a diagram schematically showing writing of data to the redundant memory performed in STEP104. For example, when data deterioration is detected in "page 1" of "block 2" of the NAND flash memory 13, "data 2" which is the data recorded in page 1 of block 2 (indicated by hatching in FIG. 4) is detected. , 1” are written into the redundant memory 15 after error correction.

Referring to FIG. 2 again, the controller 12 determines whether or not the number of pages of data of the k-th block equal to or greater than the threshold is stored in the redundant memory 15 (that is, whether or not the data of the k-th block equal to or greater than a predetermined amount of data is stored in the redundant memory 15). (STEP 105).

When it is determined that the number of pages of data of the k-th block or more is stored in the redundant memory 15 (STEP 105: Yes), the controller 12 executes refresh processing of the NAND flash memory 13 (STEP 106).

FIG. 4 is a flowchart showing a processing routine for refresh processing. First, the controller 12 erases data written in a block to be used as a data write destination in the refresh process (hereinafter referred to as a refresh destination block) in order to set it as an empty block (STEP 201).

The controller 12 sets the value of "j", which indicates the page to be moved in the refresh process among the m pages of the k-th block of the NAND flash memory 13, to j=1 (STEP 202).

The controller 12 determines whether or not the j-th page data is stored in the redundant memory 15, that is, whether or not it is the data written in the redundant memory 15 in STEP 104 of the flowchart of FIG. 2 (STEP 203).

When determining that the j-th page data is stored in the redundant memory 15 (STEP 203: Yes), the controller 12 reads the j-th page data from the redundant memory 15 (STEP 204).

On the other hand, if it is determined that the j-th page data is not stored in the redundant memory 15 (STEP 203: No), the controller 12 reads the j-th page data from the j-th page of the k-th block of the NAND flash memory 13 ( STEP 205).

The controller 12 writes the j-th page data read in STEP204 or STEP205 to the memory area of the refresh destination block of the NAND flash memory 13 (STEP206).

FIG. 5 is a diagram schematically showing reading and writing of data performed in STEP204-206. Here, in the error detection processing (see STEPs 102 to 104 in FIG. 2) targeting "block 2" of the NAND flash memory 13, a data error is detected in "pages 1, 3, 4, 5 and m". A case is shown as an example.

When a data error is detected in pages 1, 3, 4, 5 and m, the data stored in the page is copied to redundant memory 15 after error correction. Therefore, as shown in FIG. 5, the redundant memory 15 stores "data 2, 1", " Data 2, 3", "Data 2, 4", "Data 2, 5" and "Data 2, m" are stored. Therefore, the controller 12 reads these data and writes them to "block X" which is the refresh destination block.

On the other hand, no data error is detected in the data written in pages other than pages 1, 3, 4, 5 and m of block 2, so the corresponding data is not stored in redundant memory 15. FIG. Therefore, the controller 12 reads these data from the block 2 of the NAND flash memory 13 and writes them to the block X which is the refresh destination block.

As a result, data 2,1, data 2,2, data 2,3, .

Referring to FIG. 4 again, the controller 12 determines whether or not the series of processes from STEP203 to STEP206 has been performed up to the m-th page of the k-th block (STEP207).

If it is determined that the series of processes has not been performed up to the m-th page (STEP 207: No), the value of j is incremented by "+1" (STEP 208), and the process returns to STEP 203.

On the other hand, if it is determined that the series of processes has been performed up to the m-th page (STEP 207: Yes), the data of the k-th block recorded in the redundant memory 15 is erased (STEP 209), and the refresh process ends.

Referring to FIG. 2 again, if it is not determined in STEP 103 that a page with deteriorated data has been found (STEP 103: No), then in STEP 105 the redundant memory 15 stores data of the number of pages equal to or greater than the threshold value of the k-th block. If it is determined that there is no (STEP 105: No), and if the refresh processing of the k-th block in STEP 106 is completed, the controller 12 determines whether or not the series of processing of STEP 102 to 106 has been performed up to the n-th block. (STEP 107).

If it is determined that the series of processes has not been performed up to the n-th block (STEP107: No), the value of k is incremented by "+1" (STEP108), and the process returns to STEP102.

On the other hand, when it is determined that the series of processes has been performed up to the n-th block (STEP 107: Yes), the error detection process for the NAND flash memory 13 ends.

As described above, in the semiconductor memory device 11 of this embodiment, data is read from the NAND flash memory 13, error detection and correction are performed, and the data of the page in which the error is detected is written to the redundant memory 15. FIG. Then, when data of a certain number of pages or more in a specific block are recorded in the redundant memory 15, refresh processing of the block is executed.

According to the semiconductor memory device 11 of the present embodiment, when the number of pages in which data deterioration has been detected reaches a predetermined number or more per block, the block is refreshed. The number of times data is erased can be reduced compared to the case where refresh processing is performed each time it is found. Therefore, the life of the NAND flash memory 13 can be extended.

Next, Example 2 of the present invention will be described. FIG. 6 is a block diagram showing a schematic configuration of the NAND flash control system 200 of this embodiment. A NAND flash control system 200 comprises a host computer 20 and a semiconductor memory device 21 .

A semiconductor memory device 21 has a controller 12 , a RAM 14 and a NAND flash memory 23 .

The NAND flash memory 23 of this embodiment is composed of a first area made up of a plurality of blocks and a second area made up of different blocks.

The first area is a memory area used for normal data writing to the NAND flash memory 23 . The first area consists of p blocks (p is a natural number that satisfies p<n), each of which consists of m pages. In this embodiment, data is written to the first area by the MLC method.

The second area is a memory area for writing data of the page when a page whose data is degraded is detected in the first area. That is, in this embodiment, instead of the redundant memory 15 (see FIG. 1) of the first embodiment, a second area used as a redundant area is provided in the same chip as a first area used as a normal memory area. is provided. The second area consists of q blocks (q is a natural number satisfying q=n−p), each of which consists of r pages (r is a natural number satisfying r<m). In this embodiment, data is written to the second area by the SLC method.

The controller 12 performs error detection and correction processing for each page of p blocks in the first area of the NAND flash memory 13, and detects the presence or absence of data deterioration in each page. When a page with degraded data is found, the controller 12 writes the error-corrected data of the page to the second area of the NAND flash memory 13 .

FIG. 7 is a diagram schematically showing writing of data to the second area. For example, in the block 2 of the first area of the NAND flash memory 13, when data deterioration is detected in pages 1, 3 and 4, the data recorded in these pages "data 2, 1", "Data 2, 3" and "Data 2, 4" are written to the second area of the NAND flash memory 13 through error correction. Thereafter, until the refresh processing of the block is performed, when reading the data of the page, the data is read from the second area. Then, when the refresh processing of the blocks in the first area is performed, the data corresponding to the blocks are erased from the second area.

Note that management and control are performed such that page data of one block of the first area is written into one block of the second area. That is, data recorded in the same block in the first area is written in the same block in the second area. Data recorded in different blocks in the first area are written in different blocks in the second area.

When data is written to all pages (that is, r pages) of one block of the second area, the controller 12 controls the block of the first area including the page that is the original recording location of the data. Execute refresh processing.

In the refresh process, the controller 12 writes the data read from the second area to the refresh destination block for the data recorded in the second area (that is, the data of the page in which data deterioration was found). . On the other hand, the controller 12 writes the data read from the first area to the refresh destination block for the data not recorded in the second area (that is, the data of the page for which deterioration of data was not found).

As described above, in the semiconductor memory device 21 of the present embodiment, the NAND flash memory 13 is provided with the second area in which data is written by the SLC method, and the data of the page in which the data error is detected is transferred to the save memory. Use as Since the SLC method allows data to be erased more times than the MLC method and the TLC method, the life of the NAND flash memory 13 is shortened even if it is used as a backup memory on the premise that data is repeatedly erased. can be suppressed. Therefore, according to the semiconductor memory device 21 of this embodiment, it is possible to extend the life of the NAND flash memory 13 without separately providing a redundant memory as in the first embodiment.

It should be noted that the present invention is not limited to those shown in the above embodiments. For example, in the above embodiment, an example has been described in which error detection processing is sequentially performed on each page of the first to n-th blocks of the NAND flash memory 13 immediately after the power of the semiconductor memory device 11 is turned on. However, the timing of performing error detection processing is not limited to this. For example, when a certain block is accessed, error detection processing may be performed only for that block. In this case, the processing of STEPs 103 to 106 in the flowchart of FIG. 2 (that is, writing data to the redundant memory 15 and refresh processing) is executed only for the block concerned.

Further, even when the error detection process is performed immediately after the power is turned on, it is not necessary to perform the error detection process for all blocks in one error detection process. For example, the error detection process may be performed on k blocks (k is a natural number less than n) each time the power is turned on, and the target blocks may be sequentially transitioned each time the power is turned on.

In addition, in the second embodiment, the NAND flash memory 23 has a first area in which normal data is written, and a second area in which, when a page containing an error is detected, data of the page is written. , has been described. However, the division into the first area and the second area may not be made in advance. That is, in a normal state, the entire memory area of the NAND flash memory 23 is used as the first area, and when data deterioration is detected, an empty block at that time is used as the second area. may be configured to

Further, in the second embodiment, the case where data is written to the first area by the MLC method and data is written to the second area by the SLC method has been described as an example. However, the data recording method is not limited to this. For example, data may be recorded in the first area by the TLC (Triple Level Cell) method, and data may be recorded in the second area by the MLC method. However, the second area is an area used as a memory for saving the page data of the first area in which a data error has been detected, and is a storage area that is assumed to be erased repeatedly. Therefore, it is desirable to adopt a data recording method that allows more erasable times than in the first area.

Also, in the above embodiment, the case where the data written in the refresh destination block is erased at the first stage of the refresh process (STEP 201 in FIG. 4) has been described as an example. However, the timing of erasing the data in the refresh destination block is not limited to this, as long as the state in which no data is recorded in the refresh destination block is realized at the stage of performing the refresh processing. For example, a block that has become an empty block in advance may be used as a refresh destination block. Alternatively, a certain number of empty blocks may be always secured by erasing the blocks in which the original data were recorded after performing the refresh process.

Also, in the second embodiment, the case where the refresh process is performed when data is stored in all pages of one block in the second area has been described as an example. However, the block of the second area, which is the destination (save destination) of the data at the time of error detection, may be directly used as the block of the data copy destination without performing the refresh process. For example, as shown in FIG. 8, when a page containing degraded data is found, the data of the page is sequentially written into the blocks of the second area so that all the pages of one block of the second area have data. If it is stored, the data is sequentially written to blocks adjacent to the one block. By recording data over a plurality of blocks in the second area, finally all pages of data in one block in the first area can be moved to the second area. By managing data corresponding to one block in the first area with a plurality of blocks in the second area, rewriting of data can be completed without performing refresh processing. Therefore, since there is no need to erase data associated with refresh processing, the life of the NAND flash memory can be extended.

Also, the semiconductor memory device of the present invention can be applied to other types of non-volatile memory other than NAND flash memory. For example, NAND flash memory is premised on writing and reading data page by page and erasing data block by block. It is also possible to apply the present invention to a static memory. Even in such a non-volatile memory, by executing the refresh process when the number of pages containing errors reaches a certain level or more, the refresh process can be concentrated on fewer occasions than when the refresh process is executed each time. processing can be performed.

100, 200 NAND flash control system 10 host computer 11, 21 semiconductor memory device 12 controller 13 NAND flash memory 14 RAM
15 redundant memory

Claims (10)

a first storage unit having n blocks (where m and n are integers equal to or greater than 2) each containing m pages each consisting of a plurality of cells;
a second storage unit having a plurality of cells;
a control unit that controls writing, reading, and erasing of data in the first storage unit and the second storage unit;
has
The control unit reads data page by page from the first storage unit and performs error detection,
In the error detection, when a page including a data error is detected in the first storage unit, the data of the page including the error is error-corrected and written to the second storage unit;
When data stored in a predetermined number of pages in one block of the first storage unit is written to the second storage unit, the one block is refreshed. semiconductor memory device. In the refresh process, the control unit converts the data written in the second storage unit out of the data stored in the m pages of the one block into one of the first storage units. 2. An empty block is written, and data other than the data written in the second storage unit is read from the one block of the first storage unit and written into the one empty block. 2. The semiconductor memory device according to . The control unit generates the one empty block by erasing data recorded in one of blocks other than the one block in the first storage unit. 3. The semiconductor memory device according to claim 2. The control unit writes data to the first storage unit by a first data recording method, which is a method of recording multiple bits of data for each cell,
4. The method according to any one of claims 1 to 3, wherein data is written in said second storage unit by a second data recording method in which the number of bits of data recorded in each cell is smaller than that in said first data recording method. 1. A semiconductor memory device according to claim 1. The first data recording method is an MLC (Multiple Level Cell) method or a TLC (Triple Level Cell) method,
5. The semiconductor memory device according to claim 4, wherein said second data recording method is an SLC (Single Level Cell) method. The first storage unit is composed of a first nonvolatile memory in which data is recorded by the first data recording method,
6. The semiconductor memory device according to claim 4, wherein said second storage section comprises a second non-volatile memory in which data is recorded by said second data recording method. The first storage unit is configured as a block group consisting of n blocks in one nonvolatile memory,
6. The semiconductor memory device according to any one of claims 1 to 5, wherein said second storage unit is composed of blocks different from said n blocks in said one nonvolatile memory. . a first storage section having n blocks (where m and n are integers equal to or greater than 2) each containing m pages each consisting of a plurality of cells; a second storage section having a plurality of cells; A block refresh method executed by a semiconductor memory device having a control unit for controlling writing, reading, erasing, and error detection and correction processing of
a step of reading data page by page from the first storage unit and performing error detection;
when a page including a data error is detected in the first storage unit in the error detection, writing data obtained by performing error correction on the data of the page including the error in the second storage unit;
a step of performing refresh processing of the one block when data stored in a predetermined number of pages of one block of the first storage unit is written to the second storage unit;
A refresh method, comprising: The step of executing the refresh process includes:
a step of writing the data written in the second storage unit, among the data stored in m pages of the one block, into one free block of the first storage unit;
Of the data stored in the m pages of the one block, data other than the data written in the second storage unit is read out from the one block of the first storage unit and read out from the one block. writing to a free block in
9. The refreshing method according to claim 8, comprising: 3. The step of generating the one empty block by erasing data recorded in one of blocks other than the one block in the first storage unit. 9. The refresh method according to 9.

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