JP7135185B2 - Information processing system - Google Patents

Description

Embodiments of the present invention relate to information processing systems.

In the recent 3-bit/cell NAND memory, in order to avoid mutual interference between cells, all bits to be stored in a first memory cell are written at the same time, and then all bits are similarly written to adjacent cells. are written at the same time, and then all Bits are rewritten (programmed) again in the first memory cell. However, using this method requires the data to be retained on the controller side for rewriting.

1-3-3 coding is known as a method of programming all bits simultaneously. This method is a coding that distributes 7 threshold voltage regions between 8 threshold voltage regions of 3 bits/cell to 1, 3, and 3, respectively.

However, recent NAND memories are three-dimensional, and the amount of write buffer required increases, which increases the cost of memory controllers. For this reason, even in three-dimensional nonvolatile memories, it is desired to reduce the write buffer capacity of the memory controller while suppressing the mutual interference between cells and the uneven bit error rate between pages.

JP 2015-195071 A U.S. Pat. No. 9,230,664

The problem to be solved by the present invention is to reduce the write buffer amount of the memory controller while suppressing mutual interference between cells.

According to an embodiment, an information processing system is provided. The information processing system includes a host and a memory system. The memory system has a non-volatile memory and a memory controller. The nonvolatile memory includes a first threshold region indicating an erased state in which data is erased, and a second threshold region indicating a written state in which data is written with a voltage level higher than that of the first threshold region. 16 threshold regions including the 16th threshold region have a plurality of memory cells capable of storing 4-bit data represented by the first to fourth bits. The memory controller causes the nonvolatile memory to execute a first program to write data of the first bit and the second bit in response to a write request received from the host, and then writes the data of the third bit and the second bit. A second program for writing 4-bit data is caused to the non-volatile memory. The memory controller comprises: a seventeenth threshold region indicating an erased state in which data is erased according to the data of the first bit and the second bit; 18th to 20th threshold regions indicating a write state in which data is written with a voltage level higher than that of the threshold region 17; to the non-volatile memory. The memory controller sets the threshold region of the memory cell to any one of the 17th to 20th threshold regions according to the data of the 3rd bit and the 4th bit. The second programming is configured to cause the non-volatile memory to be in any one of the first to sixteenth threshold regions from the region. The nth threshold region has a higher voltage level than the (n-1)th threshold region (n is a natural number of 2 or more and 16 or less). The kth threshold region has a higher voltage level than the (k-1)th threshold region (k is a natural number between 18 and 20). The memory controller converts the threshold region in the memory cell from the 17th threshold region to the 1st to 16th threshold values according to the data of the 3rd bit and the 4th bit. When the second programming is performed on the non-volatile memory so as to be any threshold value region among the regions, four twenty-first threshold regions among the first to sixteenth threshold regions It is configured to cause the non-volatile memory to perform the second programming to be in any one of the threshold regions. The memory controller converts the threshold region in the memory cell from the 18th threshold region to the 1st to 16th threshold values according to the data of the 3rd bit and the 4th bit. When the second programming is performed on the non-volatile memory so as to be any threshold value region among the regions, four 22nd threshold regions among the first to sixteenth threshold regions It is configured to cause the non-volatile memory to perform the second programming to be in any one of the threshold regions. The memory controller converts the threshold region in the memory cell from the 19th threshold region to the 1st to 16th threshold values according to the data of the 3rd bit and the 4th bit. When the second programming is performed on the non-volatile memory so as to be any threshold value region among the regions, four twenty-third threshold regions among the first to sixteenth threshold regions It is configured to cause the non-volatile memory to perform the second programming to be in any one of the threshold regions. The memory controller converts the threshold region in the memory cell from the twentieth threshold region to the first to sixteenth threshold values according to the data of the third bit and the fourth bit. When the second programming is performed on the non-volatile memory so as to be any threshold value region among the regions, the four twenty-fourth threshold regions among the first to sixteenth threshold regions It is configured to cause the non-volatile memory to perform the second programming to be in any one of the threshold regions. The threshold regions of the four twenty-third threshold regions and the threshold regions of the four twenty-fourth threshold regions are all of the four twenty-first threshold regions , the voltage level is higher than any of the threshold regions of The threshold regions of the four twenty-third threshold regions and the threshold regions of the four twenty-fourth threshold regions are all of the four twenty-second threshold regions , the voltage level is higher than any of the threshold regions of The four twenty-second threshold regions are four consecutive threshold regions among the first to sixteenth threshold regions. The four twenty-fourth threshold regions are four consecutive threshold regions among the first to sixteenth threshold regions. The four twenty-first threshold regions are four consecutive threshold regions among the first to sixteenth threshold regions. The four twenty-third threshold regions are four consecutive threshold regions among the first to sixteenth threshold regions. Any threshold region of the four twenty-second threshold regions has a higher voltage level than any threshold region of the four twenty-first threshold regions. Any of the four twenty-fourth threshold regions has a higher voltage level than any one of the four twenty-third threshold regions. the number of first boundaries used to determine the value of the data of the first bit among 15 boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions; The number of second boundaries used to determine the value of the data of the second bit, the number of third boundaries used to determine the value of the data of the third bit, and the value of the data of the fourth bit are 1, 2, 6, 6 in order.

FIG. 1 is a block diagram illustrating a configuration example of a storage device according to a first embodiment; FIG. 2 is a block diagram showing a configuration example of a nonvolatile memory according to the first embodiment. FIG. 3 is a diagram showing a block configuration example of a memory cell array having a three-dimensional structure. FIG. 4 is a cross-sectional view of a partial region of a memory cell array of a NAND memory with a three-dimensional structure. FIG. 5 is a diagram showing an example of threshold regions according to the first embodiment. FIG. 6 is a diagram illustrating data coding in the first embodiment. FIG. 7 is a diagram showing a threshold distribution after programming in the first embodiment. FIG. 8A is a diagram showing a first example of program order of the first embodiment. FIG. 8B is a diagram showing a second example of the program order of the first embodiment. FIG. 8C is a diagram showing a third example of program order of the first embodiment. FIG. 9A is a flowchart illustrating an example of a procedure for writing an entire block according to the first embodiment; FIG. 9B is a sub-flowchart showing a write procedure in the 1st stage according to the first embodiment. FIG. 9C is a sub-flowchart showing the write procedure in the 2nd stage according to the first embodiment. FIG. 9D is a sub-flowchart showing a modification of the write procedure in the 2nd stage according to the first embodiment; FIG. 9E is a diagram for explaining majority processing of the results of reading a plurality of times. FIG. 10A is a diagram for explaining the amount of buffer data in the LM-Foggy-Fine program that employs 1-3-3 coding. FIG. 10B is a diagram for explaining the amount of buffer data in the program of the first embodiment; FIG. 11 is a diagram showing an example of a sequence of external program commands according to the first embodiment. FIG. 12A is a flow chart showing a processing procedure of page reading in a word line for which programming has been completed up to the 1st stage in the memory device according to the first embodiment. FIG. 12B is a flow chart showing a processing procedure of page reading on a word line for which programming has been completed up to the 2nd stage in the memory device according to the first embodiment. FIG. 13 is a diagram showing an example of a sequence of external read commands according to the first embodiment. FIG. 14A is a flow chart showing a procedure for writing an entire block according to the second embodiment. FIG. 14B is a sub-flowchart showing write procedures in the 1st stage and the 2nd stage according to the second embodiment. FIG. 15 is a diagram showing an example of a sequence of external program commands according to the second embodiment. FIG. 16 is a diagram for explaining data destruction caused by power shutdown. FIG. 17 is a diagram for explaining the 2nd stage program according to the third embodiment. FIG. 18 is a flow chart showing a write procedure in the 2nd stage according to the third embodiment. FIG. 19 is a diagram for explaining a program modification of the 2nd stage according to the third embodiment. FIG. 20 is a diagram showing another example of 1-3-3 data coding. FIG. 21 is a diagram showing the threshold distribution after programming in the fourth embodiment. FIG. 22A is a sub-flowchart showing a write procedure in the 1st stage according to the fourth embodiment. FIG. 22B is a sub-flowchart showing the write procedure in the 2nd stage according to the fourth embodiment. FIG. 22C is a sub-flowchart showing a modification of the write procedure in the 2nd stage according to the fourth embodiment. FIG. 23 is a diagram showing an example of a sequence of external program commands according to the fourth embodiment. FIG. 24A is a flow chart showing a processing procedure of page reading on a word line for which programming has been completed up to the 1st stage in the memory device according to the fourth embodiment. FIG. 24B is a flowchart showing a processing procedure of page reading in a word line for which programming has been completed up to the 2nd stage in the memory device according to the fourth embodiment. FIG. 25 is a diagram showing an example of a sequence of external read commands according to the fourth embodiment. FIG. 26 is a diagram for explaining the configuration of a flag cell. FIG. 27A is a diagram for explaining programming of flag cells according to the fifth embodiment. FIG. 27B is a diagram for explaining programming of dummy cells according to the fifth embodiment. FIG. 28 is a flow chart showing a write procedure in the 2nd stage according to the fifth embodiment. FIG. 29 is a flowchart showing a page read processing procedure according to the fifth embodiment. FIG. 30 is a diagram showing an example of a sequence of external read commands according to the fifth embodiment. FIG. 31 is a diagram showing an example of threshold regions according to the sixth embodiment. FIG. 32 is a diagram of a first example showing a threshold distribution after programming in the sixth embodiment. FIG. 33 shows data coding corresponding to the threshold distribution shown in FIG. FIG. 34 is a diagram of a second example showing the threshold distribution after programming in the sixth embodiment. FIG. 35 shows data coding corresponding to the threshold distribution shown in FIG. FIG. 36 is a diagram of a third example showing the threshold distribution after programming in the sixth embodiment. FIG. 37 shows data coding corresponding to the threshold distribution shown in FIG.

A memory system and a writing method according to embodiments will be described in detail below with reference to the accompanying drawings. In addition, the present invention is not limited by these embodiments.

(First embodiment)
FIG. 1 is a block diagram illustrating a configuration example of a storage device according to a first embodiment; The storage device of this embodiment comprises a memory controller 1 and a nonvolatile memory 2 . The storage device is connectable with the host. A host is, for example, an electronic device such as a personal computer or a mobile terminal.

The nonvolatile memory 2 is a memory that stores data in a nonvolatile manner, and includes, for example, a NAND memory (NAND flash memory). In the present embodiment, the nonvolatile memory 2 is described as a NAND memory having memory cells each capable of storing 3 bits, that is, a 3-bit/cell (TLC: Triple Level Cell) NAND memory. The nonvolatile memory 2 is three-dimensional.

The memory controller 1 controls writing of data to the nonvolatile memory 2 according to write commands from the host. Also, the memory controller 1 controls reading of data from the nonvolatile memory 2 in accordance with a read command from the host. The memory controller 1 includes a RAM (Random Access Memory) 11 , a processor 12 , a host interface 13 , an ECC (Error Check and Correct) circuit 14 and a memory interface 15 . RAM 11 , processor 12 , host interface 13 , ECC circuit 14 and memory interface 15 are connected to each other via internal bus 16 .

The host interface 13 outputs commands, user data (write data), etc. received from the host to the internal bus 16 . The host interface 13 also transmits user data read from the nonvolatile memory 2, responses from the processor 12, and the like to the host.

The memory interface 15 controls the process of writing user data and the like to the nonvolatile memory 2 and the process of reading from the nonvolatile memory 2 based on instructions from the processor 12 .

The processor 12 comprehensively controls the memory controller 1 . The processor 12 is, for example, a CPU (Central Processing Unit), an MPU (Micro Processing Unit), or the like. When the processor 12 receives a command from the host via the host interface 13, the processor 12 performs control according to the command. For example, processor 12 instructs memory interface 15 to write user data and parity to nonvolatile memory 2 in accordance with a command from the host. The processor 12 also instructs the memory interface 15 to read user data and parity from the nonvolatile memory 2 according to a command from the host.

The processor 12 determines a storage area (memory area) on the nonvolatile memory 2 for user data accumulated in the RAM 11 . User data is stored in RAM 11 via internal bus 16 . The processor 12 determines a memory area for page-based data (page data) that is a writing unit. In this specification, user data stored in one page of the nonvolatile memory 2 is defined as unit data. The unit data is generally encoded and stored in the nonvolatile memory 2 as codewords. Encoding is not essential in this embodiment. The memory controller 1 may store unit data in the non-volatile memory 2 without encoding, but FIG. 1 shows a configuration in which encoding is performed as a configuration example. If the memory controller 1 does not encode, the page data will match the unit data. Also, one codeword may be generated based on one unit data, or one codeword may be generated based on divided data obtained by dividing unit data. Also, one codeword may be generated using a plurality of unit data.

The processor 12 determines a memory area of the non-volatile memory 2 to write to for each unit data. Physical addresses are assigned to the memory areas of the nonvolatile memory 2 . The processor 12 manages the memory area to which unit data is written using physical addresses. The processor 12 designates the determined memory area (physical address) and instructs the memory interface 15 to write the user data into the nonvolatile memory 2 . The processor 12 manages correspondence between logical addresses of user data (logical addresses managed by the host) and physical addresses. When the processor 12 receives a read command including a logical address from the host, the processor 12 identifies a physical address corresponding to the logical address, designates the physical address, and instructs the memory interface 15 to read user data.

In this specification, memory cells commonly connected to one word line are defined as a memory cell group MG. In this embodiment, the nonvolatile memory 2 is a 3-bit/cell NAND memory, and one memory cell group MG corresponds to 3 pages. The 3 bits of each memory cell respectively correspond to these 3 pages. In this embodiment, these three pages are called a Lower page (first page), a Middle page (second page), and an Upper page (third page).

The ECC circuit 14 encodes the user data stored in the RAM 11 to generate codewords. The ECC circuit 14 also decodes code words read from the nonvolatile memory 2 .

The RAM 11 temporarily stores user data received from the host until it is stored in the nonvolatile memory 2, and temporarily stores data read from the nonvolatile memory 2 until it is transmitted to the host. The RAM 11 is, for example, a general-purpose memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory).

FIG. 1 shows a configuration example in which the memory controller 1 includes the ECC circuit 14 and the memory interface 15, respectively. However, ECC circuit 14 may be built into memory interface 15 . Also, the ECC circuit 14 may be incorporated in the nonvolatile memory 2 .

When receiving a write request from the host, the storage device (memory system) operates as follows. The processor 12 causes the RAM 11 to temporarily store the write data. The processor 12 reads data stored in the RAM 11 and inputs it to the ECC circuit 14 . ECC circuit 14 encodes the input data and inputs a codeword to memory interface 15 . The memory interface 15 writes the input codeword to the nonvolatile memory 2 .

When receiving a read request from the host, the storage device operates as follows. The memory interface 15 inputs the code word read from the nonvolatile memory 2 to the ECC circuit 14 . The ECC circuit 14 decodes the input codeword and stores the decoded data in the RAM 11 . Processor 12 transmits data stored in RAM 11 to the host via host interface 13 . A plurality of chips may be connected to the nonvolatile memory 2, and the nonvolatile memory 2 and the memory interface 15 may be connected by through vias (TSV).

FIG. 2 is a block diagram showing a configuration example of the nonvolatile memory of this embodiment. The nonvolatile memory 2 includes a NAND I/O interface 21 , a control section 22 , a NAND memory cell array (memory cell section) 23 and a page buffer 24 . The nonvolatile memory 2 is composed of, for example, a one-chip semiconductor substrate (for example, a silicon substrate).

The control unit 22 controls operations of the nonvolatile memory 2 based on commands and the like input from the memory controller 1 via the NAND I/O interface 21 . Specifically, when a write request is input, the control unit 22 controls to write the requested data to a specified address on the NAND memory cell array 23 . Further, when a read request is input, the control unit 22 controls to read the data requested to be read from the NAND memory cell array 23 and output the read data to the memory controller 1 via the NAND I/O interface 21 . The page buffer 24 is a buffer that temporarily stores data input from the memory controller 1 when writing to the NAND memory cell array 23 and temporarily stores data read from the NAND memory cell array 23 .

FIG. 3 is a diagram showing a block configuration example of a memory cell array having a three-dimensional structure. FIG. 3 shows one block BLK among a plurality of blocks forming a three-dimensional memory cell array. Other blocks in the memory cell array have the same configuration as in FIG. Note that this embodiment can also be applied to a memory cell having a two-dimensional structure.

As shown, block BLK includes, for example, four finger FNGs (FNG0-FNG3). Each finger FNG also includes multiple NAND strings NS. Each NAND string NS includes, for example, eight memory cell transistors MT (MT0 to MT7) and select transistors ST1 and ST2. Note that the number of memory cell transistors MT is not limited to eight. The memory cell transistor MT is arranged between the selection transistors ST1 and ST2 such that its current path is connected in series. The current path of the memory cell transistor MT7 at one end of this series connection is connected to one end of the current path of the selection transistor ST1, and the current path of the memory cell transistor MT0 at the other end is connected to one end of the current path of the selection transistor ST2. It is connected.

Gates of select transistors ST1 of fingers FNG0 to FNG3 are commonly connected to select gate lines SGD0 to SGD3, respectively. On the other hand, the gates of the select transistors ST2 are commonly connected to the same select gate line SGS among a plurality of fingers FNG. Control gates of memory cell transistors MT0 to MT7 in the same block BLK are commonly connected to word lines WL0 to WL7, respectively. That is, the word lines WL0 to WL7 and the select gate line SGS are commonly connected among the plurality of fingers FNG0 to FNG3 within the same block BLK, whereas the select gate line SGD is connected within the same block BLK. are also independent for each of the fingers FNG0 to FNG3.

Word lines WL0 to WL7 are connected to the control gate electrodes of the memory cell transistors MT0 to MT7 constituting the NAND string NS, respectively. are commonly connected by the same word line WLi (i=0 to n). That is, the control gate electrodes of the memory cell transistors MTi in the same row within the block BLK are connected to the same word line WLi. Note that the NAND string NS may be referred to as a string in the following description.

Each memory cell is connected to a word line WLi and also connected to a bit line. Each memory cell can be identified by an address that identifies the word line WLi and the select gate lines SGD0 to SGD3 and an address that identifies the bit line. As described above, data in memory cells (memory cell transistors MT) in the same block BLK are collectively erased. On the other hand, data reading and writing are performed in units of physical sectors MS. One physical sector MS includes a plurality of memory cells connected to one word line WLi and belonging to one finger FNG.

During read and program operations, one word line WLi and one select gate line SGD are selected according to the physical address, and the physical sector MS is selected.

FIG. 4 is a cross-sectional view of a partial region of a memory cell array of a NAND memory with a three-dimensional structure. As shown in FIG. 4, a plurality of NAND strings NS are formed on a p-type well region (P-well). That is, on the p-type well region, a plurality of wiring layers 333 functioning as select gate lines SGS, a plurality of wiring layers 332 functioning as word lines WLi, and a plurality of wiring layers 331 functioning as select gate lines SGD are formed. It is

A memory hole 334 is formed through these wiring layers 333, 332 and 331 to reach the p-type well region. A block insulating film 335 , a charge storage layer 336 , and a gate insulating film 337 are sequentially formed on the side surface of the memory hole 334 , and a conductive film 338 is embedded in the memory hole 334 . The conductive film 338 functions as a current path for the NAND string NS, and is a region in which channels are formed when the memory cell transistor MT and the select transistors ST1 and ST2 operate.

In each NAND string NS, a select transistor ST2, a plurality of memory cell transistors MT, and a select transistor ST1 are sequentially stacked on the p-type well region. A wiring layer functioning as a bit line BL is formed on the upper end of the conductive film 338 .

Furthermore, an n + -type impurity diffusion layer and a p + -type impurity diffusion layer are formed in the surface of the p-type well region. A contact plug 340 is formed on the n + -type impurity diffusion layer, and a wiring layer functioning as the source line SL is formed on the contact plug 340 . A contact plug 339 is formed on the p + -type impurity diffusion layer, and a wiring layer functioning as a well wiring CPWELL is formed on the contact plug 339 .

A plurality of configurations shown in FIG. 4 are arranged in the depth direction of the page of FIG. 4, and one finger FNG is formed by a set of a plurality of NAND strings arranged in a line in the depth direction.

FIG. 5 is a diagram showing an example of threshold regions according to the first embodiment. FIG. 5 shows a threshold distribution example of the nonvolatile memory 2 of 3 bits/cell. In the nonvolatile memory 2, information is stored by the amount of charge stored in the floating gate of the memory cell. Each memory cell has a threshold voltage corresponding to the amount of charge. A plurality of data values to be stored in the memory cell are associated with a plurality of threshold voltage regions (threshold regions).

Eight distributions (mountain-shaped) indicated by Er, A, B, C, D, E, F, and G in FIG. 5 indicate respective threshold distributions within the eight threshold regions. Thus, each memory cell has a threshold distribution partitioned by seven boundaries. The horizontal axis of FIG. 5 indicates the threshold voltage, and the vertical axis indicates the distribution of the number of memory cells (the number of cells).

In the present embodiment, the region where the threshold voltage is Vr1 or lower is called region Er, the region where the threshold voltage is higher than Vr1 and lower than or equal to Vr2 is called region A, and the threshold voltage is higher than Vr2 and lower than or equal to Vr3. A region where the threshold voltage is higher than Vr3 and lower than or equal to Vr4 is called a region C. FIG. Further, in the present embodiment, a region where the threshold voltage is greater than Vr4 and less than or equal to Vr5 is called region D, and a region where the threshold voltage is greater than Vr5 and less than or equal to Vr6 is called region E. A region where the threshold voltage is greater than Vr6 and equal to or less than Vr7 is called region F, and a region where the threshold voltage is greater than Vr7 is called region G. FIG.

Also, the threshold distributions corresponding to the regions Er, A, B, C, D, E, F, and G are the distributions Er, A, B, C, D, E, F, and G (first to eighth distribution). Vr1 to Vr7 are threshold voltages that serve as boundaries between regions.

In the nonvolatile memory 2, a plurality of data values are associated with a plurality of threshold regions (that is, threshold distributions) of memory cells. This correspondence is called data coding. This data coding is determined in advance, and charges are injected into the memory cells so as to fall within a threshold region corresponding to the data value to be stored according to the data coding when writing (programming) data. When reading data, a read voltage is applied to the memory cell, and data is determined depending on whether the threshold value of the memory cell is lower or higher than the read voltage. If the threshold voltage is lower than the read voltage, the data value in the "erased" state is defined as "1". If the threshold voltage is greater than or equal to the read voltage, the state is "programmed" and the data is defined as "0".

When reading data, the data is determined depending on whether the threshold value is lower or higher than the read level of the boundary to be read. The lowest threshold is the "erased" state and all bit data is defined as "1". If the threshold is higher than the "erased" state, then the "programmed" state defines the data as "1" or "0" according to the coding.

FIG. 6 is a diagram illustrating data coding in the first embodiment. In this embodiment, the eight threshold distributions (threshold regions) shown in FIG. 5 are associated with eight 3-bit data values, respectively. The relationships between the threshold voltages and the data values of the bits corresponding to the Upper, Middle, and Lower pages are as follows.
A memory cell whose threshold voltage is within the Er region stores "111".
A memory cell whose threshold voltage is in the A region stores "101".
A memory cell whose threshold voltage is within the B region is in a state of storing "001".
A memory cell whose threshold voltage is in the C region is in a state of storing "011".
A memory cell whose threshold voltage is within the D region is in a state of storing "010".
A memory cell whose threshold voltage is in the E region stores "110".
A memory cell whose threshold voltage is within the F region is in a state of storing "100".
A memory cell whose threshold voltage is in the G region stores "000".

In this manner, the state of 3-bit data in each memory cell can be represented for each threshold voltage region. When the memory cell is in a non-written state ("erased" state), the threshold voltage of the memory cell is within the Er region. In the code shown here, data "111" is stored in the Er (erase) state, and data "101" is stored in the A state. Data change. Thus, the coding shown in FIG. 6 is a Gray code in which only 1 bit of data changes between any two adjacent regions.

In the coding of the present embodiment shown in FIG. 6, threshold voltages serving as boundaries for determining bit values of each page are as follows.
• The threshold voltage that serves as a boundary for determining the bit value of the Lower page is Vr4.
The boundary threshold voltages for judging the bit values of the Middle page are Vr2, Vr5, and Vr7.
The threshold voltages that serve as boundaries for judging the bit values of the Upper page are Vr1, Vr3, and Vr6.

Thus, the number of threshold voltages that serve as boundaries for determining bit values (hereinafter referred to as boundary numbers) is 1, 3, and 3 for the Lower page, Middle page, and Upper page, respectively. Hereinafter, such coding will be referred to as 1-3-3 coding using the respective boundary numbers of the Lower page, Middle page, and Upper page. Note that the maximum number of adjacent data and changing boundaries per page is three. The maximum number of boundaries of 3 means that the maximum number of boundaries is the smallest when eight states are represented by 3 bits, and the bias of bit errors is reduced.

The control unit 22 of the nonvolatile memory 2 controls programming to the NAND memory cell array 23 and reading from the NAND memory cell array 23 based on the coding shown in FIG.

The three-dimensional memory cell has a larger memory cell size than the two-dimensional NAND memory of the recent miniaturization generation, and the mutual interference between cells is small. In this case, generally, all bits are programmed at the same time (all pages are programmed at the same time if each bit is assigned to a different page).

When programming all bits simultaneously, 1-2-4 coding or 2-3-2 coding is used as data coding. In 1-2-4 coding, when the 7 boundaries between the 8 threshold distributions are distributed over 3 pages, 1 on the Lower page, 2 on the Middle page, 4 on the Upper page, and so on. distributes the boundaries to Also, in 2-3-2 coding, when distributing the seven boundaries between the eight threshold distributions to three pages, there are two on the Upper page, three on the Middle page, and two on the Lower page. The boundaries are distributed like this.

However, in the case of 1-2-4 coding, the number of boundaries is significantly uneven on each page, resulting in a large uneven bit error rate between pages. This is because most of the causes of bit errors are caused by threshold shifts to neighboring distributions, and the number of bit errors increases in pages with more boundaries. This leads to the need to enhance the ECC correction capability required to correct page data errors even if the error rate as a memory cell is the same. It exacerbates cost and power consumption. In addition, bias in the number of boundaries also causes bias in readout speed.

Also, in a 3-bit/cell NAND memory, mutual interference between cells is greater than in a 1-bit/cell or 2-bit/cell NAND memory. For this reason, in recent generations of NAND memory with advanced miniaturization, in order to suppress mutual interference between cells, charges are generally injected into the floating gates of memory cells little by little using three or two stages. There is a programming method (LM-Foggy-Fine program or Foggy-Fine program). In this LM-Foggy-Fine program, after writing the first stage (LM stage), write to the adjacent cell, return to the previous cell, write the second stage (Foggy stage), and then The data is written to the adjacent cell again, and then the data is returned to the previous memory cell and written by the three program stages of the third stage (Fine stage).

In addition, in the Foggy-Fine program, after writing in the first stage (Foggy stage), write to adjacent cells, then return to the previous memory cell and perform two program stages in the second stage (Fine stage). Write is performed. Each program stage in this case is a program execution unit, and the program for one word line WLi is completed by executing three program stages.

In the program of the LM stage, which is the first stage, the input data may be only Lower page data. In the program of the second stage, the Foggy stage, the program is executed using eight threshold distributions. The threshold distribution (threshold region) at this time has a wider width than the threshold distribution in the final data coding. That is, foggy (rough) writing is performed in the foggy stage. This Foggy stage program requires all three pages of input data. Since the threshold distribution after programming the Foggy stage is in an intermediate state where adjacent distributions overlap each other, data cannot be read. In the programming of the Fine stage, which is the third stage, the threshold distribution after programming in the Foggy stage is moved to the threshold distribution in the final data coding. That is, fine writing is performed in the fine stage. This Fine stage program also requires all three pages of input data. Since the threshold distribution after programming in the Fine stage is the final state in which adjacent distributions are separated, data can be read after programming in the Fine stage.

In the case of 2-3-2 coding, there is little bias in the number of boundaries, but in the data input of the LM-Foggy-Fine program, data input for 3 pages is required in all stages. In data input of the Foggy-Fine program, data input for two pages is required in all stages. This increases the time it takes to enter the data and slows down the storage device. Also, in the storage device, the amount of write buffer (write buffer amount) for holding data to be input to the NAND memory is increased. A partial area of the RAM 11 provided in the storage device is generally allocated to this write buffer.

As a countermeasure against these, there is a method of adopting 1-3-3 coding and executing the LM-Foggy-Fine program. Since this method employs the LM-Foggy-Fine program, mutual interference between cells can be suppressed. In addition, since data for one page may be input to the LM stage, it is possible to both reduce the amount of write buffers and suppress the bias in the bit error rate caused by the bias in the number of boundaries between pages.

However, when the NAND memory of the nonvolatile memory 2 has a three-dimensional structure, the write buffer size is Since it becomes large, the cost of the memory controller 1 increases.

Therefore, in this embodiment, the storage device adopts 1-3-3 coding for the non-volatile memory 2 having a three-dimensional structure, and further performs page-by-page writing in two stages. implement. As a result, in this embodiment, even in the nonvolatile memory 2 having a three-dimensional structure, the write buffer capacity of the memory controller 1 is reduced while suppressing the mutual interference between cells and the uneven bit error rate between pages.

Interference between adjacent memory cells will now be described. The charge stored on the floating gate of one memory cell disturbs the electric field of adjacent memory cells, resulting in noise that varies the read threshold of adjacent memory cells. Programming and verifying are performed under certain electric field conditions, and after the programming is completed, adjacent memory cells are programmed with different charges, resulting in degradation of read accuracy. This interference between adjacent memory cells becomes more conspicuous as the memory device manufacturing technology is miniaturized and the memory cell spacing is reduced. This interference between adjacent memory cells is largely caused by adjacent memory cells on the same word line WLi and different bit lines and adjacent memory cells on the same bit line and different word lines WLi.

Neighboring memory cell interference can be mitigated by reducing the difference in memory cell electric field conditions between programming and verifying and reading after adjacent memory cells are programmed. is. One method of reducing inter-adjacent memory cell interference between adjacent memory cells on different bit lines on the same word line WLi is to divide the program into multiple stages to avoid large changes in charge between each stage. There is a way to run a multi-stage program that

In the program sequence of this embodiment, 3 bits on one word line WLi are programmed by two program stages, ie, the 1st stage and the 2nd stage. Each program stage is a program execution unit, and the memory device of this embodiment completes the programming of word lines WLi by executing two program stages. Further, in the present embodiment, one of 3-bit pages is allocated to each of the two program stages. Specifically, Lower page data is allocated to the 1st stage program, and Middle page and Upper page data are allocated to the 2nd stage program.

FIG. 7 is a diagram showing a threshold distribution after programming in the first embodiment. FIG. 7 shows the threshold distribution after each programming stage for the memory cells. (T1) in FIG. 7 shows the threshold distribution in the erased state, which is the initial state before programming. (T2) in FIG. 7 shows the threshold distribution after programming of the 1st stage. (T3) in FIG. 7 shows the threshold distribution after the programming of the 2nd stage.

As shown in (T1) of FIG. 7, all memory cells of the NAND memory cell array 23 are in a state of distribution Er in an unwritten state ("erased" state). As shown in (T2) of FIG. 7, the control unit 22 of the nonvolatile memory 2 maintains the distribution Er for each memory cell according to the bit values written (stored) in the Lower page in the 1st stage program. or inject charge to move it to a distribution above the distribution Er. Specifically, the control unit 22 does not inject charge when the bit value to be written to the lower page is "1", and injects charge when the bit value to be written to the lower page is "0". Program the threshold voltage to move higher.

Thereby, the memory cells are programmed to binary levels by the Lower page data. What should be noted here is that the function in the 1st stage program (first program) is a function of only Lower page data. The page data required for this execution is only the Lower page. Furthermore, since the threshold distribution after programming in the 1st stage is finally reprogrammed in the programming of the 2nd stage (the second program), there is no need to finely shape the distribution, and high-speed programming can be achieved. It is possible. Since the data after programming in the 1st stage looks like binary data, it is possible to read the Lower page data. Therefore, the threshold level for programming in the 1st stage is controlled to be between Vr1 and Vr4 in view of the assignment to transition to D or higher in the programming for the 2nd stage.

In addition, as shown in (T3) of FIG. 7, the 2nd stage program requires two pages, a Middle page and an Upper page, to write data. Then, the control unit 22 of the nonvolatile memory 2 programs the threshold distribution after programming in the 2nd stage so that the final state in which each adjacent distribution is separated has eight levels. In this case, all page data can be read.

Note that programming is typically performed by applying a programming voltage pulse one or more times. After each program voltage pulse, a read is performed to determine if the memory cell has moved beyond the threshold boundary level. By repeating this application and reading, it becomes possible to shift the threshold voltage of the memory cell within the range of the predetermined threshold voltage distribution.

Note that the control unit 22 may continuously perform the 1st stage programming and the 2nd stage programming for one word line WLi. It is also possible to perform programming in non-sequential order across the word lines WLi.

FIG. 8A is a diagram showing a first example of program order of the first embodiment. FIG. 8B is a diagram showing a second example of the program order of the first embodiment. FIG. 8C is a diagram showing a third example of program order of the first embodiment. 8A to 8C show a sequence (two-stage programming method) in which the influence of interference between adjacent memory cells is reduced. FIG. 8A shows an example of programming order when the string in the block is one NAND memory. Figures 8B and 8C also show an example of the programming order when the strings in the block are four NAND memories.

When writing is started, the control unit 22 proceeds through each program stage while straddling the word lines WLi in a predetermined discontinuous order. That is, two different program stages are not executed consecutively on the same word line WLi.

For example, after the word line WLi is programmed up to the 2nd stage, if the adjacent word line WLi is programmed in the 1st stage and the 2nd stage, the amount of change in the threshold value increases. If the amount of change in the threshold value of the adjacent word line WLi is large, interference between adjacent memory cells between the word lines WLi increases. Therefore, in order to reduce the interference between adjacent memory cells between word lines WLi, it is effective to reduce the fluctuation amount of the threshold value of the adjacent word lines WLi after the word lines WLi have been programmed up to the 2nd stage. . With such a sequence, the programming stage of the adjacent word line WLi becomes only the 2nd stage after the programming of the word line WLi is completed up to the 2nd stage.

In the case of the NAND memory shown in FIG. 8A (when the NAND memory of the nonvolatile memory 2 has a three-dimensional structure), when writing is started, the control unit 22 performs the following (1) to The program is executed in the order shown in (9). In the following processing, the operation of the program of the control unit 22 is based on the instructions from the processor 12, but for the sake of simplification of explanation, the description that it is based on the instructions from the processor 12 is omitted.

(1) First, the control unit 22 executes the 1st stage program ST ₁ 1 for the word line WL0.
(2) Next, the control unit 22 executes the 1st stage program ST ₁ 2 for the word line WL1.
(3) Next, the control unit 22 executes the 2nd stage program ST ₁ 3 for the word line WL0.
(4) Next, the control unit 22 executes the 1st stage program ST ₁ 4 for the word line WL2.
(5) Next, the control unit 22 executes the 2nd stage program ST ₁ 5 for the word line WL1.
(6) Next, the control unit 22 executes the 1st stage program ST ₁ 6 for the word line WL3.
(7) Next, the control unit 22 executes the 2nd stage program ST ₁ 7 for the word line WL2.
(8) Next, the control unit 22 executes the 1st stage program ST ₁ 8 for the word line WL4.
(9) Next, the control unit 22 executes the 2nd stage program ST ₁ 9 for the word line WL3.
Similarly, the control unit 22 proceeds with the processing in the order of the arrows pointing diagonally upward to the right in the table shown in FIG. 8A.

In the case of the NAND memory shown in FIG. 8B (when the NAND memory of the nonvolatile memory 2 has a three-dimensional structure), when writing is started, the control unit 22 executes the program in the order shown in (11) to (24) below. implement.

(11) First, the control unit 22 executes the 1st stage program ST ₂ 1 for the string St0_word line WL0.
(12) Next, the control unit 22 executes the 1st stage program ST ₂ 2 for the string St1_word line WL0.
(13) Next, the control unit 22 executes the 1st stage program ST ₂ 3 for the string St2_word line WL0.
(14) Next, the control unit 22 executes the 1st stage program ST ₂ 4 for the string St3_word line WL0.
(15) Next, the control unit 22 executes the 1st stage program ST ₂ 5 for the string St0_word line WL1.
(16) Next, the control unit 22 executes the 2nd stage program ST ₂ 6 for the string St0_word line WL0.
(17) Next, the control unit 22 executes the 1st stage program ST ₂ 7 for the string St1_word line WL1.
(18) Next, the control unit 22 executes the 2nd stage program ST ₂ 8 for the string St1_word line WL0.
(19) Next, the control unit 22 executes the 1st stage program ST ₂ 9 for the string St2_word line WL1.
(20) Next, the control unit 22 executes the 2nd stage program ST ₂ 10 for the string St2_word line WL0.
(21) Next, the control unit 22 executes the 1st stage program ST ₂ 11 for the string St3_word line WL1.
(22) Next, the control unit 22 executes the 2nd stage program ST ₂ 12 for the string St3_word line WL0.
(23) Next, the control unit 22 executes the 1st stage program ST ₂ 13 for the string St0_word line WL2.
(24) Next, the control unit 22 executes the 2nd stage program ST ₂ 14 for the string St0_word line WL1.
Likewise, the control unit 22 advances the processing in the order of the arrows pointing diagonally upward to the right in the table shown in FIG. 8B. Note that FIG. 8B describes the case where there are four strings in the block, but the number of strings in the block may be three or less, or may be five or more.

In the case of the NAND memory shown in FIG. 8C (when the NAND memory of the nonvolatile memory 2 has a three-dimensional structure), when writing is started, the control unit 22 executes the program in the order shown in (31) to (50) below. implement.

(31) First, the control unit 22 executes the 1st stage program ST ₃ 1 for the string St0_word line WL0.
(32) Next, the control unit 22 executes the 1st stage program ST ₃ 2 for the string St1_word line WL0.
(33) Next, the control unit 22 executes the 1st stage program ST ₃ 3 for the string St2_word line WL0.
(34) Next, the control unit 22 executes the 1st stage program ST ₃ 4 for the string St3_word line WL0.
(35) First, the control unit 22 executes the 1st stage program ST ₃ 5 for the string St0_word line WL1.
(36) Next, the control unit 22 executes the 1st stage program ST ₃ 6 for the string St1_word line WL1.
(37) Next, the control unit 22 executes the 1st stage program ST ₃ 7 for the string St2_word line WL1.
(38) Next, the control unit 22 executes the 1st stage program ST ₃ 8 for the string St3_word line WL1.
(39) Next, the control unit 22 executes the 2nd stage program ST ₃ 9 for the string St0_word line WL0.
(40) Next, the control unit 22 executes the 2nd stage program ST ₃ 10 for the string St1_word line WL0.
(41) Next, the control unit 22 executes the 2nd stage program ST ₃ 11 for the string St2_word line WL0.
(42) Next, the control unit 22 executes the 2nd stage program ST ₃ 12 for the string St3_word line WL0.
(43) Next, the control unit 22 executes the 1st stage program ST ₃ 13 for the string St0_word line WL2.
(44) Next, the control unit 22 executes the 1st stage program ST ₃ 14 for the string St1_word line WL2.
(45) Next, the control unit 22 executes the 1st stage program ST ₃ 15 for the string St2_word line WL2.
(46) Next, the control unit 22 executes the 1st stage program ST ₃ 16 for the string St3_word line WL2.
(47) Next, the control unit 22 executes the 2nd stage program ST ₃ 17 for the string St0_word line WL1.
(48) Next, the control unit 22 executes the 2nd stage program ST ₃ 18 for the string St1_word line WL1.
(49) Next, the control unit 22 executes the 2nd stage program ST ₃ 19 for the string St2_word line WL1.
(50) Next, the control section 22 executes the program ST ₃ 20 of the 2nd stage of the string St3_word line WL1.
Note that FIG. 8C describes the case where there are four strings in the block, but the number of strings in the block may be three or less, or may be five or more.

In this way, even if there are a plurality of strings, the order of programming the word lines WLi in each program stage in one string is the same as in the case of one string. In the case of the non-volatile memory 2 having a three-dimensional structure in which a plurality of strings exist in a block, the combination position of word lines WLi and strings is generally programmed by first programming the same word line number in different strings. then advance to the next wordline number. When following such an order, combining FIG. 8A by the number of strings results in an order such as that shown in FIG. 8B or FIG. 8C, for example.

An example of a write procedure according to the program order according to the first embodiment will now be described with reference to FIGS. 9A to 9C. 9A to 9C show the write procedure when following the program order shown in FIG. 8B or 8C. As described above, the memory controller 1 advances the program stage while straddling the word lines WLi in a discontinuous order. do.

FIG. 9A is a flow chart showing a first example of a procedure for writing an entire block according to the first embodiment. Here, one block has n+1 word lines WLi of word lines WL0 to WLn (n is a natural number). FIG. 9B is a sub-flowchart showing the writing procedure in the 1st stage according to the first embodiment, and FIG. 9C is a sub-flowchart showing the writing procedure in the 2nd stage according to the first embodiment. (1st) shown to the right of each step in FIG. 9A corresponds to the 1st stage shown in FIG. 9B, and (2nd) corresponds to the 2nd stage shown in FIG. 9C.

As shown in FIG. 9A, when writing is started, the control unit 22 executes the 1st stage programming of the string St0_word line WL0 (step S10). Next, the control unit 22 executes the 1st stage programming of the string St1_word line WL0 (step S20). After that, the control unit 22 performs the same processing as steps S10 and S20 on each string. Then, the control unit 22 executes the 1st stage programming of the string St3_word line WL0 (step S30).

Furthermore, the control unit 22 executes the 1st stage programming of the string St0_word line WL1 (step S40). Next, the control unit 22 executes the 2nd stage programming of the string St0_word line WL0 (step S50). Next, the control unit 22 executes the 1st stage programming of the string St1_word line WL1 (step S60). Thereafter, the control unit 22 repeats the processing of steps S40, S50, S60 for each word line WLi of each string.

Then, the control unit 22 executes the 1st stage programming of the string St0_word line WLn (step S70). Next, the control unit 22 executes the 2nd stage programming of the string St0_word line WLn−1 (step S80). Thereafter, the control unit 22 repeats the processing like steps S70 and S80 for each word line WLi of each string.

Then, the control unit 22 executes the 2nd stage programming of the string St3_word line WLn-1 (step S90). Next, the control unit 22 executes the 2nd stage programming of the string St0_word line WLn (step S100). Next, the control unit 22 executes the 2nd stage programming of the string St1_word line WLn (step S110). Thereafter, the control unit 22 performs the same processing as steps S100 and S110 on each string. Then, the control unit 22 executes the 2nd stage programming of the string St3_word line WLn (step S120).

As shown in FIG. 9B, in the 1st stage program, first, a lower page data input start command is input from the memory controller 1 to the nonvolatile memory 2 (step S210). Then, the lower page data is input from the memory controller 1 to the nonvolatile memory 2 (step S220). Further, a program execution command for the 1st stage is input from the memory controller 1 to the nonvolatile memory 2 (step S230), and the chip becomes busy (step S240).

When writing data, one to a plurality of program voltage pulses are applied (step S250). A data read is then performed to determine if the memory cell has moved beyond the threshold boundary level (step S260).

Furthermore, it is checked whether the number of fail bits of the data in the Lower page is smaller than the criterion (determination standard) (step S270). If the number of fail bits of data is equal to or greater than the criteria (step S270, No), the processing of steps S250 to S270 is repeated. Then, when the number of fail bits of the data becomes smaller than the criteria (step S270, Yes), the chip is ready (step S280). By repeating application, reading, and confirmation in this way, it is possible to shift the threshold value of the memory cell within the range of the predetermined threshold value distribution.

As shown in FIG. 9C, in the 2nd stage program, first, a middle page data input start command is input from the memory controller 1 to the nonvolatile memory 2 (step S310). Then, data of the Middle page is input from the memory controller 1 to the nonvolatile memory 2 (step S320).

Next, a command to start inputting upper page data is input from the memory controller 1 to the nonvolatile memory 2 (step S330). Then, the upper page data is input from the memory controller 1 to the nonvolatile memory 2 (step S340). Next, a second stage program execution command is input from the memory controller 1 to the nonvolatile memory 2 (step S350), and the chip becomes busy (step S360).

Thereafter, the control unit 22 reads Lower page data, which is IDL (Internal Data Load) (step S370). Then, Vth (threshold voltage) of the program destination of the Middle page and Upper page is determined based on the Lower page data (step S380). Thereafter, data is written to the Middle page and Upper page using the determined Vth.

Furthermore, in order to increase the reliability of the read data of the IDL, the control unit 22 can read the data a plurality of times, determine the majority of the read results in the page buffer 24 in the chip, and use it as the next write data. is. Of course, the control unit 22 can perform reading a plurality of times during normal reading operation, determine the majority of the results of reading within the chip, and use it as read data to the outside.

FIG. 9E is a diagram for explaining majority processing of the results of reading a plurality of times. In FIG. 9E, correct bits are indicated by circles (o) and incorrect bits are indicated by crosses (x). Also, FIG. 9E shows the result of the majority decision when three readings are performed.

In each bit, the result of the majority decision is determined to be erroneous when (a) it is erroneous three times and (b) it is erroneous twice. If the probability that each bit is erroneous is p, and if p = 0.2, then the probability of (a) being erroneous three times is p x p x p = 0.2 x 0.2 x 0.2, and ( b) The probability of getting it wrong twice is (1−p)×p×p=(1−0.2)×0.2×0.2. Therefore, it is (p.times.p.times.p)+3.times.(1-p).times.p.times.p=0.104 that the three majority results are determined to be erroneous. In this way, the control unit 22 can increase the reliability of the read data by performing the majority decision processing of the results of reading a plurality of times in the page buffer 24 within the chip.

When writing data to the middle page and upper page, one to a plurality of program voltage pulses are applied (step S390). Then, in order to confirm whether the memory cell has moved beyond the threshold boundary level, data reading of the Middle page and Upper page is performed (step S400).

Further, it is checked whether the number of fail bits of data in the Middle page and Upper page is smaller than the criteria (step S410). If the number of fail bits of data in the middle page and the upper page is equal to or greater than the criteria (step S410, No), the processing of steps S390 to S410 is repeated. Then, when the number of fail bits of data becomes smaller than the criteria (step S410, Yes), the chip is ready (step S420).

Here, a modification of the write procedure shown in FIG. 9C will be described. FIG. 9D is a sub-flowchart showing a modification of the write procedure in the 2nd stage according to the first embodiment; In the processing procedure shown in FIG. 9D, the processing procedures of steps S310 to S420 are the same as those of FIG. 9C except that the processing of step S370 described in FIG. 9C is not performed.

In the case of the processing procedure shown in FIG. 9D, steps S301 to S309 are performed before step S310. Specifically, first, a lower page read command is input from the memory controller 1 to the nonvolatile memory 2 (step S301), and the chip becomes busy (step S302).

After that, the control unit 22 reads the IDL Lower page data at the threshold voltage of Vr4. Then, the control unit 22 determines the value of the read data to be "0" or "1" based on the read result at the threshold voltage of Vr4 (step S303). After that, the chip becomes ready (step S304).

When the controller 22 outputs the read lower page data (step S305), this lower page data is sent to the ECC circuit 14 (step S306). As a result, the ECC circuit 14 ECC-corrects the lower page data (step S307).

Then, a lower page data input start command is input from the memory controller 1 to the nonvolatile memory 2 (step S308). As a result, the ECC circuit 14 inputs data of the Lower page to the nonvolatile memory 2 (step S309).

After that, the processing of steps S310 to S420 is performed. In step S380, based on the Lower page data from the ECC circuit 14, Vth of the program destination of the Middle page and Upper page is determined.

In the 2nd stage program described above, the data input to the nonvolatile memory 2 is only two pages, the Middle page and the Upper page. However, in this 2nd stage, Vth, which is the destination of memory cell programming, requires data for 3 pages including the Lower page (Vth before starting the 2nd stage). Therefore, in the program at this stage, as preprocessing, the control unit 22 first reads the Lower page data, synthesizes the data with the input Middle page and Upper page, and determines Vth of the program destination. I do.

The lower page data can be read because 1-3-3 coding, in which the number of lower page boundaries is one, is employed. Since the lower page data is read out in the second stage, it is unnecessary to input the lower page data in the second stage. That is, since 1-3-3 coding is adopted and Vth of the program destination is determined based on the lower page data, interference between adjacent memory cells between word lines WLi can be reduced, and one page data can be processed only once. data entry.

As a result, when the LM-Foggy-Fine program is executed in 3 stages using 1-3-3 coding, the amount of memory required for the write buffer of the memory controller 1 is reduced to multiple word lines (up to 7 pages). ), whereas in the present embodiment, the memory capacity required for the write buffer of the memory controller 1 is at most two pages.

Here, a comparison between the processing procedure of the LM-Foggy-Fine program employing 1-3-3 coding and the program processing procedure of this embodiment will be described. FIG. 10A is a diagram for explaining the amount of write buffer data in the LM-Foggy-Fine program employing 1-3-3 coding.

In FIG. 10A and FIG. 10B, which will be described later, the upper side shows a time chart of data input and program execution for block writing, and the lower side shows a time chart of the period required to hold data in the write buffer. there is Note that FIG. 10A and FIG. 10B, which will be described later, show the case where the number of strings in one block is 1 for the sake of simplicity of explanation. If there are multiple strings, a memory amount equal to the number of strings is required.

In the case of the 1-3-3 coding LM-Foggy-Fine program, the LM stage, which is the first stage, consists of one page of data input and this one page of program (LM stage program). will be In addition, in the case of the 1-3-3 coding LM-Foggy-Fine program, in the second stage, the Foggy stage, 3 pages of data are input, and this 3 pages of program (Foggy stage program) and is done. In the case of the 1-3-3 coding LM-Foggy-Fine program, in the third stage, the Fine stage, 3 pages of data are input, and this 3-page program (Fine stage program) is is done.

On each word line WL0, WL1, WL2, . must be stored in the write buffer.

In the LM-Foggy-Fine program as well, data for three pages of Lower/Middle/Upper are not written continuously in order to reduce interference between adjacent memory cells. For example, after the LM stage for word line WL0 is executed, the LM stage for word line WL1 adjacent to word line WL0 is executed before the Foggy stage for word line WL0 is executed. After the Foggy stage for word line WL0 is executed, the Foggy stage for word line WL1 adjacent to word line WL0 is executed before the Fine stage for word line WL0 is executed. Similarly, after the LM stage for word line WL1 is performed, the LM stage for word line WL2 adjacent to word line WL1 is performed before the Foggy stage for word line WL1 is performed. After executing the Foggy stage for the word line WL1, before executing the Fine stage for the word line WL1, the Foggy stage for the word line WL2 adjacent to the word line WL1 is executed.

Thus, in the LM-Foggy-Fine program, it takes a long time from the LM stage to the Fine stage in each word line WLi. For example, the program of the following stages (P1) to (P5) is executed between the LM stage and the Fine stage on the word line WL1.
(P1) LM stage for word line WL2 (P2) Foggy stage for word line WL1 (P3) Fine stage for word line WL0 (P4) LM stage for word line WL3 (P5) Foggy stage for word line WL2

Thus, in the case of the 1-3-3 coding LM-Foggy-Fine program, the input data is only the Lower page in the first LM stage. However, in this method, it is necessary to hold the data for three pages of Lower/Middle/Upper in the write buffer until data input for the third and final Fine stage is completed. Also, in order to reduce interference between adjacent memory cells, it is necessary to hold data in a plurality of word lines WLi in a write buffer. For example, when the foggy stage is executed for the word line WL2, 3 pages of data for the word line WL1, 3 pages of data for the word line WL2, and 1 page of data for the word line WL3. must be held in the write buffer. Thus, in the case of the 1-3-3 coding LM-Foggy-Fine program, a maximum of 7 pages of data must be held in the write buffer.

FIG. 10B is a diagram for explaining the write buffer amount (buffer data amount) in the program of the first embodiment. The program of this embodiment uses a two-stage program with 1-3-3 coding. In the program of this embodiment, in the 1st stage, data input for one page (lower page) and programming for this one page (1st program) are performed. Further, in the case of the program of the present embodiment, in the 2nd stage, data input for 2 pages (middle page and upper page) and programming for these 2 pages (2nd program) are performed.

In each word line WL0, WL1, WL2, . May be deleted. For example, when data is input in the 1st stage, this data is stored in the write buffer. Then, when the program is started in the 1st stage, the data stored in the write buffer may be deleted. Similarly, when data is input in the 2nd stage, this data is stored in the write buffer. Then, when the program is started in the 2nd stage, the data stored in the write buffer may be deleted.

Also in the programming of this embodiment, data for three pages of Lower/Middle/Upper are not written continuously in order to reduce interference between adjacent memory cells. For example, after the 1st stage for word line WL0 is executed, the 1st stage for word line WL1 adjacent to word line WL0 is executed before the 2nd stage for word line WL0 is executed. Similarly, after the 1st stage for word line WL1 is executed, the 1st stage for word line WL2 adjacent to word line WL1 is executed before the 2nd stage for word line WL1 is executed.

Thus, since the program of the present embodiment has two stages, the processing from the 1st stage to the 2nd stage is short for each word line WLi. For example, the program of the following stage (P11) is executed between the 1st stage and the 2nd stage on the word line WL1.
(P11) 1st stage for word line WL2

Further, in the case of the program of this embodiment, it is only necessary to hold data in the write buffer from the start of data input until the end of data input, and when the program starts, the data is deleted from the write buffer. may be Therefore, in the case of the program of this embodiment, the data that needs to be held in the write buffer is at most two pages worth of data.

As described above, in this embodiment, all page data is required only for one stage of programming, so that data in the write buffer can be discarded when the data input is completed. Therefore, in this embodiment, the number of pages that need to be held simultaneously in the write buffer is small.

The page data to be programmed into the non-volatile memory 2 is configured by a write buffer in the RAM 11 and is temporarily held, and then input to the non-volatile memory 2 during programming. In this embodiment, the required capacity of the RAM 11 can be reduced, resulting in cost reduction.

Also, when the LM-Foggy-Fine program or the Foggy-Fine program is used, data transfer of all page data must be performed two or three times. is also required in excess. In this embodiment, all page data is completed by one data transfer for each page, so that the transfer time and power consumption can be reduced to about 1/2 to 1/3.

FIG. 11 is a diagram showing an example of a sequence of external program commands according to the first embodiment. FIG. 11A shows the sequence of external program commands in the 1st stage according to the first embodiment, and FIG. 11B shows the sequence of external program commands in the 2nd stage according to the first embodiment. showing.

As shown in FIG. 11A, in the 1st stage, after the program start command (80h) is input, the address of the block/page to be programmed (lower page address) is input, and then the lower page is programmed. Data is entered. Then, when the program execution command (10h) is finally input, the chip becomes busy and the program starts operating inside the memory chip. Inputting such a program command programs the Lower page.

As shown in FIG. 11B, in the 2nd stage, after the program start command (80h) is input, the address of the block/page to be programmed (middle page address) is input, and then the middle page program Data is entered. After that, a concatenation command (1Ah) of program commands is input, and program data for the Upper page is input in the same sequence. Then, when the program execution command (10h) is finally input, the chip becomes busy and the program starts operating inside the memory chip. By inputting such a program command, the Lower page is read, and the Middle page and Upper page are programmed. Either the program data for the Middle page or the program data for the Upper page may be input first.

Here, page read processing will be described. The page read method differs depending on whether the word line WLi including the page to be read is programmed before or after the 2nd stage write.

Before the 2nd stage writing, only the Lower page of the recorded data is valid. Therefore, the control unit 22 reads data from the memory cells only when the read page is the Lower page. Then, in the case of other pages, the control unit 22 does not perform the memory cell read operation, but performs control to forcibly output all "1" as read data.

On the other hand, in the case of the word line WLi that has completed up to the 2nd stage, the control unit 22 reads the memory cells regardless of whether the read page is the Upper/Middle/Lower page. In this case, since the necessary read voltage differs depending on which page is read, the control unit 22 performs only necessary read according to the selected page.

According to the coding shown in FIG. 6, there is only one boundary between the threshold states where the Lower page data changes, so the control unit 22 determines which of the two ranges separated by the boundary has a threshold value. The data is determined by whether the is located. For example, when the threshold voltage is lower than Vr4, the control unit 22 performs control to output "1" as data of the memory cell. On the other hand, when the threshold voltage is higher than Vr4, the control unit 22 performs control to output "0" as data of the memory cell.

Also, since there are three boundaries between the threshold states where the data of the Middle page or the Upper page change, the control unit 22 determines which of the four ranges separated by these boundaries the threshold is located. Determine the data by

A specific processing procedure for page reading will be described below. FIG. 12A is a flow chart showing a processing procedure of page reading on word lines before 2nd stage writing in the storage device according to the first embodiment. FIG. 12B is a flow chart showing a processing procedure of page reading on a word line for which programming has been completed up to the 2nd stage in the memory device according to the first embodiment.

As shown in FIG. 12A, in the case of the word line WLi before the 2nd stage write, the control unit 22 selects the read page (step S510). If the page to be read is the Lower page (Step S510, Lower), the control unit 22 reads with the threshold voltage of Vr4 (Step S520). Then, the control unit 22 determines the value of the read data to be "0" or "1" based on the read result at the threshold voltage of Vr4 (step S530).

If the page to be read is the Middle page (step S510, Middle), the control unit 22 forcibly outputs "1" as the output data of the memory cells (step S540).

If the read page is the Upper page (step S510, Upper), the control unit 22 forcibly outputs "1" as the output data of all the memory cells (step S550).

Further, as shown in FIG. 12B, in the case of the word line WLi that has been programmed up to the 2nd stage, the control unit 22 selects the read page (step S610). If the page to be read is the Lower page (step S610, Lower), the control unit 22 reads at the threshold voltage of Vr4 (step S620). Then, the control unit 22 determines the value of the read data to be "0" or "1" based on the read result at the threshold voltage of Vr4 (step S630).

If the page to be read is the Middle page (step S610, Middle), the control unit 22 reads at the threshold voltages of Vr1, Vr3 and Vr6 (steps S640, S650, S660). Then, the control unit 22 determines the value of the read data to be "0" or "1" based on the read results at the threshold voltages Vr1, Vr3 and Vr6 (step S670).

If the page to be read is the Upper page (step S610, Upper), the control unit 22 performs the reading with threshold voltages Vr2, Vr5 and Vr7 (steps S680, S690, S700). Then, the control unit 22 determines the value of the read data to be "0" or "1" based on the read results at the threshold voltages Vr2, Vr5 and Vr7 (step S710).

The memory controller 1 can manage and identify whether the program for the word line WLi is before or after the completion of the 2nd stage write. Since the memory controller 1 performs program control, if the memory controller 1 records the progress, the memory controller 1 can easily determine which address in the nonvolatile memory 2 is in which program state. can refer to. In this case, when reading from the nonvolatile memory 2, the memory controller 1 identifies what program state the word line WLi including the target page address is in, and issues a read command according to the identified state. .

FIG. 13 is a diagram showing an example of a sequence of external read commands according to the first embodiment. FIG. 13A shows the sequence of external read commands on the word line WLi for which programming has been completed up to the 1st stage in the storage device according to the first embodiment, and FIG. 2 shows a sequence of external read commands on the word line WLi for which programming has been completed up to the 2nd stage in the storage device according to the embodiment of FIG.

As shown in FIG. 13A, in the case of the word line WLi before the 2nd stage write, a command (2Dh) indicating the state before the 2nd stage write is first input as a command for executing the read operation. After that, a read start command (00h) is input, and then the address of the block/page to be read (lower page, middle page, or upper page address) is input. Finally, when the read execution command (30h) is input, the chip becomes busy and the read operation starts inside the memory chip. Data is read from the Lower page, Middle page, or Upper page by inputting such a program command. The chip is then ready to output the read data.

On the other hand, as shown in FIG. 13B, in the case of the word line WLi for which programming has been completed up to the 2nd stage, a command (25h) indicating the completion state up to the 2nd stage is first input as a command for executing the read operation. be done. After that, a read start command (00h) is input, and then the address of the block/page to be read (lower page, middle page, or upper page address) is input. Finally, when the read execution command (30h) is input, the chip becomes busy and the read operation starts inside the memory chip. By inputting such a program command, data is read from the address of the Lower page, Middle page or Upper page. The chip is then ready to output the read data.

As described above, in the first embodiment, 1-3-3 data coding is adopted when programming the nonvolatile memory 2 (3-bit/cell NAND memory having a three-dimensional structure or a two-dimensional structure). The stage of was made into a 2-stage system. Since programming is performed in a two-stage system in this manner, the amount of data input during data programming is reduced, and the amount of write buffer required for the memory controller 1 can be suppressed. In addition, the bias of the bit error rate between pages of the nonvolatile memory 2 can be reduced, and the cost of ECC can be reduced. In addition, since data is transferred only once for each page, transfer time and power consumption can be reduced.

Moreover, since each program stage is executed while straddling word lines WLi, the amount of interference between adjacent cells with adjacent word lines WLi can be reduced. Also, since 1-3-3 data coding is used, the IDL margin before the 2nd stage can be expanded, and the reliability of the write sequence can be improved. Also, since 1-3-3 data coding is used, the 1st stage program, that is, the Lower page program can be speeded up by setting the threshold boundary to one in the Lower page. The programming speed of the 1st stage is increased by stepping up the write voltage little by little when writing and writing verify are repeated, and setting the step voltage to a value higher than that of the 2nd stage programming. can be done.

(Second embodiment)
Next, a second embodiment will be described with reference to FIGS. 14A, 14B and 15. FIG. In the second embodiment, the 2nd stage programming of the word line WLn−1 and the 1st stage programming of the word line WLn are collectively performed. In this embodiment, the case where the same data coding as that explained in FIG. 6 of the first embodiment is used will be explained.

In the flowchart of the program shown in FIG. 9A, the 1st stage program and the 2nd stage program are all separated one by one, and each program command and program data are input during each program. . In this embodiment, this program command and program data input are collected as much as possible.

For example, as shown in FIG. 8B, programming of the 1st stage of the word line WLn and the programming of the 2nd stage of the word line WLn−1 always continue except for the beginning and end of the block. Therefore, in the present embodiment, this part is used as a collective command input. That is, with one command input, the program data of the lower page of word line WLn and the middle/upper page of word line WLn−1 are collectively input. Even if LM-Foggy-Fine is adopted, the data of the Lower/Middle/Upper pages are collectively input with one program command (however, in this case, the pages within the same word line WLi) are input for 3 pages. It is the same amount of data input as was done.

By combining the input of program commands and program data in this way, the frequency of command input and polling (regular checking of whether the chip busy has returned to ready) in the control performed by the memory controller 1 is reduced. Higher speed and simplification as a storage device are possible.

An example of the write procedure according to the program order according to the second embodiment will now be described with reference to FIGS. 14A and 14B. 14A and 14B show the write procedure when following the program order shown in FIG. 8B. 14A or 14B, descriptions of the same processes as those described with reference to FIGS. 9A to 9C will be omitted.

FIG. 14A is a flow chart showing a procedure for writing an entire block according to the second embodiment. Here, one block has n+1 word lines WLi of word lines WL0 to WLn (n is a natural number). FIG. 14B is a sub-flowchart showing write procedures in the 1st stage and the 2nd stage according to the second embodiment. Note that (1st) shown to the right of each step in FIG. 14A corresponds to the 1st stage shown in FIG. 9B, (2nd) corresponds to the 2nd stage shown in FIG. It corresponds to the 1st stage and the 2nd stage shown in 14B.

As shown in FIG. 14A, when writing is started, the control unit 22 executes steps S810 to S830, which are similar to steps S10 to S30. As a result, the 1st stage programming of the word line WL0 of the strings St0 to St3 is performed.

Further, the control unit 22 executes the 1st stage programming of the string St0_word line WL1 and the 2nd stage programming of the string St0_word line WL0 (step S840). Next, the control unit 22 executes the 1st stage programming of the string St1_word line WL1 and the 2nd stage programming of the string St1_word line WL0 (step S850). Next, the control unit 22 executes the 1st stage programming of the string St2_word line WL1 and the 2nd stage programming of the string St2_word line WL0 (step S860). After that, the control unit 22 repeats the processing such as steps S840, S850, and S860 for each word line WLi of each string.

Then, the control unit 22 executes the 1st stage programming of the string St0_word line WLn and the 2nd stage programming of the string St0_word line WLn-1 (step S870). Next, the control unit 22 executes the 1st stage programming of the string St1_word line WLn and the 2nd stage programming of the string St1_word line WLn−1 (step S880). Thereafter, the control unit 22 repeats the processing like steps S870 and S880 for each word line WLi of each string.

Then, the control unit 22 executes the 1st stage programming of the string St3_word line WLn and the 2nd stage programming of the string St3_word line WLn−1 (step S890). Next, the control unit 22 executes the processes of steps S900 to S920, which are the same processes as steps S100 to S120. As a result, the word lines WLn of the strings St0 to St3 are programmed in the 2nd stage.

Thus, at the beginning of the block, only the 1st stage is programmed as in the first embodiment, and at the end of the block, as in the first embodiment, only the 2nd stage is programmed. In this case, the program for only the 1st stage is executed according to the procedure shown in FIG. 9B, and the program for only the 2nd stage is executed according to the procedure shown in FIG. 9C.

As shown in FIG. 14B, in the 1st stage and 2nd stage programs, the 1st stage program is executed continuously after the 2nd stage program is executed. Specifically, first, a command to start inputting middle page data of the word line WLn-1 is input from the memory controller 1 to the nonvolatile memory 2 (step S1010). Then, data of the Middle page of the word line WLn−1 is input from the memory controller 1 to the nonvolatile memory 2 (step S1020).

Next, a command to start inputting upper page data of the word line WLn−1 is input from the memory controller 1 to the nonvolatile memory 2 (step S1030). Then, the upper page data of the word line WLn−1 is input from the memory controller 1 to the nonvolatile memory 2 (step S1040).

Next, a command to start inputting lower page data of the word line WLn is input from the memory controller 1 to the nonvolatile memory 2 (step S1050). Then, the lower page data of the word line WLn is input from the memory controller 1 to the nonvolatile memory 2 (step S1060).

Next, a program execution command for the 1st stage and the 2nd stage is input from the memory controller 1 to the nonvolatile memory 2 (step S1070), and the chip becomes busy (step S1080).

Thereafter, one to a plurality of program voltage pulses are applied to the lower page of word line WLn (step S1090). Then, in order to confirm whether the memory cell has moved beyond the threshold boundary level, the lower page data read of word line WLn is performed (step S1100).

Further, it is checked whether the number of fail bits of data in the Lower page is smaller than the criteria (step S1110). If the number of fail bits of data in the Lower page is equal to or greater than the criteria (step S1110, No), the processes of steps S1140 to S1160 are repeated. Then, when the number of fail bits of the data becomes smaller than the criteria (step S1110, Yes), the lower page data of the word line WLn-1 is read (step S1120).

Then, based on the lower page data of the word line WLn-1, Vth (threshold voltage) of the program destination of the middle page and upper page is determined (step S1130). Thereafter, using the determined Vth, data is written to the Middle page and Upper page of word line WLn-1.

When writing data to the middle page and upper page, one to a plurality of program voltage pulses are applied to the middle page and upper page of word line WLn-1 (step S1140). Then, in order to confirm whether or not the memory cell has moved beyond the threshold boundary level, data is read from the Middle page and Upper page of word line WLn-1 (step S1150).

Furthermore, it is checked whether the number of fail bits of data in the Middle page and Upper page is smaller than the criteria (step S1160). If the number of fail bits of data in the middle page and the upper page is equal to or greater than the criteria (step S1160, No), the processes of steps S1140 to S1160 are repeated. Then, when the number of fail bits of data becomes smaller than the criteria (step S1160, Yes), the chip is ready (step S1170).

Note that any of the processes of steps S1010, S1030, and S1050 may be performed first. Moreover, any of the processes of steps S1020, S1040, and S1060 may be performed first. However, the process of step S1020 is performed after the process of step S1010, the process of step S1040 is performed after the process of step S1030, and the process of step S1060 is performed after the process of step S1050.

The processing from steps S1120 to S1160 shown in FIG. 14B corresponds to the 2nd stage programming of the word line WLn-1, and the processing from steps S1090 to S1110 corresponds to the 1st stage programming of the word line WLn. ing.

Thus, in FIG. 14B, the case where the 1st stage programming of the word line WLn is executed before the 2nd stage programming of the word line WLn−1 has been described. This is because the 1st stage programming of the word line WLn is performed first so that the cells of the word line WLn-1 to which the 8-level Vth is written are not affected by the adjacent cells.

As described above, in this embodiment, three pages of data, that is, data of the Middle page and Upper page of the word line WLn−1 and data of the Lower page of the word line WLn are continuously input.

FIG. 15 is a diagram showing an example of a sequence of external program commands according to the second embodiment. The sequence of external program commands in the 1st stage is the same as that shown in FIG. 11(A). The sequence of external program commands in the 2nd stage is the same as that shown in FIG. 11(B). Therefore, here, the sequence of external program commands when the 2nd stage and the 1st stage are programmed continuously will be described. When the 1st stage and the 2nd stage are programmed continuously, the command for the 2nd stage and the command for the 1st stage are input continuously.

Specifically, as shown in FIG. 15, after the program start command (80h) is input, the address of the block/page to be programmed (the address of the middle page of the word line WLn-1) is input, and then the word Middle page program data on line WLn-1 is input. After that, a concatenation command (1Ah) of program commands is input, and program data of the Upper page of the word line WLn-1 is input in the same sequence. Then, a concatenation command (1Ah) of program commands is input, and program data of the Lower page of the word line WLn is input in the same sequence. Then, when the program execution command (10h) is finally input, the chip becomes busy and the program starts operating inside the memory chip.

Inputting such a program command programs the lower page of the word line WLn. Also, as IDL, the lower page data of word line WLn−1 is read. Then, based on the lower page data, the Vth of the program destination of the Middle page and the Upper page is determined, and the Middle page and the Upper page of the word line WLn-1 are programmed with the determined Vth.

As another modification, after the program command is input, the IDL first reads the lower page data of the word line WLn-1, then programs the lower page of the word line WLn, and then performs the middle page data reading. The Vth of the program destination of the page and the upper page is determined, and the programming of the Middle page and the Upper page of the word line WLn can be performed with the determined Vth. By doing so, the lower page data of the word line WLn-1 of the IDL can be read before interference between adjacent cells due to the writing of the word line WLn.

In the present embodiment, the actual execution order of the program by collective commands for the 1st stage of the word line WLn and the 2nd stage of the word line WLn−1 can be modified. That is, the programming of the lower page of the word line WLn and the reading of the lower page data of the word line WLn-1 as the IDL shown in FIG. By performing IDL (reading lower page data of word line WLn−1) before programming the lower page of word line WLn, IDL can be performed without being affected by the programming of the lower page of word line WLn. Become.

As described above, in the second embodiment, the 2nd stage programming of the word line WLn-1 and the 1st stage programming of the word line WLn are collectively performed, so that the frequency of command input and polling is reduced. Therefore, it is possible to speed up and simplify the storage device.

(Third Embodiment)
Next, a third embodiment will be described with reference to FIGS. 16 to 19. FIG. In the third embodiment, when executing the programming of the second stage, the memory cells whose Vth distribution is expected to be in the region D or higher are first programmed, and then the Vth distribution is set to be in the region C or lower. Execute the program for the memory cells to be programmed. In this embodiment, the case where the same data coding as that explained in FIG. 6 of the first embodiment is used will be explained.

In a multi-bit/cell program, data will be destroyed if a sudden power cutoff occurs during execution of the program. In such a case, the information of the program data that was being executed when the power was interrupted is lost from the memory cells. In such a case, past program data that has already been programmed and has been discarded from the write buffer of the memory controller 1 may also be lost. As a result, data recovery becomes impossible.

Such an event occurs when power is cut off during the middle/upper page program of the 2nd stage. I will explain this situation. FIG. 16 is a diagram for explaining data destruction caused by power shutdown. (T11) in FIG. 16 shows the Vth distribution state (data state) after the 1st stage programming is completed. (T12) in FIG. 16 shows the Vth distribution state during programming of the 2nd stage. Also, (T13) in FIG. 16 shows the Vth distribution state after the power is cut off.

After the 1st stage program as shown at (T11) in FIG. 16 is completed, the 2nd stage program is started, and the Vth distribution state is as shown in FIG. 16 (T12). When the power supply is cut off while the Vth distribution is in the middle of writing as shown in FIG. 16(T12), the Vth distribution becomes as shown in FIG. 16(T13).

Here, consider starting the program of the 2nd stage from the state after the completion of the 1st stage. Generally, inside the NAND memory, programs are executed in order from low Vth to high Vth. Therefore, as shown in (T12) of FIG. 16, when the program of the 2nd stage has progressed halfway, if the power supply is interrupted, the Vth distribution becomes as shown in (T13) of FIG.

Here, the memory cells included in the positive distribution are in a state where the memory cells whose lower page data are "1" and the memory cells whose lower page data are "0" are mixed. Therefore, even if the lower page data whose programming has already been completed is read in this state, correct read data cannot be obtained. It should be noted that correct lower page data cannot be obtained even if the read voltage after the completion of programming in the 2nd stage is used.

Therefore, in this embodiment, the Vth order of the programs in the Middle/Upper pages of the 2nd stage is changed. FIG. 17 is a diagram for explaining the 2nd stage program according to the third embodiment. FIG. 17 shows a Vth state transition method in the 2nd stage. (T21) in FIG. 17 shows the Vth distribution state after the 1st stage programming is completed. (T22) in FIG. 17 shows the Vth distribution state at the time when the programming of the first half of the 2nd stage is completed. Also, (T23) in FIG. 17 shows the Vth distribution state at the time when the programming of the latter half of the 2nd stage is completed.

When the 1st stage shown in (T21) in FIG. 17 is completed, the control unit 22 of the present embodiment selects memory cells in which the Vth distribution state of the write destination is greater than or equal to region D, as shown in (T22) in FIG. Program first (D-First program). Then, after completing the programming of the Vth distribution state for the regions D to G, the control unit 22 executes the programming for the Vth distribution state of the regions A to C as shown in (T23) of FIG.

In this manner, the control unit 22 of the present embodiment starts programming the memory cells that cause the Vth distribution state of the write destination to be in the region D or higher before programming the memory cells that cause the Vth distribution state in the region C or lower. Then, after completing the programming of the memory cells that cause the Vth distribution state of the write destination to be the region D or more, the programming of the memory cells that is the region C or less is completed.

As a result, the timing in which memory cells whose lower page data is "1" and memory cells whose lower page data is "0" do not occur. Therefore, even if a power cutoff occurs in the 2nd stage, the control unit 22 can read the Lower page data by using either the read voltage Vr1 or Vr4.

FIG. 18 is a flow chart showing a write procedure in the 2nd stage according to the third embodiment. It should be noted that descriptions of the same processes as those described with reference to FIG. 9C will be omitted. Steps S1210 to S1280 of the second stage according to the third embodiment are the same as steps S310 to S380 of the second stage according to the first embodiment shown in FIG. 9C.

After the Vth of the program destination of the Middle page and Upper page is determined (step S1280), data is written to the Middle page and Upper page using the determined Vth.

In the 2nd stage according to the third embodiment, when data is written to the Middle page and Upper page, a program voltage pulse is applied one to a plurality of times to the memory cells that are to be regions D to G (step S1290 ). Then, in order to confirm whether or not the memory cell has moved beyond the threshold boundary level, data is read from regions D to G of the Middle and Upper pages (step S1300).

Further, it is checked whether the number of fail bits of data in areas D to G in the Middle page and Upper page is smaller than the criteria (step S1310). If the number of fail bits of data in areas D to G of the middle page and upper page is equal to or greater than the criteria (step S1310, No), the processes of steps S1290 to S1310 are repeated.

Then, when the number of fail bits of data in areas D to G of the Middle page and Upper page becomes smaller than the criteria (step S1310, Yes), writing is performed to areas A to C of the Middle page and Upper page. Specifically, when data is written to the Middle page and Upper page, one to a plurality of program voltage pulses are applied to the memory cells to be assigned to areas A to C (step S1320). Then, in order to confirm whether or not the memory cell has moved beyond the threshold boundary level, data is read from areas A to C of the Middle page and Upper page (step S1330).

Further, it is checked whether the number of fail bits of data in areas A to C in the Middle page and Upper page is smaller than the criteria (step S1340). If the number of fail bits of data in areas A to C of the middle page and upper page is equal to or greater than the criteria (step S1340, No), steps S1320 to S1340 are repeated.

Then, when the number of fail bits of data in areas A to C of the Middle page and Upper page becomes smaller than the criteria (step S1350, Yes), the chip is ready (step S1350).

In this embodiment, programming of the Vth distribution states of the regions D to G is completed in the first half of the programming of the 2nd stage. It doesn't have to end in In this case, the control unit 22 temporarily leaves the program up to the Vth distribution state of the region D or so. After that, the control unit 22 sequentially executes the programs of the areas A to C and the programs of the areas D to G which were in the middle of the programming.

FIG. 19 is a diagram for explaining a program modification of the 2nd stage according to the third embodiment. FIG. 19 shows a Vth state transition method (modification) in the 2nd stage. (T31) in FIG. 19 shows the Vth distribution state after the 1st stage programming is completed. Also, (T32) in FIG. 19 shows the Vth distribution state at the time when the programming of the first half of the 2nd stage is completed. Also, (T33) in FIG. 19 shows the Vth distribution state at the time when the programming of the latter half of the 2nd stage is completed.

When the 1st stage shown in (T31) of FIG. 19 is completed, the control unit 22 of the present embodiment executes the program up to the Vth distribution state of about region D as shown in (T32) of FIG. do. After that, the control unit 22 executes the programs of the regions A to C using the Vth distribution state of the region Er. Further, the control unit 22 uses the Vth distribution state of about the region D (the Vth distribution state in the middle of the program) to execute the program of the regions D to G. FIG.

In the case of the method shown in FIG. 19, as in the case of the method shown in FIG. will no longer occur. Therefore, even if a power cutoff occurs in the 2nd stage, the control unit 22 can read the Lower page data by using either the read voltage Vr1 or Vr4.

In this way, the control unit 22 moves the threshold distribution for the memory cells that cause the Vth distribution state of the write destination to be greater than or equal to the region D to a position that does not overlap the threshold regions of the regions Er to C. After that, programming to the memory cells in the regions Er to G is completed.

As described above, in the third embodiment, when programming the second stage, the upper Vth distribution is programmed first, so collateral destruction of written data due to illegal power shutdown can be prevented. , it is possible to improve the reliability of the storage device.

In the first to third embodiments, the case of using the same 1-3-3 data coding as that described with reference to FIG. 6 has been described, but other 1-3-3 data coding may be used. . However, in 1-3-3 data coding, there is a condition that the lower page data has one boundary.

FIG. 20 is a diagram showing another example of 1-3-3 data coding. In modification 1 of 1-3-3 data coding shown in FIG. 20A, the relationship between the threshold voltage and the data value is as follows.
A memory cell whose threshold voltage is within the Er region stores "111".
A memory cell whose threshold voltage is within the A region is in a state of storing "011".
A memory cell whose threshold voltage is within the B region is in a state of storing "001".
A memory cell whose threshold voltage is within the C region is in a state of storing "101".
A memory cell whose threshold voltage is in the D region stores "100".
A memory cell whose threshold voltage is in the E region stores "110".
A memory cell whose threshold voltage is within the F region is in a state of storing "010".
A memory cell whose threshold voltage is in the G region stores "000".

In modification 2 of 1-3-3 data coding shown in FIG. 20B, the relationship between the threshold voltage and the data value is as follows.
A memory cell whose threshold voltage is within the Er region stores "110".
A memory cell whose threshold voltage is within the A region stores "100".
A memory cell whose threshold voltage is within the B region is in a state of storing "000".
A memory cell whose threshold voltage is within the C region is in a state of storing "010".
A memory cell whose threshold voltage is within the D region is in a state of storing "011".
A memory cell whose threshold voltage is in the E region stores "111".
A memory cell whose threshold voltage is within the F region is in a state of storing "101".
A memory cell whose threshold voltage is in the G region stores "001".

In modification 3 of 1-3-3 data coding shown in FIG. 20C, the relationship between the threshold voltage and the data value is as follows.
A memory cell whose threshold voltage is within the Er region stores "110".
A memory cell whose threshold voltage is within the A region is in a state of storing "010".
A memory cell whose threshold voltage is within the B region is in a state of storing "000".
A memory cell whose threshold voltage is within the C region is in a state of storing "100".
A memory cell whose threshold voltage is within the D region is in a state of storing "101".
A memory cell whose threshold voltage is in the E region stores "111".
A memory cell whose threshold voltage is within the F region is in a state of storing "011".
A memory cell whose threshold voltage is in the G region stores "001".

(Fourth embodiment)
A fourth embodiment will now be described with reference to FIG. In the fourth embodiment, the 1st stage is the Lower/Middle page program, and the 2nd stage is the Upper page program.

FIG. 21 is a diagram showing the threshold distribution after programming in the fourth embodiment. FIG. 21 shows the threshold distribution after each programming stage for the memory cells. (T41) in FIG. 21 shows the threshold distribution in the erased state, which is the initial state before programming. (T42) in FIG. 21 shows the threshold distribution after the programming of the 1st stage. (T43) in FIG. 21 shows the threshold distribution after the programming of the 2nd stage.

As shown in (T41) of FIG. 21, all memory cells of the NAND memory cell array 23 are in a state of distribution Er in an unwritten state. As shown in (T42) of FIG. 21, the control unit 22 of the nonvolatile memory 2 keeps the distribution Er for each memory cell according to the bit values written in the Lower/Middle pages in the 1st stage program. Alternatively, charge is injected to move to a distribution above the distribution Er. Thereby, the memory cells are programmed to four levels by the Lower/Middle page data.

In addition, as shown in (T43) of FIG. 21, in the program of the 2nd stage, one page of the upper pages is required for data writing. The control unit 22 of the nonvolatile memory 2 adds data of the Upper page as the 2nd stage to the data of the 1st stage. In this way, the control unit 22 programs the threshold distribution after programming in the 2nd stage so that the final state in which each adjacent distribution is separated has eight levels.

For example, the threshold levels for programming to the four levels of the 1st stage are as follows. The control unit 22 controls the second lowest threshold level to have the same distribution as the area A, considering that the second stage program allocates the area A and the area B so as to transition. In addition, the control unit 22 controls the third lowest threshold level to be between Vr3 and Vr5, considering that the second stage program allocates the transition to the areas D and E. FIG. In addition, the control unit 22 controls the highest threshold level to be between Vr5 and Vr7, considering that the second stage program allocates transitions to regions E and F. After that, the control unit 22 uses the 4 values of the 1st stage to program the 8 values of the 2nd stage.

In order to reduce the influence of interference between adjacent memory cells, programs are executed in the same order as shown in FIG. 8B. That is, two different program stages are not executed consecutively on the same word line WLi. In order to reduce the interference between adjacent memory cells between word lines WLi, it is effective to reduce the fluctuation amount of the threshold value of the adjacent word lines WLi after the word lines WLi have been programmed up to the 2nd stage. . With the sequence shown in FIG. 8B, the adjacent word line WLi is programmed only in the 2nd stage after the word line WLi has been programmed up to the 2nd stage, so the influence of interference between adjacent memory cells can be reduced.

Here, a write procedure according to the fourth embodiment will be described. Note that the procedure for writing an entire block according to the fourth embodiment is the same as the procedure for writing an entire block (FIG. 9A) according to the first embodiment, so description thereof will be omitted. In the present embodiment, as in the first embodiment, the program stage proceeds in a discontinuous order while straddling the word lines WLi. A program is executed as a unit.

FIG. 22A is a sub-flowchart showing the writing procedure in the 1st stage according to the fourth embodiment, and FIG. 22B is a sub-flowchart showing the writing procedure in the 2nd stage according to the fourth embodiment. It should be noted that, among the processes shown in FIG. 22A, descriptions of the same processes as those shown in FIG. 9B will be omitted. Further, among the processes shown in FIG. 22B, descriptions of the same processes as those shown in FIG. 9C are omitted.

As shown in FIG. 22A, in the 1st stage program, first, a lower page data input start command is input from the memory controller 1 to the nonvolatile memory 2 (step S1410). Lower page data is then input from the memory controller 1 to the nonvolatile memory 2 (step S1420).

Further, a middle page data input start command is input from the memory controller 1 to the nonvolatile memory 2 (step S1430). The middle page data is then input from the memory controller 1 to the nonvolatile memory 2 (step S1440).

A 1st stage program execution command is input from the memory controller 1 to the nonvolatile memory 2 (step S1450), and the chip becomes busy (step S1460).

After that, Vth of the program destination of the 2nd stage is determined based on the Lower page data and the Middle page data (step S1470). Thereafter, data is written to the Lower page and Middle page using the determined Vth.

When writing data to the Lower page and Middle page, one to a plurality of program voltage pulses are applied (step S1480). A read is then performed to determine if the memory cell has moved beyond the threshold boundary level (step S1490). Furthermore, it is checked whether the number of fail bits of data in the Lower page and the Middle page is smaller than the criteria (determination standard) (step S1500). If the number of fail bits in the data is greater than or equal to the criteria (step S1500, No), the processing of steps S1480 to S1500 is repeated. Then, when the number of fail bits of data becomes smaller than the criteria (step S1500, Yes), the chip is ready (step S1510).

As shown in FIG. 22B, in the 2nd stage program, first, a command to start inputting upper page data is input from the memory controller 1 to the nonvolatile memory 2 (step S1610). Then, data of the Upper page is input from the memory controller 1 to the nonvolatile memory 2 (step S1620). Next, a second stage program execution command is input from the memory controller 1 to the nonvolatile memory 2 (step S1630), and the chip becomes busy (step S1640).

Thereafter, lower page data, which is IDL, is read (step S1650). Furthermore, reading of Middle page data, which is IDL, is performed (step S1660). Then, based on the Lower page data and the Middle page data, the Vth of the program destination of the Upper page is determined (step S1670). Thereafter, data is written to the Upper page using the determined Vth.

Furthermore, in order to increase the reliability of the read data of the IDL, the control unit 22 can read the data a plurality of times, determine the majority of the read results in the page buffer 24 in the chip, and use it as the next write data. is. Of course, the control unit 22 can perform reading a plurality of times during normal reading operation, determine the majority of the results of reading within the chip, and use it as read data to the outside.

When writing data to the Upper page, one to a plurality of program voltage pulses are applied (step S1680). The data read of the Upper page is then performed to see if the memory cell has moved beyond the threshold boundary level (step S1690).

Further, it is checked whether the number of fail bits of data in the Upper page is smaller than the criteria (step S1700). If the number of fail bits of data in the Upper page is equal to or greater than the criteria (step S1700, No), the processing of steps S1680 to S1700 is repeated. Then, when the number of fail bits of data becomes smaller than the criteria (step S1700, Yes), the chip is ready (step S1710).

Here, a modification of the write procedure shown in FIG. 22B will be described. FIG. 22C is a sub-flowchart showing a modification of the write procedure in the 2nd stage according to the fourth embodiment. In the processing procedure shown in FIG. 22C, the processing procedure of steps S1610 to S1710 is the same as that of FIG. 22B except that the processing of steps S1650 and S1670 described in FIG. 22B is not performed.

In the case of the processing procedure shown in FIG. 22C, steps S1601 to S1609 are performed before step S1610. Specifically, first, a lower page and middle page read command is input from the memory controller 1 to the nonvolatile memory 2 (step S1601), and the chip becomes busy (step S1602).

Thereafter, the control unit 22 reads the IDL Lower page data and Middle page data at threshold voltages Vr1, Vr3, Vr5, and Vr7. Then, the control unit 22 determines the value of the read data to be "0" or "1" based on the read results at the threshold voltages Vr1, Vr3, Vr5, and Vr7 (step S1603). After that, the chip becomes ready (step S1604).

When the control unit 22 outputs the read lower page data and middle page data (step S1605), the lower page data and middle page data are sent to the ECC circuit 14 (step S1606). As a result, the ECC circuit 14 ECC-corrects the Lower page data and the Middle page data (step S1607).

Then, a command to start inputting lower page data and middle page data is input from the memory controller 1 to the nonvolatile memory 2 (step S1608). As a result, the ECC circuit 14 inputs data of the Lower page and Middle page data to the nonvolatile memory 2 (step S1609).

After that, the processing of steps S1610 to S1710 is performed. In step S1670, based on the Lower page data and Middle page data from the ECC circuit 14, Vth of the program destination of the Middle page and Upper page is determined.

Thus, in this embodiment, the data input in the 2nd stage program is only one page of the Upper page. However, in this 2nd stage, Vth, which is the destination of memory cell programming, requires data for three pages including Lower/Middle pages. Therefore, in this 2nd stage program, the Lower page data and the Middle page data are first read out as preprocessing. By synthesizing the read data and the input Upper page data, Vth of the program destination of the Upper page is determined.

FIG. 23 is a diagram showing an example of a sequence of external program commands according to the fourth embodiment. FIG. 23A shows the sequence of external program commands in the 1st stage according to the fourth embodiment, and FIG. 24B shows the sequence of external program commands in the 2nd stage according to the fourth embodiment. showing.

As shown in FIG. 23A, in the 1st stage, after the program start command (80h) is input, the address of the block/page to be programmed (lower page address) is input, and then the lower page is programmed. Data is entered. After that, a concatenation command (1Ah) of program commands is input, and in the same sequence, the middle page program data is input. Then, when the program execution command (10h) is finally input, the chip becomes busy and the program starts operating inside the memory chip. Inputting such a program command programs the Lower page and the Middle page. It does not matter which of the lower page program data and the middle page program data is input first.

As shown in FIG. 23B, in the 2nd stage, after the program start command (80h) is input, the address of the block/page to be programmed (upper page address) is input, and then the upper page is programmed. Data is entered. Then, when the program execution command (10h) is finally input, the chip becomes busy and the program starts operating inside the memory chip. By inputting such a program command, the Lower page and Middle page as IDL are read, and the Upper page is programmed.

Here, page read processing will be described. The page read method differs depending on whether the word line WLi including the page to be read is programmed before the 2nd stage write or after the 2nd stage is completed.

In the case of the word line WLi before the 2nd stage writing, the recorded data are effective in the Lower page and the Middle page. Therefore, the control unit 22 reads data from the memory cells when the read page is the Lower page or the Middle page. Then, in the case of the Upper page, the control unit 22 does not perform the memory cell read operation, but performs control to forcibly output all "1" as read data.

On the other hand, in the case of the word line WLi that has completed up to the 2nd stage, the control unit 22 reads the memory cells regardless of whether the read page is the Upper/Middle/Lower page. In this case, since the necessary read voltage differs depending on which page is read, the control unit 22 performs only necessary read according to the selected page.

According to the coding shown in FIG. 6, there is only one boundary between the threshold states where the Lower page data changes, so the control unit 22 determines which of the two ranges separated by the boundary has a threshold value. The data is determined by whether the is located.

Also, since there are three boundaries between the threshold states where the data of the Middle page or the Upper page change, the control unit 22 determines which of the four ranges separated by these boundaries the threshold is located. Determine the data by

A specific processing procedure for page reading will be described below. FIG. 24A is a flow chart showing a processing procedure of page reading on word lines before 2nd stage writing in the memory device according to the fourth embodiment. FIG. 24B is a flowchart showing a processing procedure of page reading in a word line for which programming has been completed up to the 2nd stage in the memory device according to the fourth embodiment. It should be noted that, among the processes shown in FIG. 24A, descriptions of the same processes as those shown in FIG. 12A will be omitted. Further, among the processes shown in FIG. 24B, descriptions of the same processes as those shown in FIG. 12B are omitted.

As shown in FIG. 24A, in the case of the word line WLi before the 2nd stage write, the control unit 22 selects the read page (step S1810). If the page to be read is the Lower page (Step S1810, Lower), the control unit 22 reads at the threshold voltage of Vr3 (Step S1820). Then, the control unit 22 determines the value of the read data to be "0" or "1" based on the read result at the threshold voltage of Vr3 (step S1830).

If the page to be read is the Middle page (step S1810, Middle), the control section 22 performs the reading with the threshold voltages of Vr1, Vr3 and Vr5 (steps S1840, S1850, S1860). Then, the control unit 22 determines the value of the read data to be "0" or "1" based on the read results at the threshold voltages Vr1, Vr3 and Vr5 (step S1870).

If the page to be read is the Upper page (step S1810, Upper), the control unit 22 forcibly outputs "1" as the output data of the memory cells (step S1880).

Further, as shown in FIG. 24B, in the case of the word line WLi that has been programmed up to the 2nd stage, the control unit 22 selects a read page (step S1910). If the page to be read is the Lower page (Step S1910, Lower), the control unit 22 reads at the threshold voltage of Vr4 (Step S1920). Then, the control unit 22 determines the value of the read data to be "0" or "1" based on the read result at the threshold voltage of Vr4 (step S1930).

If the page to be read is the Middle page (step S1910, Middle), the control unit 22 performs reading with threshold voltages Vr1, Vr3 and Vr6 (steps S1940, S1950, S1960). Then, the control unit 22 determines the value of the read data to be "0" or "1" based on the read results at the threshold voltages Vr1, Vr3 and Vr6 (step S1970).

If the page to be read is the Upper page (step S1910, Upper), the control unit 22 performs the reading with threshold voltages Vr2, Vr5 and Vr7 (steps S1980, S1990, S2000). Then, the control unit 22 determines the value of the read data to be "0" or "1" based on the read results at the threshold voltages Vr2, Vr5 and Vr7 (step S2010).

In this way, in the program control of the threshold value as shown in FIG. 21, Vr3 is used as the read level that can separate the four levels by two levels above and below when reading the lower page data. In the case of reading the middle page data, since the data allocation is such that the data cannot be determined unless one of the four levels is specified, it is necessary to read three levels of Vr1, Vr3 and Vr5 as read levels. Become.

On the other hand, in the case of the word line WLi that has completed up to the 2nd stage, memory cells are read regardless of whether the read page is Upper/Middle/Lower. Only the necessary reads according to the page specified are performed.

It should be noted that the memory controller 1 can manage and identify to which of the 1st stage and the 2nd stage the programming for the word line WLi has been completed. Since the memory controller 1 performs program control, if the memory controller 1 records the progress, the memory controller 1 can easily determine which address in the nonvolatile memory 2 is in which program state. can refer to. In this case, when reading from the nonvolatile memory 2, the memory controller 1 identifies what program state the word line WLi including the target page address is in, and issues a read command according to the identified state. .

FIG. 25 is a diagram showing an example of a sequence of external read commands according to the fourth embodiment. FIG. 25A shows the sequence of external read commands on the word line WLi for which programming has been completed up to the 1st stage in the storage device according to the fourth embodiment, and FIG. 2 shows a sequence of external read commands on the word line WLi for which programming has been completed up to the 2nd stage in the storage device according to the embodiment of FIG.

As shown in FIG. 25A, in the case of the word line WLi before the 2nd stage write, a command (2Dh) indicating the state before the 2nd stage write is first input as a command for executing the read operation. After that, a read start command (00h) is input, and then the address of the block/page to be read (lower page, middle page, or upper page address) is input. Finally, when the read execution command (30h) is input, the chip becomes busy and the read operation starts inside the memory chip. Data is read from the Lower page, Middle page, or Upper page by inputting such a program command. The chip is then ready to output the read data.

On the other hand, as shown in FIG. 25B, in the case of the word line WLi for which programming has been completed up to the 2nd stage, a command (25h) indicating the completion state up to the 2nd stage is first input as a command for executing the read operation. be done. After that, a read start command (00h) is input, and then the address of the block/page to be read (lower page, middle page, or upper page address) is input. Finally, when the read execution command (30h) is input, the chip becomes busy and the read operation starts inside the memory chip. Data is read from the Lower page, Middle page, or Upper page by inputting such a program command. The chip is then ready to output the read data.

Note that the same modification as the modification of the second embodiment with respect to the first embodiment may be applied to the present embodiment. That is, also in the present embodiment, the 2nd stage programming of word line WLn−1 and the 1st stage programming of word line WLn may be performed together.

Also, in the present embodiment, the restriction that the number of boundaries in the Lower is 1 is not required for the type of 1-3-3 data coding. Therefore, 1-3-3 data coding other than the 1-3-3 data coding used in the first to third embodiments may be applied. Specific states of the 1-3-3 data coding of this embodiment are shown in FIGS. It is a thing.

Thus, in the fourth embodiment, as in the first embodiment, when programming the nonvolatile memory 2 (3-bit/cell NAND memory having a three-dimensional structure or a two-dimensional structure), 1-3 -3 data coding was adopted, and the program was made into a 2-stage system. Since programming is performed in a two-stage system in this manner, the amount of data input during data programming is reduced, and the amount of write buffer required for the memory controller 1 can be suppressed. In addition, the bias of the bit error rate between pages of the nonvolatile memory 2 can be reduced, and the cost of ECC can be reduced.

(Fifth embodiment)
Next, a fifth embodiment will be described with reference to FIGS. 26 to 30. FIG. In the fifth embodiment, it is recorded in a memory cell (flag cell) to which of the 1st stage and the 2nd stage the programming for the word line WLi has been completed. appropriately control the read sequence based on

In this embodiment, the case where the same data coding as that explained in FIG. 6 of the first embodiment is used will be explained. Also, in the following description, a memory cell array that stores data may be referred to as a data storage cell. Further, information indicating whether the 1st stage or the 2nd stage has been completed may be referred to as completion information. In this embodiment, data is written in the flag cell when the process is completed up to the 2nd stage, so this data becomes the completion information indicating that the process is completed up to the 2nd stage. On the other hand, if the 2nd stage has not been completed yet, no data is written in the flag cell, so this unwritten data becomes completion information indicating that the 2nd stage has not been completed.

FIG. 26 is a diagram for explaining the configuration of a flag cell. This embodiment also uses a memory cell array having a configuration similar to that of the memory cell array described in FIG. 3 of the first embodiment. Note that FIG. 26 shows the memory cell transistors MT and the like connected to the select gate line SGD0, and omits the illustration of the memory cell transistors MT and the like connected to the select gate lines SGD1 to SGD3.

Dummy cells DC and flag cells FC are arranged beside the memory cell transistors (data storage cells) MT connected to the bit lines BL0 to BLm-1. Dummy cell DC and flag cell FC have the same configuration as memory cell transistor MT. Specifically, the dummy cells DC are connected to a select gate line SGD0, word lines WL0 to WL7, a select gate line SGS, a source line SL, a dummy cell bit line DBL, and the like. The flag cells FC are connected to a select gate line SGD0, word lines WL0 to WL7, a select gate line SGS, a source line SL, flag cell bit lines FBL0 to FBLk-1, and the like. In other words, some of the memory cells in the block BLK are used for data storage, and the remaining part are used as dummy cells DC and flag cells FC.

In the first to fifth embodiments, the memory controller 1 manages and identifies to which of the 1st stage and the 2nd stage the programming for the word lines WLi has been completed. When reading data, the memory controller 1 issues a read command according to the completion state of the program.

On the other hand, in the present embodiment, the control unit 22 records in the flag cell FC of the nonvolatile memory 2 completion information indicating which of the 1st stage and the 2nd stage has been completed. When reading data, the control unit 22 controls the read sequence based on the completion information recorded in the flag cell FC.

A flag cell FC is provided for each word line. That is, some of the plurality of memory cells in word line WLi are used as flag cells FC. Although one flag cell FC may be provided for each word line WLi, a plurality of flag cells FC is preferably provided in order to increase the reliability of data through multiplexing. Also, in order to suppress the influence of deterioration in reliability due to interference between adjacent cells, it is preferable not to physically adjoin the data storage cell storing data and the flag cell FC. For example, it is preferable to arrange dummy cells DC, which are not used as data recording areas, between the data storage cells and the flag cells FC.

The completion information recorded in the flag cell FC is binary information indicating whether or not the programming of the 2nd stage has been performed. The control unit 22 writes completion information indicating that the programming of the 2nd stage is completed in the flag cell FC in the same word line WLi during the programming of the 2nd stage. The control unit 22 writes the completion information in the flag cell FC at D level or higher, for example. How the threshold distribution changes at this time will be described.

FIG. 27A is a diagram for explaining programming of flag cells according to the fifth embodiment. FIG. 27A shows a transition method of the Vth state in the flag cell FC performed during programming of the 2nd stage.

(T51) in FIG. 27A shows the Vth distribution state in the flag cell FC in the erased state, which is the initial state before programming. (T52) in FIG. 27A shows the Vth distribution state at the time when the programming of the 1st stage is completed. (T53) in FIG. 27A shows the Vth distribution state at the time when the programming of the 2nd stage is completed. When the 2nd stage is completed, the control unit 22 of the present embodiment sets the flag cells FC so that the Vth distribution state of the write destination is greater than or equal to the region D (Vr4 or greater), as shown in (T53) in FIG. 27A. program.

The flag cell FC is written at the same time as the data cell in the second stage, but the transition of the threshold including the flag cell FC is larger than that of the data cell. Therefore, when the reliability of the data cells adjacent to the flag cell FC deteriorates, a dummy cell DC is provided between the flag cell FC and the data cell. Also, the dummy cell DC may be written from Er to A or B or C at the 2nd stage as shown in FIG. 27B.

FIG. 27B is a diagram for explaining programming of dummy cells according to the fifth embodiment. FIG. 27B shows a transition method of the Vth state in the dummy cell DC which is performed during programming of the 2nd stage.

(T61) in FIG. 27B shows the Vth distribution state in the dummy cell DC in the erased state, which is the initial state before programming. (T62) in FIG. 27B shows the Vth distribution state at the time when the programming of the 1st stage is completed. (T53) in FIG. 27A shows the Vth distribution state at the time when the programming of the 2nd stage is completed. When the 2nd stage is completed, the control unit 22 of the present embodiment controls the dummy cells DC so that the Vth distribution state of the write destination is below the region C (below Vr4), as shown in (T63) in FIG. 27B. program.

FIG. 28 is a flow chart showing a write procedure in the 2nd stage according to the fifth embodiment. It should be noted that descriptions of the same processes as those described with reference to FIG. 9C will be omitted. Steps S2110 to S2180 of the 2nd stage according to the fifth embodiment are the same as steps S310 to S380 of the 2nd stage according to the first embodiment shown in FIG. 9C.

In this embodiment, after the Vth of the programming destination for the Middle page, Upper page, and flag cell FC is determined (step S2180), the determined Vth is used to program data storage cells (Middle page, Upper page) and flag cell FC. data is written to

In the 2nd stage according to the fifth embodiment, one to a plurality of program voltage pulses are applied when writing data to the Middle page, Upper page, and flag cells FC. (Step S2190). Data is then read from the Middle page, Upper page, and flag cell FC to determine whether the memory cell has moved beyond the threshold boundary level (step S2200).

Further, it is checked whether the number of fail bits of data in the Middle page and Upper page is smaller than the criteria (step S2210). If the number of fail bits of data in the middle page and the upper page is equal to or greater than the criteria (step S2210, No), the processing of steps S2190 to S2210 is repeated. In this case, the processing of steps S2190 and S2210 for the flag cell FC is omitted.

Then, when the number of fail bits of the data in the Middle page and the Upper page becomes smaller than the criteria (step S2210, Yes), it is checked whether the number of fail bits of the data in the flag cell FC is smaller than the criteria (step S2220). .

If the number of fail bits of the data in the flag cell FC is equal to or greater than the criteria (step S2220, No), the processing of steps S2190 to S2220 is repeated. In this case, the processes of steps S2190 to S2210 for the Middle page and Upper page are omitted.

Then, when the number of fail bits of the data in the flag cell FC becomes smaller than the criteria (step S2220, Yes), the chip is ready (step S2230).

Thus, in step S2190 (the step of applying the program voltage pulse) of this embodiment, the program voltage pulse is simultaneously applied to the flag cells FC in addition to the data storage cells in which data is to be written. In subsequent data reading, the data in the data storage cells and the data in the flag cells FC (completion information) are read to confirm whether the data storage cells and the flag cells FC have been programmed.

After that, the data read out from the data storage cells and flag cells FC are compared with the criteria corresponding to the expected values. At this time, the number of failed bits is counted, but the failed data in the data storage cells and the failed data in the flag cells FC are separately counted and compared with respective criteria. If either one of the criteria is not satisfied, the process returns to the program voltage pulse application procedure. If any comparison satisfies the criteria, the chip is made ready and the process ends.

In the page read in the first embodiment, different processing orders are used depending on whether the programming for the word line WLi including the page to be read has been completed up to the 1st stage or the 2nd stage. Which processing procedure is to be executed is determined based on the external read command. However, in the present embodiment, which of the 1st stage and the 2nd stage has been completed is not indicated by a command from the memory controller 1, but is determined according to the completion information in the flag cell FC. That is, upon receiving a read command from the memory controller 1, the control unit 22 first reads the completion information, which is the data in the flag cell FC. Then, the control unit 22 determines to which of the 1st stage and the 2nd stage the writing has been completed, depending on whether or not the flag cell FC has been written.

As described above, in this embodiment, the write level to the flag cell FC is D level or higher. Therefore, reading the flag cells FC is possible with any one of the read voltages Vr1, Vr2, Vr3 or Vr4. Therefore, the control unit 22 uses the lowest read level of the plurality of read levels required when the program up to the 2nd stage is completed, regardless of whether the page to be read is the Lower page, the Middle page, or the Upper page. , the flag cell FC can be read. Then, if it is determined that the flag cell FC has been written, the control unit 22 determines that programming up to the 2nd stage has been completed, and reads from the memory cells other than the flag cell FC at the remaining read level. Run.

On the other hand, if it is determined that the flag cell FC has not been written, and the Lower page is to be read, the control unit 22 rereads the data at Vr1. If the Middle/Upper page is to be read, the control unit 22 determines that further reading is unnecessary, and forcibly sets the output data to "1".

When determining whether or not the flag cell FC has been written from the read result (completion information) of the flag cell FC, if there is one flag cell FC, the control unit 22 determines whether the cell itself has been written. should be determined. In some cases, a plurality of flag cells FC are provided in order to increase the reliability of the data in the flag cells FC. In this case, for example, when completion information indicating that cells equal to or greater than the number of criteria have been written is read from a flag cell FC among a plurality of flag cells FC, the control unit 22 determines that the flag cell FC has been written. We judge that it is.

Here, a specific processing procedure for page reading will be described. FIG. 29 is a flowchart showing a page read processing procedure according to the fifth embodiment. 29, the description of the same processing as the processing shown in FIG. 12A or FIG. 24A will be omitted.

As shown in FIG. 29, the control unit 22 selects a read page (step S2310). If the page to be read is the Lower page (Step S2310, Lower), the control unit 22 reads at the threshold voltage of Vr4 (Step S2320).

Then, the control unit 22 determines whether completion information is written in the flag cell FC (step S2330). If the completion information has not been written in the flag cell FC (step S2330, No), the control unit 22 performs reading at the threshold voltage of Vr1 (step S2340). Then, the control unit 22 determines the value of the read data to be "0" or "1" based on the read result at the threshold voltage of Vr1 (step S2350).

On the other hand, if the completion information has already been written in the flag cell FC (step S2330, Yes), the control unit 22 sets the value of the read data to "0" or "" based on the read result at the threshold voltage of Vr4. 1″ (step S2360).

If the page to be read is the Middle page (step S2310, Middle), the control unit 22 reads at the threshold voltage of Vr1 (step S2370). Then, the control unit 22 determines whether completion information is written in the flag cell FC (step S2380). If the completion information has not been written in the flag cell FC (step S2380, No), the control unit 22 forcibly outputs "1" as the output data of the data storage cells (middle page) (step S2390). .

On the other hand, if the completion information has already been written in the flag cell FC (step S2380, Yes), the control unit 22 reads with the threshold voltages of Vr3 and Vr6 (steps S2400, S2410). Then, the control unit 22 determines the value of the read data to be "0" or "1" based on the read results at the threshold voltages Vr1, Vr3 and Vr6 (step S2420).

If the page to be read is the Upper page (step S2430, Upper), the control unit 22 reads at the threshold voltage of Vr2 (step S2370). Then, the control unit 22 determines whether completion information is written in the flag cell FC (step S2440). If the completion information has not been written in the flag cell FC (step S2440, No), the control unit 22 forcibly outputs "1" as the output data of the data storage cells (upper page) (step S2450). .

On the other hand, if the completion information has already been written in the flag cell FC (step S2440, Yes), the control unit 22 performs reading at the threshold voltages of Vr5 and Vr7 (steps S2460, S2470). Then, the control unit 22 determines the value of the read data to be "0" or "1" based on the read results at the threshold voltages of Vr2, Vr5 and Vr7 (step S2780).

FIG. 30 is a diagram showing an example of a sequence of external read commands according to the fifth embodiment. In this embodiment, there is only one type of read command. As shown in FIG. 30, a read start command (00h) is input as a command for executing a read operation, and then the address of the block/page to be read (lower page, middle page, or upper page address) is input. . Finally, when the read execution command (30h) is input, the chip becomes busy and the read operation starts inside the memory chip. Data is read from the Lower page, Middle page, or Upper page by inputting such a program command. The chip is then ready to output the read data.

As described above, in the fifth embodiment, since the completion information is stored in the flag cell FC, it is possible to read the page data in the same processing order regardless of whether the 1st stage or the 2nd stage has been completed. Become.

(Sixth embodiment)
Next, a sixth embodiment will be described with reference to FIGS. 31 to 36. FIG. In the sixth embodiment, page unit writing is performed in two stages to the nonvolatile memory 2 of 4 bits/cell (QLC: Quadruple Level Cell) having a three-dimensional structure or a two-dimensional structure.

FIG. 31 is a diagram showing an example of threshold regions according to the sixth embodiment. FIG. 31 shows a threshold distribution example of the nonvolatile memory 2 of 4 bits/cell. The 16 distributions labeled Er1, A1, B1, C1, D1, E1, F1, G1, H1, I1, J1, K1, L1, M1, N1, and O1 in FIG. Each threshold distribution within the region is shown. Thus, each memory cell of this embodiment has a threshold distribution partitioned by 15 boundaries. The horizontal axis of FIG. 31 indicates the threshold voltage, and the vertical axis indicates the distribution of the number of memory cells (the number of cells).

In the present embodiment, the region where the threshold voltage is Vr11 or lower is called region Er1, the region where the threshold voltage is higher than Vr11 and lower than or equal to Vr12 is called region A1, and the threshold voltage is higher than Vr12 and lower than or equal to Vr13. A region where the threshold voltage is higher than Vr13 and lower than or equal to Vr14 is referred to as a region C1. In the present embodiment, a region where the threshold voltage is greater than Vr14 and less than or equal to Vr15 is called region D1, and a region where the threshold voltage is greater than Vr15 and less than or equal to Vr16 is called region E1. A region where the threshold voltage is greater than Vr16 and less than or equal to Vr17 is called region F1, and a region where the threshold voltage is greater than Vr17 and less than or equal to Vr18 is called region G1.

In the present embodiment, a region where the threshold voltage is greater than Vr18 and less than or equal to Vr19 is called region H1, and a region where the threshold voltage is greater than Vr19 and less than or equal to Vr20 is called region I1. A region where the threshold voltage is greater than Vr20 and less than or equal to Vr21 is called region J1, and a region where the threshold voltage is greater than Vr21 and less than or equal to Vr22 is called region K1. In the present embodiment, a region where the threshold voltage is greater than Vr22 and less than or equal to Vr23 is called region L1, and a region where the threshold voltage is greater than Vr23 and less than or equal to Vr24 is called region M1. A region where the threshold voltage is greater than Vr24 and less than or equal to Vr25 is called region N1, and a region where the threshold voltage is greater than Vr25 is called region O1.

Also, the threshold distributions corresponding to the regions Er1, A1, B1, C1, D1, E1, F1, G1, H1, I1, J1, K1, L1, M1, N1, O1 are represented by distributions Er1, A1, B1, They are called C1, D1, E1, F1, G1, H1, I1, J1, K1, L1, M1, N1, O1 (first to sixteenth distributions). Vr11 to Vr25 are threshold voltages that serve as boundaries between regions.

The following FIGS. 32, 34 and 36 show threshold distributions after each programming stage for a 4-bit/cell memory cell. Also, the threshold distribution shown in FIG. 32 and the data coding shown in FIG. 33 correspond to 1-4-5-5 coding. In 1-4-5-5 coding, the number of boundaries for determining bit values is 1, 4, 5, and 5 for the Lower page, Middle page, Upper page, and Higher page, respectively.

FIG. 32 is a diagram of a first example showing a threshold distribution after programming in the sixth embodiment. (T71) in FIG. 32 shows the threshold distribution in the erased state, which is the initial state before programming. (T72) in FIG. 32 shows the threshold distribution after programming of the 1st stage. (T73) in FIG. 32 shows the threshold distribution after programming of the 2nd stage.

As shown in (T71) of FIG. 32, all memory cells of the NAND memory cell array 23 have distribution Er in the unwritten state. As shown in (T72) of FIG. 32, the control unit 22 of the nonvolatile memory 2 keeps the distribution Er for each memory cell according to the bit values written to the Lower page and Middle page in the 1st stage program. , or inject charge to move it to a distribution above the distribution Er. Thereby, the memory cells are programmed to four levels by the Lower page data and the Middle page data.

Also, as shown in (T73) in FIG. 32, in the 2nd stage program, two pages, an Upper page and a Higher page, are required for writing data. Then, the control unit 22 of the nonvolatile memory 2 programs the threshold distribution after programming in the 2nd stage so that the final state in which each adjacent distribution is separated has 16 levels. In this case, all page data can be read.

FIG. 33 shows data coding corresponding to the threshold distribution shown in FIG. In the data coding shown in FIG. 33, for example, a memory cell whose threshold voltage is in the Er1 area stores "1111" as the data value of bits corresponding to the Upper, Middle, Lower, and Higher pages. be. A memory cell whose threshold voltage is within the A1 area stores "1011".

Also, the threshold distribution shown in FIG. 34 and the data coding shown in FIG. 35 correspond to 1-6-4-4 coding. In 1-6-4-4 coding, the number of boundaries for determining bit values is 1, 6, 4, and 4 for the Lower page, Middle page, Upper page, and Higher page, respectively.

FIG. 34 is a diagram of a second example showing the threshold distribution after programming in the sixth embodiment. (T81) in FIG. 34 shows the threshold distribution in the erased state, which is the initial state before programming. (T82) in FIG. 34 shows the threshold distribution after programming of the 1st stage. (T83) in FIG. 34 shows the threshold distribution after the programming of the 2nd stage.

As shown in (T81) of FIG. 34, all memory cells of the NAND memory cell array 23 have distribution Er in an unwritten state. As shown in (T82) of FIG. 34, the control unit 22 of the nonvolatile memory 2 maintains the distribution Er for each memory cell according to the bit values written to the Lower page and Middle page in the 1st stage program. , or inject charge to move it to a distribution above the distribution Er. Thereby, the memory cells are programmed to four levels by the Lower page data and the Middle page data.

Also, as shown in (T83) in FIG. 34, in the 2nd stage program, two pages, an Upper page and a Higher page, are required for writing data. Then, the control unit 22 of the nonvolatile memory 2 programs the threshold distribution after programming in the 2nd stage so that the final state in which each adjacent distribution is separated has 16 levels. In this case, all page data can be read.

FIG. 35 shows data coding corresponding to the threshold distribution shown in FIG. In the data coding shown in FIG. 35, for example, a memory cell whose threshold voltage is in the Er1 area stores "1111" as the data value of bits corresponding to the Upper, Middle, Lower, and Higher pages. be. A memory cell whose threshold voltage is within the A1 area stores "0111".

Also, the threshold distribution shown in FIG. 36 and the data coding shown in FIG. 37 correspond to 1-2-6-6 coding. In 1-2-6-6 coding, the number of boundaries for determining bit values is 1, 2, 6, 6 for the Lower page, Middle page, Upper page, and Higher page, respectively.

FIG. 36 is a diagram of a third example showing the threshold distribution after programming in the sixth embodiment. (T91) in FIG. 36 shows the threshold distribution in the erased state, which is the initial state before programming. (T92) in FIG. 36 shows the threshold distribution after programming of the 1st stage. (T93) in FIG. 36 shows the threshold distribution after the programming of the 2nd stage.

As shown in (T91) of FIG. 36, all memory cells of the NAND memory cell array 23 have distribution Er in the unwritten state. As shown in (T92) of FIG. 36, the control unit 22 of the nonvolatile memory 2 maintains the distribution Er for each memory cell according to the bit values written to the Lower page and Middle page in the 1st stage program. , or inject charge to move it to a distribution above the distribution Er. Thereby, the memory cells are programmed to four levels by the Lower page data and the Middle page data.

In addition, as shown in (T93) of FIG. 36, in the program of the 2nd stage, two pages, an Upper page and a Higher page, are required for writing data. Then, the control unit 22 of the nonvolatile memory 2 programs the threshold distribution after programming in the 2nd stage so that the final state in which each adjacent distribution is separated has 16 levels. In this case, all page data can be read.

FIG. 37 shows data coding corresponding to the threshold distribution shown in FIG. In the data coding shown in FIG. 37, for example, a memory cell whose threshold voltage is in the Er1 area stores "1111" as the data value of bits corresponding to the Upper, Middle, Lower, and Higher pages. be. A memory cell whose threshold voltage is within the B1 region stores "0011".

Also in this embodiment, the program is executed and each page data is read by the same processing as in the first to fifth embodiments.

As described above, in the sixth embodiment, page-based writing is performed in two stages on the 4-bit/cell nonvolatile memory 2 having a three-dimensional structure or a two-dimensional structure. It is possible to obtain the same effect as the form.

Note that the first to sixth embodiments may be combined. For example, at least one of the second to fourth embodiments may be combined with the fourth or fifth embodiment.

Also, in the first to sixth embodiments, the case where the nonvolatile memory 2 is configured using a NAND memory has been described, but other types of memory may be used. Further, in the first to fifth embodiments, the nonvolatile memory 2 applies 1-3-3 coding, but the coding applied by the nonvolatile memory 2 is limited to 1-3-3 coding. do not have. For example, the non-volatile memory 2 may apply 1-2-4 coding or 2-3-2 coding.

7, 12, 17, 19, and 29, the read levels (Vr1, Vr4) before the 2nd stage write and after the 2nd stage write are the read levels (T3) after the 2nd stage write (T3). Vr1, Vr4) may be slightly different. Also, the read levels (Vr1, Vr3, Vr5, Vr7) before the 2nd stage write and after the 2nd stage write described with reference to FIGS. , Vr7).

While several embodiments of the invention have been described, these embodiments have been presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and modifications can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and equivalents thereof.

DESCRIPTION OF SYMBOLS 1... Memory controller, 2... Non-volatile memory, 11... RAM, 12... Processor, 22... Control part, 23... NAND memory cell array, FC... Flag cell, MT... Memory cell transistor.

Claims (5)

host and
A first threshold region indicating an erased state in which data is erased, and second to sixteenth threshold values indicating a written state in which data is written with a voltage level higher than that of the first threshold region. A non-volatile memory having a plurality of memory cells capable of storing 4-bit data represented by the first to fourth bits by means of 16 threshold regions in total, and a write request received from the host. a second program for writing the data of the third bit and the fourth bit after causing the nonvolatile memory to execute the first program for writing the data of the first bit and the second bit; a memory system having a memory controller that causes the
with
The memory controller comprises: a seventeenth threshold region indicating an erased state in which data is erased according to the data of the first bit and the second bit; 18th to 20th threshold regions indicating a write state in which data is written with a voltage level higher than that of the threshold region 17; is configured to cause the non-volatile memory to perform
The memory controller sets the threshold region of the memory cell to any one of the 17th to 20th threshold regions according to the data of the 3rd bit and the 4th bit. configured to cause the non-volatile memory to perform the second program to be in any one of the first to sixteenth threshold regions from the region;
the n-th threshold region has a higher voltage level than the (n-1)th threshold region (n is a natural number of 2 or more and 16 or less);
the kth threshold region has a higher voltage level than the (k-1)th threshold region (k is a natural number between 18 and 20);
The memory controller converts the threshold region in the memory cell from the 17th threshold region to the 1st to 16th threshold values according to the data of the 3rd bit and the 4th bit. When the second programming is performed on the non-volatile memory so as to be any threshold value region among the regions, four twenty-first threshold regions among the first to sixteenth threshold regions configured to cause the non-volatile memory to perform the second program so as to be in any one of the threshold regions;
The memory controller converts the threshold region in the memory cell from the 18th threshold region to the 1st to 16th threshold values according to the data of the 3rd bit and the 4th bit. When the second programming is performed on the non-volatile memory so as to be any threshold value region among the regions, four 22nd threshold regions among the first to sixteenth threshold regions configured to cause the non-volatile memory to perform the second program so as to be in any one of the threshold regions;
The memory controller converts the threshold region in the memory cell from the 19th threshold region to the 1st to 16th threshold values according to the data of the 3rd bit and the 4th bit. When the second programming is performed on the non-volatile memory so as to be any threshold value region among the regions, four twenty-third threshold regions among the first to sixteenth threshold regions configured to cause the non-volatile memory to perform the second program so as to be in any one of the threshold regions;
The memory controller converts the threshold region in the memory cell from the twentieth threshold region to the first to sixteenth threshold values according to the data of the third bit and the fourth bit. When the second programming is performed on the non-volatile memory so as to be any threshold value region among the regions, the four twenty-fourth threshold regions among the first to sixteenth threshold regions configured to cause the non-volatile memory to perform the second program so as to be in any one of the threshold regions;
The threshold regions of the four twenty-third threshold regions and the threshold regions of the four twenty-fourth threshold regions are all of the four twenty-first threshold regions voltage level higher than any of the threshold regions of
The threshold regions of the four twenty-third threshold regions and the threshold regions of the four twenty-fourth threshold regions are all of the four twenty-second threshold regions voltage level higher than any of the threshold regions of
the four twenty-second threshold regions are four consecutive threshold regions among the first to sixteenth threshold regions;
the four twenty-fourth threshold regions are four consecutive threshold regions among the first to sixteenth threshold regions;
the four twenty-first threshold regions are four consecutive threshold regions among the first to sixteenth threshold regions;
the four twenty-third threshold regions are four consecutive threshold regions among the first to sixteenth threshold regions;
any threshold region of the four twenty-second threshold regions has a higher voltage level than any threshold region of the four twenty-first threshold regions;
any of the four twenty-fourth threshold regions has a higher voltage level than any of the four twenty-third threshold regions;
the number of first boundaries used to determine the value of the data of the first bit among 15 boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions; The number of second boundaries used to determine the value of the data of the second bit, the number of third boundaries used to determine the value of the data of the third bit, and the value of the data of the fourth bit the number of fourth boundaries used in is 1, 2, 6, 6 in order,
Information processing system. host and
A first threshold region indicating an erased state in which data is erased, and second to sixteenth threshold values indicating a written state in which data is written with a voltage level higher than that of the first threshold region. A non-volatile memory having a plurality of memory cells capable of storing 4-bit data represented by the first to fourth bits by means of 16 threshold regions in total, and a write request received from the host. a second program for writing the data of the third bit and the fourth bit after causing the nonvolatile memory to execute the first program for writing the data of the first bit and the second bit; a memory system having a memory controller that causes the
with
The memory controller comprises: a seventeenth threshold region indicating an erased state in which data is erased according to the data of the first bit and the second bit; 18th to 20th threshold regions indicating a write state in which data is written with a voltage level higher than that of the threshold region 17; is configured to cause the non-volatile memory to perform
The memory controller sets the threshold region of the memory cell to any one of the 17th to 20th threshold regions according to the data of the 3rd bit and the 4th bit. configured to cause the non-volatile memory to perform the second program to be in any one of the first to sixteenth threshold regions from the region;
the n-th threshold region has a higher voltage level than the (n-1)th threshold region (n is a natural number of 2 or more and 16 or less);
the kth threshold region has a higher voltage level than the (k-1)th threshold region (k is a natural number between 18 and 20);
The memory controller converts the threshold region in the memory cell from the 17th threshold region to the 1st to 16th threshold values according to the data of the 3rd bit and the 4th bit. When the second programming is performed on the non-volatile memory so as to be any threshold value region among the regions, four twenty-first threshold regions among the first to sixteenth threshold regions configured to cause the non-volatile memory to perform the second program so as to be in any one of the threshold regions;
The memory controller converts the threshold region in the memory cell from the 18th threshold region to the 1st to 16th threshold values according to the data of the 3rd bit and the 4th bit. When the second programming is performed on the non-volatile memory so as to be any threshold value region among the regions, four 22nd threshold regions among the first to sixteenth threshold regions configured to cause the non-volatile memory to perform the second program so as to be in any one of the threshold regions;
The memory controller converts the threshold region in the memory cell from the 19th threshold region to the 1st to 16th threshold values according to the data of the 3rd bit and the 4th bit. When the second programming is performed on the non-volatile memory so as to be any threshold value region among the regions, four twenty-third threshold regions among the first to sixteenth threshold regions configured to cause the non-volatile memory to perform the second program so as to be in any one of the threshold regions;
The memory controller converts the threshold region in the memory cell from the twentieth threshold region to the first to sixteenth threshold values according to the data of the third bit and the fourth bit. When the second programming is performed on the non-volatile memory so as to be any threshold value region among the regions, the four twenty-fourth threshold regions among the first to sixteenth threshold regions configured to cause the non-volatile memory to perform the second program so as to be in any one of the threshold regions;
The threshold regions of the four twenty-third threshold regions and the threshold regions of the four twenty-fourth threshold regions are all of the four twenty-first threshold regions voltage level higher than any of the threshold regions of
The threshold regions of the four twenty-third threshold regions and the threshold regions of the four twenty-fourth threshold regions are all of the four twenty-second threshold regions voltage level higher than any of the threshold regions of
the four twenty-second threshold regions are four consecutive threshold regions among the first to sixteenth threshold regions;
the four twenty-fourth threshold regions are four consecutive threshold regions among the first to sixteenth threshold regions;
The continuous four twenty-second threshold regions have a lower voltage level than one threshold region of the four twenty-first threshold regions, and the four twenty-first threshold regions a higher voltage level than the remaining three of the threshold regions;
Information processing system. The continuous four twenty-fourth threshold regions have a lower voltage level than one threshold region of the four twenty-third threshold regions, and the four twenty-third threshold regions 3. The information handling system of claim 2, wherein the voltage level is higher than the remaining three of the threshold regions. the number of first boundaries used to determine the value of the data of the first bit among 15 boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions; The number of second boundaries used to determine the value of the data of the second bit, the number of third boundaries used to determine the value of the data of the third bit, and the value of the data of the fourth bit 4. An information processing system according to claim 2 or 3, wherein the number of fourth boundaries used for is 1, 4, 5, 5 in order. The memory controller reads the data written by the first program from the nonvolatile memory after causing the first program to be executed in the nonvolatile memory, corrects the error in the read data, and corrects the error. 4. The non-volatile memory is configured to execute the second program using the data and the data of the third bit and the fourth bit. The information processing system according to any one of the items.

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