CN112825026B

CN112825026B - Memory system

Info

Publication number: CN112825026B
Application number: CN202010848525.6A
Authority: CN
Inventors: 原德正; 柴田升
Original assignee: Kioxia Corp
Current assignee: Kioxia Corp
Priority date: 2019-11-21
Filing date: 2020-08-21
Publication date: 2023-08-18
Anticipated expiration: 2040-08-21
Also published as: TW202331729A; TWI752569B; CN116954520A; CN112825026A; JP2022002160A; TW202121426A; TW202213363A; JP7414669B2; TWI802140B

Abstract

Embodiments provide a memory system capable of reducing a write buffer capacity and suppressing bit error rate variation while avoiding inter-cell interference. In a memory system, a memory controller within the memory system: the nonvolatile memory is programmed 1 st so that a threshold region in the memory cell becomes a 17 th threshold region indicating an erased state in which data has been erased, and a certain threshold region of 18 th to 24 th threshold regions indicating a written state in which data has been written, which are higher in voltage level than the 17 th threshold region, in accordance with the 1 st bit, 2 nd bit, and 4 th bit data, and the nonvolatile memory is programmed 2 nd so that the threshold region in the memory cell is changed from the certain threshold region of 17 th to 24 th threshold regions to a certain threshold region of two of the 1 st to 16 th threshold regions in accordance with the 3 rd bit data, and in the case of programming the nonvolatile memory 2 nd bit, the 2 nd and 3 rd bit data are input to the nonvolatile memory.

Description

Memory system

The present application enjoys priority of Japanese patent application No. 2019-210823 (application date: 11/21/year of 2019) and Japanese patent application No. 2020-113206 (application date: 30/year of 2020). The present application includes the entire contents of the basic application by reference to these basic applications.

Technical Field

Embodiments of the present disclosure relate to memory systems (memory systems).

Background

In a NAND flash memory (flash memory), a TLC (Triple Level Cell, three-level cell) technology is now put into practical use, in which multi-value data formed of a plurality of bits (bits) is generally written into a memory cell (memory cell), and multi-value data formed of 3 bits is written into the memory cell. In the future, QLC (Quadruple Level Cell, four-level cell) technology for writing multi-value data formed of 4 bits will become the mainstream.

In QLC, in order to avoid inter-cell interference, the following methods have been studied: after simultaneously writing 4-bit data into the 1 st memory cell, similarly, 4-bit data is simultaneously written into the adjacent cell, and thereafter, 4-bit data is simultaneously rewritten into the 1 st memory cell again. However, in this method, a write buffer (buffer) holding 4-bit data within the memory controller (memory controller) is required before the re-write is completed.

In recent years, NAND memories have been three-dimensionally formed, and there are problems as follows: the memory capacity of the write buffer required increases, and the cost of the memory controller incorporating the write buffer increases. Therefore, in a three-dimensional nonvolatile memory, a countermeasure for reducing the write buffer amount of the memory controller is also required.

As a countermeasure for reducing the write buffer amount of the memory controller while avoiding the inter-cell interference, the following method is known: when writing data of each bit to a memory cell, the data is written in two stages (stages), and thus, it is not necessary to rewrite all bits of data.

However, this method has a problem that a bit error rate (bit error rate) is large when writing each bit of data to a memory cell.

In order to improve the reliability of the QLC technique, it is necessary to avoid inter-cell interference, reduce the capacity of a write buffer in a memory controller, and suppress the variation in bit error rate when writing data of each bit.

Disclosure of Invention

One embodiment of the present disclosure provides a memory system capable of reducing the capacity of a write buffer in a memory controller while avoiding inter-cell interference and suppressing variations in bit error rate when writing data of each bit.

According to the present embodiment, there is provided a memory system including: a nonvolatile memory having a plurality of memory cells each capable of storing 4-bit data represented by 1 st to 4 th bits with 16 threshold regions including a 1 st threshold region indicating an erased state in which data has been erased and 2 nd to 16 th threshold regions indicating a written state in which data has been written, the voltage level (level) of which is higher than that of the 1 st threshold region; and a memory controller configured to cause the nonvolatile memory to perform 2 nd programming (program) in which the 3 rd bit data is written after the nonvolatile memory is caused to perform 1 st programming (program) in which the 1 st bit, the 2 nd bit, and the 4 th bit data are written, the largest value among 15 boundaries between adjacent ones of the 1 st threshold region and the 16 th threshold region, the number of 1 st boundaries used for determining the value of the 1 st bit data, the number of 2 nd boundaries used for determining the value of the 2 nd bit data, the number of 3 rd boundaries used for determining the value of the 3 rd bit data, and the number of 4 th boundaries used for determining the value of the 4 th bit data, is 5, the second largest value is 4, the memory controller being configured to cause the nonvolatile memory to perform the 1 st programming, so that a threshold region in the memory cell becomes a 17 th threshold region representing an erased state in which data has been erased, and a certain threshold region from an 18 th threshold region to a 24 th threshold region representing a written state in which data has been written, which are higher in voltage level than the 17 th threshold region, in accordance with the 1 st bit, the 2 nd bit, and the 4 th bit data, the memory controller is configured to cause the nonvolatile memory to perform the 2 nd programming so that a threshold region in the memory cell becomes a certain threshold region from the 17 th threshold region to the 24 th threshold region, in accordance with the 3 rd bit data, from the 1 st threshold region to a certain threshold region from two threshold regions from the 16 th threshold region, the number of threshold regions between the threshold region having the lowest voltage level and the threshold region having the highest voltage level of the two threshold regions is equal to or less than two, and the memory controller is configured to input the 2 nd bit data and the 3 rd bit data to the nonvolatile memory when the nonvolatile memory is subjected to the 2 nd programming.

Drawings

Fig. 1 is a block diagram showing a schematic configuration of a memory system according to embodiment 1.

Fig. 2 is a block diagram showing an example of the internal configuration of the nonvolatile memory according to the present embodiment.

Fig. 3 is a circuit diagram showing an example of a NAND memory cell array having a three-dimensional structure.

Fig. 4 is a cross-sectional view of a part of an area of a NAND memory cell array of a three-dimensional structure NAND memory.

Fig. 5 is a diagram showing an example of the threshold region in embodiment 1.

Fig. 6A is a diagram showing an example of data encoding (data coding) according to embodiment 1.

Fig. 6B is a diagram showing another example of data encoding according to embodiment 1.

Fig. 7 is a diagram showing the programmed threshold regions in embodiment 1.

Fig. 8A is a diagram showing example 1 of the programming sequence of embodiment 1.

Fig. 8B is a diagram showing example 2 of the programming sequence of embodiment 1.

Fig. 8C is a diagram showing example 3 of the programming sequence of embodiment 1.

Fig. 9 is a flowchart showing example 1 of a writing step (writing flow) of the entire amount of one block (block) according to embodiment 1.

Fig. 10 is a flowchart showing a writing procedure in the first stage (1 st stage) of embodiment 1.

Fig. 11 is a flowchart showing example 1 of the writing procedure in the second stage (2 nd stage).

Fig. 12 is a diagram for explaining the selection processing of the read result of a plurality of times.

Fig. 13 is a flowchart showing a modification of the second-stage writing step according to embodiment 1.

FIG. 14A is a diagram illustrating the amount of data written to a buffer in Foggy-Fine programming using 4-3-4-4 data encoding.

Fig. 14B is a diagram illustrating the data amount of the write buffer in the present embodiment.

Fig. 15 is a flowchart showing the processing steps of page (page) reading on a word line where programming has been completed to the first stage.

Fig. 16A is a flowchart showing the processing steps of page reading on the word line where programming has been completed to the second stage.

Fig. 16B is a diagram showing data encoding suitable for page reading processing based on a modification.

Fig. 16C is a flowchart showing a read processing procedure according to a modification.

Fig. 16D is a voltage waveform diagram of a selected word line, a ReadyBusy signal line, and an output data line.

FIG. 17 is a diagram showing an example of 1-5-4-5 data encoding.

FIG. 18 is a diagram showing an example of 1-5-4-5 data encoding.

FIG. 19 is a diagram showing an example of 3-5-2-5 data encoding.

FIG. 20 is a diagram showing an example of 3-3-4-5 data encoding.

FIG. 21 is a diagram showing an example of 2-3-5-5 data encoding.

Fig. 22 is a diagram showing an example of 3-2-5-5 data encoding.

Fig. 23 is a diagram showing an example of 3-4-4-4 data encoding.

Fig. 24 is a diagram showing an example of 3-4-4-4 data encoding.

FIG. 25 is a diagram showing an example of 1-4-5-5 data encoding.

Fig. 26 is a diagram showing an example of 2-5-3-5 data encoding.

FIG. 27 is a diagram showing an example of 3-4-5-3 data encoding.

Fig. 28 is a diagram showing an example of 3-2-5-5 data encoding.

Fig. 29 is a diagram showing an example of 3-2-5-5 data encoding.

FIG. 30 is a diagram showing an example of 1-5-5-4 data encoding.

FIG. 31 is a diagram showing an example of 1-5-4-5 data encoding.

FIG. 32 is a diagram showing an example of 1-4-5-5 data encoding.

FIG. 33 is a diagram showing an example of 1-5-3-6 data encoding.

FIG. 34 is a diagram showing an example of 1-3-6-5 data encoding.

FIG. 35 is a diagram showing an example of encoding 1-2-6-6 data.

FIG. 36 is a diagram showing an example of 1-2-6-6 data encoding.

FIG. 37 is a diagram showing an example of 1-2-6-6 data encoding.

FIG. 38 is a diagram showing an example of 1-4-6-4 data encoding.

FIG. 39 is a diagram showing an example of 1-4-4-6 data encoding.

FIG. 40 is a diagram showing an example of 1-4-6-4 data encoding.

FIG. 41 is a diagram showing an example of 1-4-4-6 data encoding.

Fig. 42 is a diagram showing an example of 2-5-2-6 data encoding.

FIG. 43 is a diagram showing an example of 2-5-2-6 data encoding.

Fig. 44 is a diagram showing an example of 2-5-2-6 data encoding.

Fig. 45 is a diagram showing an example of 3-3-3-6 data encoding.

FIG. 46 is a diagram showing an example of 3-3-6-3 data encoding.

FIG. 47 is a diagram showing an example of 2-3-4-6 data encoding.

Fig. 48 is a diagram showing an example of 3-4-2-6 data encoding.

Fig. 49 is a diagram showing an example of 2-3-4-6 data encoding.

FIG. 50 is a diagram showing an example of 3-2-6-4 data encoding.

Fig. 51 is a diagram showing an example of 3-2-4-6 data encoding.

Fig. 52 is a diagram showing an example of 3-2-6-4 data encoding.

FIG. 53 is a diagram showing an example of encoding 3-4-2-6 data.

Fig. 54 is a diagram showing an example of 3-2-4-6 data encoding.

Fig. 55 is a diagram showing an example of 5-3-2-5 data encoding.

Fig. 56 is a diagram showing an example of 3-5-2-5 data encoding.

Fig. 57 is a diagram showing an example of 3-2-5-5 data encoding.

Fig. 58 is a diagram showing an example of 2-3-5-5 data encoding.

FIG. 59 is a diagram showing an example of 2-3-5-5 data encoding.

FIG. 60 is a diagram showing an example of 2-3-5-5 data encoding.

Fig. 61 is a diagram showing an example of 5-4-2-4 data encoding.

Fig. 62 is a diagram showing an example of 4-5-2-4 data encoding.

Fig. 63 is a diagram showing an example of 5-4-2-4 data encoding.

Fig. 64 is a diagram showing an example of 2-4-5-4 data encoding.

Fig. 65 is a diagram showing an example of 2-4-5-4 data encoding.

FIG. 66 is a diagram showing an example of 2-5-4-4 data encoding.

Fig. 67 is a diagram showing an example of 2-5-4-4 data encoding.

Fig. 68 is a diagram showing an example of 2-5-4-4 data encoding.

FIG. 69 is a diagram showing an example of 1-5-4-5 data encoding.

FIG. 70 is a diagram showing an example of 1-4-5-5 data encoding.

FIG. 71 is a diagram showing an example of 1-5-5-4 data encoding.

FIG. 72 is a diagram showing an example of 1-4-5-5 data encoding.

FIG. 73 is a diagram showing an example of encoding 1-5-5-4 data.

FIG. 74 is a diagram showing an example of 1-5-4-5 data encoding.

FIG. 75 is a diagram showing an example of encoding 1-5-5-4 data.

FIG. 76 is a diagram showing an example of 1-5-4-5 data encoding.

FIG. 77 is a diagram showing an example of 1-4-5-5 data encoding.

FIG. 78 is a diagram showing an example of encoding 1-4-5-5 data.

FIG. 79 is a diagram showing an example of 1-4-5-5 data encoding.

FIG. 80 is a diagram showing an example of 1-4-5-5 data encoding.

FIG. 81 is a diagram showing an example of 3-5-4-3 data encoding.

Fig. 82 is a diagram showing an example of 3-4-5-3 data encoding.

Fig. 83 is a diagram showing an example of 3-5-3-4 data encoding.

Fig. 84 is a diagram showing an example of 3-4-3-5 data encoding.

FIG. 85 is a diagram showing an example of 3-4-5-3 data encoding.

Fig. 86 is a diagram showing an example of 3-4-3-5 data encoding.

FIG. 87 is a diagram showing an example of encoding 3-3-5-4 data.

Fig. 88 is a diagram showing an example of 3-3-5-4 data encoding.

FIG. 89 is a diagram showing an example of 4-5-3-3 data encoding.

FIG. 90 is a diagram showing an example of 3-5-4-3 data encoding.

FIG. 91 is a diagram showing an example of 3-4-5-3 data encoding.

Fig. 92 is a diagram showing an example of 3-3-4-5 data encoding.

Fig. 93 is a diagram showing an example of 3-3-4-5 data encoding.

Fig. 94 is a diagram showing an example of 3-3-4-5 data encoding.

FIG. 95 is a diagram showing an example of 3-4-5-3 data encoding.

FIG. 96 is a diagram showing an example of 3-3-5-4 data encoding.

FIG. 97 is a diagram showing an example of 3-3-4-5 data encoding.

Fig. 98 is a diagram showing an example of 4-3-4-4 data encoding.

FIG. 99 is a diagram showing an example of 3-4-4-4 data encoding.

Fig. 100 is a diagram showing an example of 3-4-4-4 data encoding.

Fig. 101 is a diagram showing an example of 4-3-4-4 data encoding.

Fig. 102 is a diagram showing an example of 3-4-4-4 data encoding.

Fig. 103 is a diagram showing an example of 3-4-4-4 data encoding.

Fig. 104 is a diagram showing an example of 3-4-4-4 data encoding.

Fig. 105 is a diagram showing an example of 3-4-4-4 data encoding.

Fig. 106 is a diagram showing an example of 4-4-3-4 data encoding.

Fig. 107 is a diagram showing an example of 4-4-3-4 data encoding.

Fig. 108 is a flowchart showing a procedure of writing the entire amount of one block according to embodiment 3.

Fig. 109 is a flowchart showing the writing procedure in the first and second stages according to embodiment 3.

Fig. 110 is a diagram for explaining the write buffer amount in programming according to embodiment 3.

Description of the reference numerals

1 a memory system; 2 a memory controller; 3 a nonvolatile memory; a host processor (host processor); a 5NAND memory; 6RAM (random access memory); 7ROM (read Only memory); 8, a processor; a host interface (host interface); a 10ECC circuit; 11 memory interface (memory interface); 12 an internal bus; a 21NAND I/O interface; 22 control part; a 23NAND memory cell array; a 24 page buffer (page buffer); 31 an oscillator; 32 sequencer (sequencer); a 33 command user interface (command user interface); a 34 voltage supply unit; a 35 column counter (column counter); a 36 serial access controller (serial access controller); a 37 row decoder (row decoder); a sense amplifier (sense amplifier) 38; 41P-type well regions (P-wells); 42. 43, 44 wiring layers; 45 memory holes; a 46-block insulating film; a 47 charge accumulation layer; 48 gate (gate) insulating film; 49 conductive film.

Detailed Description

Fig. 1 is a block diagram showing a schematic configuration of a memory system 1 according to embodiment 1. The memory system 1 of fig. 1 includes a memory controller 2 and a nonvolatile memory 3. The memory system 1 of fig. 1 can be connected to a host processor (hereinafter, simply referred to as a host) 4. The host computer 4 is an electronic device such as a personal computer or a mobile terminal.

The nonvolatile memory 3 is a memory that stores data in a nonvolatile manner, and includes, for example, a NAND flash memory (hereinafter, also referred to as a NAND memory) 5. In this embodiment, an example will be described in which the nonvolatile memory 3 is a 4-bit/Cell (QLC) NAND memory 5 having memory cells capable of storing 4-bit data for each memory Cell. The nonvolatile memory 3 of the present embodiment has a three-dimensional structure in which memory cells are stacked in three dimensions. The nonvolatile memory 3 has a plurality of memory cells each capable of storing 4-bit data represented by 1 st to 4 th bits with 16 threshold regions including a 1 st threshold region indicating an erased state in which data has been erased, and 2 nd to 16 th threshold regions indicating a written state in which data has been written, which are higher in voltage level than the 1 st threshold region. For example, bit 1 is the Lower bit (Lower bit), bit 2 is the next Lower Middle bit (Middle bit), bit 3 is the next higher Upper bit (Upper bit), and bit 4 is the first bit (Top bit) of the highest bit.

The memory controller 2 controls writing of data to the nonvolatile memory 3 in accordance with a write command from the host 4. In addition, the memory controller 2 controls data reading from the nonvolatile memory 3 in accordance with a read command from the host 4. The memory controller 2 includes RAM (Random Access Memory), ROM (Read Only Memory), a processor 8, a host interface 9, an ECC (Error Check and Correct, error checking and correction) circuit 10, and a memory interface 11. The RAM6, the processor 8, the host interface 9, the ECC circuit 10, and the memory interface 11 are connected via a common internal bus 12.

As described later, the memory controller 2 of the present embodiment causes the nonvolatile memory 3 to perform the 1 st program for writing the 1 st, 2 nd, and 4 th bit data, and then causes the nonvolatile memory 3 to perform the 2 nd program for writing the 3 rd bit data. The largest value among the 15 boundaries existing between adjacent threshold regions of the 1 st to 16 th threshold regions, out of the number of 1 st boundaries used to determine the value of the 1 st bit data, the number of 2 nd boundaries used to determine the value of the 2 nd bit data, the number of 3 rd boundaries used to determine the value of the 3 rd bit data, and the number of 4 th boundaries used to determine the value of the 4 th bit data, is 5, and the second largest value is 4. The memory controller 2 is configured to cause the nonvolatile memory 3 to perform 1 st programming such that a threshold region in a memory cell becomes a 17 th threshold region indicating an erased state in which data has been erased, and any one of 18 th to 24 th threshold regions indicating a written state in which data has been written, which have a higher voltage level than the 17 th threshold region, in accordance with the 1 st bit, 2 nd bit, and 4 th bit data. The memory controller 2 is configured to cause the nonvolatile memory 3 to perform 2 nd programming so that a threshold region in the memory cell becomes a certain threshold region among two threshold regions from 1 st to 16 th threshold regions from a certain threshold region from 17 th to 24 th threshold regions according to 3 rd bit data. The number of threshold regions between the threshold region having the lowest voltage level and the threshold region having the highest voltage level among the two threshold regions is within two. The memory controller 2 is configured to input the 2 nd bit data and the 3 rd bit data to the nonvolatile memory 3 when the nonvolatile memory 3 is subjected to the 2 nd programming.

In more detail, the memory controller 2 causes the nonvolatile memory to perform 1 st programming and 2 nd programming such that, among 15 boundaries between 16 threshold regions (1 st to 16 th threshold regions), the number of boundaries in which the value of 1 st bit differs, the number of boundaries in which the value of 2 nd bit differs, the number of boundaries in which the value of 3 rd bit differs, and the number of boundaries in which the value of 4 th bit differs are sequentially 1, 4, 5, or 1, 5, 4, 5, or 3, 4, 5.

Alternatively, the memory controller 2 of the present embodiment causes the nonvolatile memory 3 to perform the 1 st program for writing the 1 st, 2 nd, and 4 th bit data, and then causes the nonvolatile memory 3 to perform the 2 nd program for writing the 3 rd bit data. The number of 1 st boundaries used to determine the value of the 1 st bit data, the number of 2 nd boundaries used to determine the value of the 2 nd bit data, the number of 3 rd boundaries used to determine the value of the 3 rd bit data, and the number of 4 th boundaries used to determine the value of the 4 th bit data, which are present in 15 boundaries between adjacent threshold regions of the 1 st to 16 th threshold regions, are 3, 5, 2, 5 in this order. The memory controller 2 is configured to cause the nonvolatile memory 3 to perform 1 st programming such that a threshold region in a memory cell becomes a 17 th threshold region indicating an erased state in which data has been erased, and any one of 18 th to 24 th threshold regions indicating a written state in which data has been written, which have a higher voltage level than the 17 th threshold region, in accordance with the 1 st bit, 2 nd bit, and 4 th bit data. The memory controller 2 is configured to cause the nonvolatile memory 3 to perform 2 nd programming so that a threshold region in the memory cell becomes a certain threshold region among two threshold regions from 1 st to 16 th threshold regions from a certain threshold region from 17 th to 24 th threshold regions according to 3 rd bit data. The number of threshold regions between the threshold region having the lowest voltage level and the threshold region having the highest voltage level among the two threshold regions is within two. The memory controller 2 is configured to input the 2 nd bit data and the 3 rd bit data to the nonvolatile memory 3 when the nonvolatile memory 3 is subjected to the 2 nd programming.

The memory controller 2 may also cause the nonvolatile memory to perform 1 st programming such that a difference in voltage level between two threshold regions different in value from the 2 nd bit data among the 17 th to 24 th threshold regions is smaller than a difference in voltage level between two threshold regions different in value from the 1 st bit data and smaller than a difference in voltage level between two threshold regions different in value from the 4 th bit data.

Alternatively, the memory controller 2 may cause the nonvolatile memory to perform the 2 nd programming so that the interval between adjacent threshold regions among 4 threshold regions obtained by performing the 2 nd programming with the 3 rd bit data for the two threshold regions is wider than the interval between the two threshold regions at the 1 st programming in which the values of the 2 nd bit data are different.

The host interface 9 outputs a command, user data (write data), and the like received from the host 4 to the internal bus 12. The host interface 9 transmits the user data read from the nonvolatile memory 3, the response from the processor 8, and the like to the host 4.

The memory interface 11 controls processing of writing user data or the like into the nonvolatile memory 3 and processing of reading from the nonvolatile memory 3 based on an instruction of the processor 8.

The processor 8 controls the memory controller 2 as a whole. The processor 8 is, for example, CPU (Central Processing Unit), MPU (Micro Processing Unit), or the like. The processor 8, upon receiving a command from the host 4 via the host interface 9, performs control in accordance with the command. For example, the processor 8 instructs the memory interface 11 to write user data and parity (parity) into the nonvolatile memory 3 in accordance with a command from the host 4. The processor 8 instructs the memory interface 11 to read the user data and parity from the nonvolatile memory 3 in accordance with a command from the host 4.

The user data is stored in the RAM6 via the internal bus 12. The processor 8 determines a storage area (memory area) in the nonvolatile memory 3 for the user data stored in the RAM6. The processor 8 determines a storage area on the nonvolatile memory 3 for data (page data) in units of pages as writing units. In this specification, user data held by one page of the nonvolatile memory 3 is defined as module data (unit data). The module data is typically encoded and stored as codewords in the non-volatile memory 3, but encoding is not required. The memory controller 2 may store the block data in the nonvolatile memory 3 without encoding the block data, but fig. 1 shows a configuration for encoding as an example. The page data coincides with the module data without being encoded by the memory controller 2. In addition, one codeword may be generated based on one block data, or one codeword may be generated based on divided data obtained by dividing the block data. In addition, a codeword may be generated using a plurality of module data.

The processor 8 determines a storage area of the nonvolatile memory 3 to be written for each block data. A physical address is allocated to a storage area of the nonvolatile memory 3. The processor 8 manages a storage area of the write destination of the module data using the physical address. The processor 8 designates the decided storage area (physical address) and instructs the memory interface 11 to write the user data to the nonvolatile memory 3. On the other hand, the host 4 manages data with logical addresses. Thus, the processor 8 manages the correspondence of the logical address and the physical address of the user data. The processor 8, upon receiving a read command including a logical address from the host 4, determines a physical address corresponding to the logical address, designates the physical address, and instructs the memory interface 11 to read user data.

In this specification, a plurality of memory cells commonly connected to one word line is defined as a memory cell group MG. One memory cell group MG is a unit of writing (programming). In the present embodiment, the nonvolatile memory 3 is a 4-bit/cell NAND memory 5, and one memory cell group MG has a data amount of 4 bits×cell number. The bits written to each memory cell correspond to different pages. In the present embodiment, 4 pages of one memory cell group MG are referred to as Lower page (Lower page) (page 1), middle page (Middle page) (page 2), upper page (Upper page) (page 3), and Top page (Top page) (page 4).

The ECC circuit 10 encodes the user data stored in the RAM6 to generate a codeword. In addition, the ECC circuit 10 decodes the codeword read from the nonvolatile memory 3. The ECC circuit 10 corrects an error code (bit error) included in the codeword read from the nonvolatile memory 3, and then decodes the codeword into user data.

The RAM6 temporarily holds user data received from the host 4 until it is stored in the nonvolatile memory 3, and temporarily holds data read from the nonvolatile memory 3 until it is transmitted to the host 4. The RAM6 is a general-purpose memory such as SRAM (Static Random Access Memory ) and DRAM (Dynamic Random Access Memory, dynamic random access memory).

Fig. 1 shows an example of a configuration in which the memory controller 2 includes an ECC circuit 10 and a memory interface 11, respectively. However, the ECC circuit 10 may be built in the memory interface 11. The ECC circuit 10 may be incorporated in the nonvolatile memory 3.

In the case of receiving a write request from the host 4, the memory system 1 operates as follows. The processor 8 temporarily saves the write data in the RAM6. The processor 8 reads the data stored in the RAM6 and inputs the data to the ECC circuit 10. The ECC circuit 10 encodes the input data and inputs the codeword to the memory interface 11. The memory interface 11 writes the entered codeword to the non-volatile memory 3.

In the case of receiving a read request from the host 4, the memory system 1 operates as follows. The memory interface 11 inputs the codeword read from the nonvolatile memory 3 to the ECC circuit 10. The ECC circuit 10 decodes the input codeword, and temporarily stores the decoded data in the RAM6. The processor 8 sends the data stored in the RAM6 to the host 4 via the host interface 9. In addition, the nonvolatile memory 3 may be constituted by a plurality of chips, and the nonvolatile memory 3 and the memory interface 11 may be connected by a through hole (TSV Through Silicon Via).

The memory controller 2 shown in fig. 1 is an example, and various derivatives may be employed in addition to this, for example, the internal bus 12 may be divided and/or layered, or additional functional blocks may be connected.

Fig. 2 is a block diagram showing an example of the internal configuration of the nonvolatile memory 3 according to the present embodiment. The nonvolatile memory 3 includes a NAND I/O interface 21, a control section 22, a NAND memory cell array (memory cell section) 23, and a page buffer (2 nd memory section) 24. The nonvolatile memory 3 is formed on a semiconductor substrate (for example, a silicon substrate) and is formed into a chip.

The control section 22 controls the operation of the nonvolatile memory 3 based on a command or the like from the memory controller 2 via the NAND I/O interface 21. Specifically, when a write request is input, the control unit 22 performs control to write the data requested to be written to the specified address on the NAND memory cell array 23. When a read request is input, the control unit 22 performs control to read the data requested to be read from the NAND memory cell array 23 and output the read data to the memory controller 2 via the NAND I/O interface 21. The page buffer 24 is a buffer that temporarily holds data input from the memory controller 2 at the time of writing of the NAND memory cell array 23 and temporarily holds data read from the NAND memory cell array 23.

As described later, the control unit 22 determines the threshold voltage of the bit data programmed in the second phase programming based on the data obtained by reading the data programmed in the first phase programming, the bit data repeatedly input in the first phase programming and the second phase programming, and the bit input data programmed in the second phase programming.

The control section 22 has an oscillator 31, a sequencer 32, a command user interface 33, a voltage supply section 34, a column counter 35, and a serial access controller 36. In addition, the NAND memory cell array 23 has a row decoder 37 and a sense amplifier 38.

The NAND I/O interface 21 is a circuit for transmitting/receiving an IO signal (input/output signal) and a control signal to/from the memory controller 2. The command user interface 33 obtains a command and an address from among commands, addresses, and data received from the memory controller 2 via the IO signal lines based on the control signal. The command user interface 33 gives the acquired command and address to the sequencer 32.

The oscillator 31 is a circuit that generates a clock. The clock generated by the oscillator 31 is supplied to each component including the sequencer 32. Sequencer 32 is a state machine driven by a clock supplied from oscillator 31. The sequencer 32 performs access or the like control to the NAND memory cell array 23. For example, the sequencer 32 issues instructions for controlling various internal voltages, operation timings (timings), and the like, in accordance with commands received from the command user interface 33. In addition, the sequencer 32 supplies the block address and the page address included in the address received from the command user interface 33 to the row decoder 37. Further, the sequencer 32 supplies a column address included in the address received from the command user interface 33 to the column counter 35.

The voltage supply unit 34 generates various internal voltages to be supplied to the word lines and various internal voltages to be supplied to the bit lines, and supplies them to the row decoder 37 and the sense amplifier 38. In the programming operation or the reading operation, the column counter 35 starts the column address supplied from the sequencer 32, and sequentially advances the column address in accordance with a control signal supplied from the serial access controller 36.

During programming, the page buffer 24 sequentially stores the data received from the serial access controller 36 in the column address area designated by the column counter 35. In addition, at the time of the reading operation, the page buffer 24 sequentially transmits the data of the column address specified by the above-mentioned column address among the stored data to the serial access controller 36.

In the programming operation, the serial access controller 36 saves data received in a serial manner from the NAND I/O interface 21 for each bit width of the IO signal line in the page buffer 24. In addition, at the time of the reading operation, the serial access controller 36 transmits data received in a serial manner from the page buffer 24 for each bit width of the IO signal line to the NAND I/O interface 21.

In the programming operation and the reading operation, the row decoder 37 decodes the block address and the page address, and selects a word line corresponding to the page to be accessed included in the block BLK to be accessed. Each row decoder 37 applies an appropriate voltage to the selected word line and the unselected word line.

During programming operation, sense amplifier 38 forwards the corresponding data stored in page buffer 24 to the memory cell transistors. In addition, at the time of a read operation, the sense amplifier 38 senses data read from the selected word line to the bit line, and stores the obtained data in the page buffer 24. The data stored in the page buffer 24 is sent to the memory controller 2 via the serial access controller 36 and the NAND I/O interface 21.

Fig. 3 is a circuit diagram showing an example of the NAND memory cell array 23 having a three-dimensional structure. Fig. 3 shows a circuit structure of one block BLK among a plurality of blocks within the NAND memory cell array 23 of a three-dimensional structure. Other blocks of the NAND memory cell array 23 also have the same circuit configuration as fig. 3. The present embodiment can also be applied to a memory cell having a two-dimensional structure.

As shown in fig. 3, the block BLK has, for example, 4 fingers (finger) FNG (FNG 0 to FNG 3). In addition, each finger FNG includes a plurality of NAND strings (strings) NS. Each of the NAND strings NS has, for example, 8 memory cell transistors MT (MT 0 to MT 7) and select transistors ST1, ST2 connected in cascade. In this specification, each finger FNG is sometimes referred to as a string St.

Further, the number of memory cell transistors MT within the NAND string NS is not limited to 8. The memory cell transistor MT is arranged between the selection transistors ST1 and ST2 such that current paths thereof are connected in series. The current path of the memory cell transistor MT7 on one end side of the series connection is connected to one end of the current path of the selection transistor ST1, and the current path of the memory cell transistor MT0 on the other end side is connected to one end of the current path of the selection transistor ST2.

Gates of the respective select transistors ST1 denoted by FNG0 to FNG3 are commonly connected to select gate lines SGD0 to SGD3, respectively. On the other hand, the gates of the selection transistors ST2 are commonly connected to the same selection gate line SGS between the plurality of fingers FNG. Control gates of the memory cell transistors MT0 to MT7 in the same block BLK are commonly connected to the word lines WL0 to WL7, respectively. In other words, the word lines WL0 to WL7 and the select gate line SGS are commonly connected to each of the plurality of fingers FNG0 to FNG3 in the same block BLK, whereas the select gate line SGD is independent for each of the fingers FNG0 to FNG3 even in the same block BLK.

Word lines WL0 to WL7 are connected to control gate electrodes of memory cell transistors MT0 to MT7 constituting the NAND string NS, respectively, and the i-th memory cell transistors MTi (i=0 to n) in the NAND strings NS in the same finger FNG are commonly connected by the same word line WLi (i=0 to n). That is, the control gate electrodes of the memory cell transistors MTi in the same row within the block BLK are connected to the same word line WLi.

Each NAND string NS is connected to a word line WLi and also to a bit line. Each memory cell in each NAND string NS can be identified by an address identifying a word line WLi and select gate lines SGD0 to SGD3 and an address identifying a bit line. As described above, the data of the memory cells (memory cell transistors MT) in the same block BLK are erased together. On the other hand, data is read and written in units of physical sectors MS. One physical sector MS includes a plurality of memory cells connected to one word line WLi and belonging to one finger FNG.

The memory controller 2 performs writing (programming) in units of all the NAND strings NS connected to one word line in one finger. Therefore, the unit of the data amount that the memory controller 2 performs programming becomes 4 bits×the number of bit lines.

In the read operation and the program operation, one word line WLi and one select gate line SGD are selected according to the physical address, and the physical sector MS is selected. In this specification, the operation of writing data into a memory cell is referred to as programming as needed.

Fig. 4 is a cross-sectional view of a partial area of the NAND memory cell array 23 of the NAND memory 5 of the three-dimensional structure. As shown in fig. 4, a plurality of NAND strings NS are formed in the up-down direction on a P-well region (P-well) 41 of a semiconductor substrate. That is, on the p-type well region 41, a plurality of wiring layers 42 functioning as the select gate lines SGS, a plurality of wiring layers 43 functioning as the word lines WLi, and a plurality of wiring layers 44 functioning as the select gate lines SGD are formed in the vertical direction.

Further, a memory hole 45 is formed to reach the p-type well region 41 through the wiring layers 42, 43, and 44. A block insulating film 46, a charge storage layer 47, and a gate insulating film 48 are sequentially formed on the side surface of the storage hole 45, and a conductive film 49 is embedded in the storage hole 45. The conductive film 49 functions as a current path of the NAND string NS, and is a region where a channel is formed when the memory cell transistor MT and the selection transistors ST1 and ST2 operate.

In each NAND string NS, a selection transistor ST2, a plurality of memory cell transistors MT, and a selection transistor ST1 are stacked in this order on the p-type well region 41. A wiring layer functioning as a bit line BL is formed on the upper end of the conductive film 49.

Further, an n+ type impurity diffusion layer and a p+ type impurity diffusion layer are formed in the surface of the p-type well region 41. The contact plug 50 is formed on the n+ -type impurity diffusion layer, and a wiring layer functioning as the source line SL is formed on the contact plug 50. Further, a contact plug 51 is formed on the p+ type impurity diffusion layer, and a wiring layer functioning as a well wiring CPWELL is formed on the contact plug 51. The well wiring CPWELL is used to apply an erase voltage.

The NAND memory cell array 23 shown in fig. 4 is arranged in a plurality of columns in the depth direction of the paper surface of fig. 4, and one finger FNG is formed by a set of a plurality of NAND strings NS arranged in a column in the depth direction. The other finger FNG is formed, for example, in the left-right direction of fig. 4. Although 4 fingers FNG0 to 3 are illustrated in fig. 3, fig. 4 shows an example in which 3 fingers are arranged between the contact plugs 50 and 51.

Fig. 5 is a diagram showing an example of the threshold region in embodiment 1. Fig. 5 shows an example of the distribution of the threshold regions of the nonvolatile memory 3 of 4 bits/cell. In the nonvolatile memory 3, information is stored by using the charge amount of electrons stored in the charge storage layer 47 of the memory cell. Each memory cell has a threshold voltage corresponding to the amount of charge of electrons. The plurality of data values to be stored in the memory cell are associated with a plurality of regions (threshold regions) having different threshold voltages, respectively.

S0 to S15 in fig. 5 represent threshold distributions in 16 threshold regions. The horizontal axis of fig. 5 represents threshold voltage, and the vertical axis represents the number of memory cells (number of cells). The threshold distribution refers to the range of threshold variation. Thus, each memory cell has 16 threshold regions separated by 15 boundaries, each threshold region having an inherent threshold distribution.

In the present embodiment, the region having the threshold voltage of Vr1 or less is referred to as a region S0, the region having the threshold voltage of Vr1 or more and Vr2 or less is referred to as a region S1, the region having the threshold voltage of Vr2 or more and Vr3 or less is referred to as a region S2, and the region having the threshold voltage of Vr3 or more and Vr4 or less is referred to as a region S3. In the present embodiment, the region having the threshold voltage of Vr4 or higher and Vr5 or lower is referred to as a region S4, the region having the threshold voltage of Vr5 or higher and Vr6 or lower is referred to as a region S5, the region having the threshold voltage of Vr6 or higher and Vr7 or lower is referred to as a region S6, and the region having the threshold voltage of Vr7 or higher and Vr8 or lower is referred to as a region S7. In the present embodiment, the region having the threshold voltage of Vr8 or higher and Vr9 or lower is referred to as a region S8, the region having the threshold voltage of Vr9 or higher and Vr10 or lower is referred to as a region S9, the region having the threshold voltage of Vr10 or higher and Vr11 or lower is referred to as a region S10, and the region having the threshold voltage of Vr11 or higher and Vr12 or lower is referred to as a region S11. In the present embodiment, the region having the threshold voltage of Vr12 or higher and Vr13 or lower is referred to as a region S12, the region having the threshold voltage of Vr13 or higher and Vr14 or lower is referred to as a region S13, the region having the threshold voltage of Vr14 or higher and Vr15 or lower is referred to as a region S14, and the region having the threshold voltage of Vr15 or higher is referred to as a region S15.

The threshold distributions corresponding to the regions S0 to S15 are referred to as 1 st to 16 th distributions. Vr1 to Vr15 are threshold voltages that border the respective threshold regions.

In the nonvolatile memory 3, a plurality of threshold regions of the memory cell are associated with a plurality of data values, respectively. This correspondence is referred to as data encoding. The data encoding is determined in advance, and at the time of writing (programming) of data, electric charges are injected into the charge storage layer 47 in the memory cell so as to be within a threshold region corresponding to a data value stored in accordance with the data encoding. In addition, during reading, a read voltage is applied to the memory cell, and data logic is determined according to whether the threshold value of the memory cell is lower or higher than the read voltage.

In reading data, logic for determining the data is determined according to whether the threshold is lower or higher than the read level of the boundary of the read object. In the case where the threshold is the lowest, the "erased" state is defined as "1" for all data. In the case where the threshold is higher than the "erased" state, which is the "programmed" state, the data is defined as "1" or "0" in terms of encoding.

Fig. 6A is a diagram showing an example of data encoding according to embodiment 1, and shows an example of 1-4-5-5 data encoding. In the present embodiment, 16 threshold regions shown in fig. 5 are respectively associated with 16 data values of 4 bits. The relationship between the threshold voltage in fig. 6A and the data value of the bit corresponding to Top, upper, middle, lower page is as follows.

Memory cells whose threshold voltage is within the S0 region are in a state in which "1111" is stored.

Memory cells whose threshold voltage is within the S1 region are in a state in which "0111" is stored.

Memory cells whose threshold voltage is within the S2 region are in a state in which "0011" is stored.

Memory cells whose threshold voltage is within the S3 region are in a state in which "1011" is stored.

Memory cells whose threshold voltage is within the S4 region are in a state in which "1001" is stored.

Memory cells whose threshold voltage is within the S5 region are in a state in which "0001" is stored.

Memory cells whose threshold voltage is within the S6 region are in a state in which "0101" is stored.

Memory cells whose threshold voltage is within the S7 region are in a state in which "1101" is stored.

Memory cells whose threshold voltage is within the S8 region are in a state in which "1100" is stored.

Memory cells whose threshold voltage is within the region S9 are in a state in which "1110" is stored.

Memory cells whose threshold voltage is within the S10 region are in a state in which "1010" is stored.

Memory cells whose threshold voltage is within the region S11 are in a state in which "1000" is stored.

Memory cells whose threshold voltage is within the region S12 are in a state in which "0000" is stored.

Memory cells whose threshold voltage is within the S13 region are in a state in which "0100" is stored.

Memory cells whose threshold voltage is within the region of S14 are in a state in which "0110" is stored.

Memory cells whose threshold voltage is within the region of S15 are in a state in which "0010" is stored.

Fig. 6B is a diagram showing another example of data encoding according to embodiment 1, and shows an example of 4-3-4-4 data encoding. The relationship between the threshold voltage in fig. 6B and the data value of the bit corresponding to Top, upper, middle, lower page is as follows.

Memory cells whose threshold voltage is within the S4 region are in a state in which "1010" is stored.

Memory cells whose threshold voltage is within the S5 region are in a state in which "1110" is stored.

Memory cells whose threshold voltage is within the S6 region are in a state in which "1100" is stored.

Memory cells whose threshold voltage is within the S7 region are in a state in which "1000" is stored.

Memory cells having a threshold voltage within the region S8 are in a state in which "1001" is stored.

Memory cells whose threshold voltage is within the S9 region are in a state in which "0001" is stored.

Memory cells whose threshold voltage is within the S10 region are in a state in which "0000" is stored.

Memory cells whose threshold voltage is within the region S11 are in a state in which "0010" is stored.

Memory cells whose threshold voltage is within the region of S12 are in a state in which "0110" is stored.

Memory cells whose threshold voltage is within the region S14 are in a state in which "0101" is stored.

Memory cells whose threshold voltage is within the region of S15 are in a state in which "1101" is stored.

As shown in fig. 6A and 6B, logic of 4-bit data of each memory cell can be allocated to each region of the threshold voltage. In addition, in a state where the memory cell is not written (an "erased" state), the threshold voltage of the memory cell is within the S0 region. In addition, regarding the code shown here, only 1-bit data changes between any two adjacent areas, such as storing data of "1111" in the S0 (erased) state and storing data of "0111" in the S1 state. Thus, the data codes shown in fig. 6A and 6B are gray codes in which only 1 bit of data is changed between any two adjacent areas.

In the encoding of the present embodiment shown in fig. 6A, the threshold voltages that are boundaries for determining the bit values of each page are as follows.

Threshold voltages that are boundaries for determining the bit value of the Top page are Vr1, vr3, vr5, vr7, vr12.

The threshold voltages that are boundaries for determining the bit value of the Upper page are Vr2, vr6, vr10, vr13, vr15.

Threshold voltages that are boundaries for determining bit values of the Middle page are Vr4, vr9, vr11, vr14.

The threshold voltage that becomes the boundary for determining the bit value of the Lower page is Vr8.

In this way, the number of threshold voltages (hereinafter, referred to as the boundary number) serving as boundaries for determining the bit values is 1, 4, 5, and 5 on the Lower page, middle page, upper page, and Top page, respectively. Hereinafter, the number of boundaries of the Lower page, middle page, upper page, and Top page is referred to as 1-4-5-5 encoding.

The 1 st feature of this embodiment is that the number of boundaries in which the bit value of each page changes is 5 at the maximum. In the case of representing 16 states with 4 bits, the minimum value of the maximum number of boundaries is 4, and the codes of fig. 6A and 6B are only one more, so that the deviation of the error code is reduced. As described above, the memory system 1 according to the present embodiment has the 1 st feature, whereby the bit error rate can be suppressed, and the variation in the bit error can be suppressed on a page-by-page basis.

The 2 nd feature of this embodiment is that the number of boundaries of Lower pages is 1, the number of boundaries of Middle pages is 4, and programming can be performed in two phases, i.e., programming in the 1 st phase in which Lower pages and Middle pages are integrated together, and programming in the 2 nd phase in which Upper pages and Top pages are integrated together.

A 3 rd feature of the present embodiment is that the range of variation from the threshold region generated by the programming of the 1 st phase to the threshold region generated by the programming of the 2 nd phase is small. That is, the variation amplitude of the threshold voltage is small. The smaller the amplitude of the variation of the threshold region, the less susceptible to adjacent inter-cell interference. The above-described 1 st to 3 rd features will be described in detail later.

The control section 22 of the nonvolatile memory 3 controls programming to the NAND memory cell array 23 and reading from the NAND memory cell array 23 based on the codes shown in fig. 6A and 6B.

Three-dimensional memory cells do not progress as fast as two-dimensional memory cells in terms of miniaturization of memory cells. Therefore, in the three-dimensional memory cell, if the adjacent memory cells are a generation having a wide space between them, the inter-cell interference is small. In this case, a method of simultaneously programming all bits of each memory cell is generally employed, for example, if each bit is allocated to a different page, all pages are simultaneously programmed.

When all bits of each memory cell are programmed at the same time, no special combination is pursued as data encoding. Based on the data of all the bits, it is sufficient to determine which of the 16 threshold regions is located, and program the region from S0, which is the erased state, to the determined threshold region. In this case, data encoding is generally employed in which the maximum number of boundaries of 4-4-3-4 data encoding is a minimum value. In 4-4-3-4 data encoding, when 15 boundaries between 16 threshold regions are allocated to 4 pages, 4 boundaries are allocated to Lower pages, 4 boundaries are allocated to Middle pages, 3 boundaries are allocated to Upper pages, and 4 boundaries are allocated to Top pages. In the case of this data encoding, since the deviation of the number of boundaries between pages is small, as a result, the deviation of the bit error rate between pages is reduced. This is because the cause of bit errors is almost always caused by the shift of the threshold value to the adjacent threshold value region, and the number of bit errors increases as the number of pages having the same boundary increases. This is effective in suppressing deterioration of the response performance, cost, and power consumption of the memory system 1 to the write request from the host 4 because the correction capability of the ECC circuit 10 required for correcting the error of the page data must be enhanced even if the error rate is the same as the memory cell. In addition, the deviation of the reading speed caused by the deviation of the number of boundaries is also reduced.

In addition, in the 4-bit/cell NAND memory 5, since the interval between adjacent threshold regions is narrowed, the influence due to the mutual interference between cells becomes larger than in the 1-bit/cell and 2-bit/cell NAND memory 5. Therefore, in the NAND memory 5 of the generation in which miniaturization has been advanced in recent years, a programming method (Foggy-Fine programming) is generally employed in which charges are gently injected into the charge storage layer 47 of the memory cell using a plurality of programming stages, for example, two programming stages (hereinafter, may be simply referred to as stages) in order to suppress the inter-cell interference. In this Foggy-Fine programming, writing to the memory cell is performed in the first phase (Foggy phase) and then writing to the adjacent cell is performed, and thereafter writing is performed in the second phase (Fine phase) back to the first memory cell. Each stage in this case is an execution unit of programming, and programming of a memory cell corresponding to one word line WLi is completed by executing two programming stages.

Programming is performed using 16 threshold regions, whether first phase programming or second phase programming. The threshold distribution of the threshold region at the end of programming of the first phase has a width that is wider than the threshold distribution of the threshold region in the final data encoding. That is, in the Foggy phase, foggy (rough, blurred) writing is performed. In this Foggy phase programming, 4 pages of input data are required. The programmed threshold distribution in the Foggy stage is an intermediate state in which adjacent distributions overlap with each other, and thus data cannot be read. In the Fine phase programming as the second phase, the threshold region after the Foggy phase programming is shifted to the threshold region in the final data encoding. That is, in the Fine phase, fine writing is performed. In this Fine phase programming, 4 pages of input data are also required. The programmed threshold distribution in the Fine phase is the final state in which adjacent distributions are separated, and thus data can be read after the programming in the Fine phase.

In the case of 4-4-3-4 data encoding, the deviation of the number of boundaries is small, but in the data input of Foggy-Fine programming, data input of the amount of 4 pages is required at each stage. This may result in an increase in the time taken for data input, deteriorating the response performance of the memory system 1 to the write request from the host 4. In addition, the buffer amount (write buffer amount) of the write buffer (1 st storage section) for holding data for input to the NAND memory 5 in the memory system 1 is increased. The write buffer is typically a buffer allocated with a partial area of the RAM6 in the memory system 1.

As a countermeasure against this, in the present embodiment, the memory system 1 employs 1-4-5-5 data encoding for the nonvolatile memory 3 having a three-dimensional structure, and further performs writing in units of pages (page by page) in two stages. Thus, in the present embodiment, in the nonvolatile memory 3 having the three-dimensional structure, not only the inter-cell interference and the variation in bit error rate between pages are suppressed, but also the write buffer amount of the memory controller 2 is reduced. The write buffer of the present embodiment enables data of bits (data of Lower page, middle page, upper page, and Top page) of bits 1 to 4, which are repeatedly input at the time of programming 1 and programming 2, to be discarded or invalidated after programming 2 is started, and enables data of other bits to be discarded or invalidated after programming 1 is started.

Here, the interference between adjacent memory cells will be described. The electric charge stored in the charge storage layer 47 of one memory cell disturbs the electric field of the adjacent memory cell, and as a result, noise that fluctuates the threshold voltage when reading the adjacent memory cell is generated. Programming and verifying (verify) are performed under certain electric field conditions, and after programming is completed, adjacent memory cells are programmed to different charges, which deteriorates the read accuracy. The inter-adjacent memory cell interference becomes apparent with miniaturization of the manufacturing technology of the memory device and with a reduction in the memory cell pitch. Moreover, the inter-adjacent memory cell interference is mostly generated between adjacent memory cells connected to different bit lines on the same word line WLi.

The inter-adjacent cell disturb can be alleviated by reducing the difference in the electric field conditions of the memory cells at the time of programming and verifying, and at the time of reading after the adjacent memory cells are programmed. As one method of reducing the adjacent memory cell interference between adjacent memory cells connected to different bit lines on the same word line WLi, there is a method of dividing programming into a plurality of stages and performing programming so that the amount of charge in the charge accumulation layer 47 does not change greatly between the stages.

In the programming timing (sequence) of the present embodiment, 4 bits on one word line WLi are programmed by two programming phases, i.e., a first phase and a second phase. Each programming phase is a unit of execution of programming, and the memory system 1 of the present embodiment completes writing of 4-bit data into the memory cell by executing two programming phases. In the present embodiment, data of a page of a certain bit of 4 bits is used for each of two programming phases. Specifically, lower page data, middle page data, and Top page data are used for the first phase programming, and Middle page data, upper page data, and Top page data are used for the second phase programming.

Fig. 7 is a diagram showing the programmed threshold regions in embodiment 1. In fig. 7, the threshold regions after the first and second phases of programming of the memory cells are shown. Fig. 7 (T1) shows a threshold region of an erased state as an initial state before programming. Fig. 7 (T2) shows the threshold region after the programming of the first phase (programming 1). Fig. 7 (T3) shows the threshold region after the programming of the second phase (programming 2).

As shown in (T1) of fig. 7, all memory cells of the NAND memory cell array 23 are in a state of distribution S0 in an unwritten state (an "erased" state). As shown in (T2) of fig. 7, in the programming of the first stage, the control unit 22 of the nonvolatile memory 3 moves to the distribution above the distribution S0 by each memory cell, by either holding the distribution S0 unchanged, or injecting charges, according to the bit values to be written (stored) to the Lower page, middle page, and Top page.

Specifically, the control unit 22 is programmed so that no charge is injected when the bit values to be written to the Lower page, middle page, and Top page are all "1", and so that even when one of the bit values to be written to the Lower page, middle page, and Top page is "0", the charge is injected to shift the threshold voltage to a higher side.

That is, the distribution S1 is shifted when the bit values to be written to the Lower page, the Middle page, and the Top page are "011", the distribution S4 is shifted when the bit values to be written to the Lower page, the Middle page, and the Top page are "101", the distribution S5 is shifted when the bit values to be written to the Lower page, the Middle page, and the Top page are "001", the distribution S8 is shifted when the bit values to be written to the Lower page, the Middle page, and the Top page are "100", the distribution S9 is shifted when the bit values to be written to the Lower page, the Middle page, and the Top page are "110", the distribution S12 is shifted when the bit values to be written to the Lower page, the Middle page, and the Top page are "000", and the distribution S14 is shifted when the bit values to be written to the Lower page, the Middle page, and the Top page are "010".

Here, it is preferable that the distributions S1, S4, S5, S8, S9, S12, and S14 increase the width of the threshold region so that the threshold voltage is slightly lowered to be programmed roughly. That is, the rising amplitude of the programming voltage pulse described later is increased. This can shorten the time taken for writing. Further, by programming such that the threshold voltage is slightly lowered, the width of the threshold distribution region can be written so as to be a predetermined width eventually by the programming of the second stage.

Further, it is preferable that the intervals between the adjacent distributions S8 and S9 and between the adjacent threshold distributions S12 and S14 are narrower than the intervals between the other adjacent distributions. These adjacent threshold distributions with reduced spacing differ from each other in the data written to the Middle page. That is, since the programmed data in the first stage appears as binary data, the read of the Lower page, middle page, and Top page data can be performed, and by narrowing the interval between different threshold distributions of the Middle page data, the interval between different threshold distributions of the Lower page and Top page data is ensured to be wider, and the margin (margin) at the time of the read of the Lower page and Top page increases. Threshold distributions S0 to S14 shown in (T2) of fig. 7 correspond to the 17 th to 24 th threshold regions.

Next, as shown in (T3) of fig. 7, in the programming of the second phase, two pages, the Middle page and the Upper page, are required for writing data. The control unit 22 of the nonvolatile memory 3 is programmed so that the threshold distribution after the second phase programming becomes a level (step) of 16 values in the final state where each adjacent distribution is separated. The second phase of programming is followed by a read of all page data.

In the programming of the second phase, the larger the amplitude of the change in the threshold value of the memory cell from the end of the programming of the first phase, the larger the adjacent cell-to-cell interference. Therefore, it is preferable that the variation of the threshold distribution in which the variation of the threshold distribution of the memory cell is largest is minimized. According to the present embodiment, the maximum amount of change in the threshold distribution is 3 amounts of threshold distribution, which is a case where S0 changes to S3, a case where S4 changes to S7, and a case where S8 changes to S11. Threshold distributions S0 to S15 shown in (T3) of fig. 7 correspond to the 1 st to 16 th threshold regions.

Further, programming is typically performed by applying one or more programming voltage pulses. In the application of the programming voltage pulse a plurality of times, the voltage value rises stepwise. After each programming voltage pulse, a read called verify is performed to confirm whether the memory cell has moved beyond the threshold boundary level. By repeating the application and the reading, the threshold value of the memory cell can be moved into a range having a predetermined threshold distribution.

The control unit 22 may perform the first-stage programming and the second-stage programming continuously for one word line WLi, but may perform the programming in a discontinuous order across a plurality of word lines WLi in order to reduce the influence of the adjacent memory cell interference.

Fig. 8A is a diagram showing example 1 of the programming sequence of embodiment 1. Fig. 8B is a diagram showing example 2 of the programming sequence of embodiment 1. Fig. 8C is a diagram showing example 3 of the programming sequence of embodiment 1. In fig. 8A to 8C, in order to reduce the influence of the interference between adjacent memory cells, programming is performed in two programming phases. Fig. 8A shows an example of a program sequence in the NAND memory 5 in which one string St is connected to each word line in each block. Fig. 8B and 8C show an example of the programming sequence in the NAND memory 5 in which 4 strings St are connected to each word line in each block. In fig. 8B and 8C, 4 strings St connected to each word line are denoted as strings (strings) 0 to 3.

When writing is started, the control unit 22 advances each programming stage while crossing the word line WLi in a predetermined discontinuous order. That is, the first and second phases for the same word line are not continuously performed, but the second phase is programmed for a different word line after the first phase is programmed for a certain word line.

After programming is completed for each word line up to the second stage, the amount of variation in threshold voltage increases when programming is continuously performed for the first and second stages for adjacent word lines. Further, if the variation amount of the threshold voltages of the adjacent word lines is large, the inter-word line adjacent memory cell interference increases. Therefore, in order to reduce the inter-cell interference between adjacent memory cells between word lines, it is effective to reduce the amount of variation in threshold voltages of the adjacent word lines after the word lines have completed programming until the second stage. If the timing of FIG. 8A is the same, the programming phase of the adjacent word line after programming of a word line to the second phase is only the second phase.

When programming the three-dimensional NAND memory 5 in the programming sequence of fig. 8A, the control unit 22 starts writing, and executes programming in the following sequences (1) to (9) based on an instruction from the processor 8. The control unit 22 performs programming to the NAND memory 5 based on an instruction from the processor 8, but description based on an instruction from the processor 8 will be omitted below.

(1) First, the control section 22 performs the first-stage programming ST of the word line WL0 ₁ 1。

(2) Next, the control section 22 performs the first-stage programming ST of the word line WL1 ₁ 2。

(3) Next, the control section 22 performs the programming ST of the second stage of the word line WL0 ₁ 3。

(4) Next, the control section 22 performs the first-stage programming ST of the word line WL2 ₁ 4。

(5) Next, the control unit 22 implements the wordProgramming ST of the second phase of line WL1 ₁ 5。

(6) Next, the control unit 22 performs the first-stage programming ST of the word line WL3 ₁ 6。

(7) Next, the control section 22 performs the programming ST of the second stage of the word line WL2 ₁ 7。

(8) Next, the control unit 22 performs the first-stage programming ST of the word line WL4 ₁ 8。

(9) Next, the control unit 22 performs the second-stage programming ST of the word line WL3 ₁ 9。

In the same manner as below, the control unit 22 performs the process obliquely upward from the lower left to the upper right in fig. 8A. Thus, in fig. 8A, the plurality of memory cells in the nonvolatile memory 3 have a plurality of 1 st memory cells connected to the 1 st word line and a plurality of 2 nd memory cells connected to the 2 nd word line adjacent to the 1 st word line, and the memory controller 2 causes 1 st programming to be performed on the plurality of 2 nd memory cells after causing 1 st programming to be performed on the plurality of 1 st memory cells, and then causes 2 nd programming to be performed on the plurality of 1 st memory cells after causing 1 st programming to be performed on the plurality of 2 nd memory cells.

When programming the NAND memory 5 having the three-dimensional structure in the programming sequence of fig. 8B, the control unit 22 starts writing, and executes programming in the following sequences (11) to (24).

(11) First, the control unit 22 performs the first-stage programming St of the string st0_word line WL0 ₂ 1。

(12) Next, the control unit 22 performs the first-stage programming St of the string st1_word line WL0 ₂ 2。

(13) Next, the control unit 22 performs the first-stage programming St of the string st2_word line WL0 ₂ 3。

(14) Next, the control unit 22 performs the first-stage programming St of the string st3_word line WL0 ₂ 4。

(15) Next, the control unit 22 performs the first-stage programming St of the string st0_word line WL1 ₂ 5。

(16) Next, the control unit 22 performs the second-stage programming St of the string st0_word line WL0 ₂ 6。

(17) Next, the control unit 22 performs the first-stage programming St of the string st1_word line WL1 ₂ 7。

(18) Next, the control unit 22 performs the second-stage programming St of the string st1_word line WL0 ₂ 8。

(19) Next, the control unit 22 performs the first-stage programming St of the string st2_word line WL1 ₂ 9。

(20) Next, the control unit 22 performs the second-stage programming St of the string st2_word line WL0 ₂ 10。

(21) Next, the control unit 22 performs the first-stage programming St of the string st3_word line WL1 ₂ 11。

(22) Next, the control unit 22 performs the second-stage programming St of the string st3_word line WL0 ₂ 12。

(23) Next, the control unit 22 performs the first-stage programming St of the string st0_word line WL2 ₂ 13。

(24) Next, the control unit 22 performs the programming St of the second stage of the string st0_word line WL1 ₂ 14。

In the same manner as below, the control unit 22 performs the process obliquely upward from the lower left to the upper right in fig. 8B. In fig. 8B, the case where the number of strings St in the block is 4 has been described, but the number of strings St in the block may be 3 or less or 5 or more.

When programming the three-dimensional NAND memory 5 in the programming sequence of fig. 8C, the control unit 22 starts writing, and executes programming in the following sequence (31) to (50).

(31) First, the control unit 22 performs the first-stage programming St of the string st0_word line WL0 ₃ 1。

(32) Next, the control unit 22 performs the first-stage programming St of the string st1_word line WL0 ₃ 2。

(33) Next, the control unit 22 performs the first-stage programming St of the string st2_word line WL0 ₃ 3。

(34) Next, the control unit 22 performs the first-stage programming St of the string st3_word line WL0 ₃ 4。

(35) First, the control unit 22 implements the first stage of the string st0_wl1Programming ST ₃ 5。

(36) Next, the control unit 22 performs the first-stage programming St of the string st1_word line WL1 ₃ 6。

(37) Next, the control unit 22 performs the first-stage programming St of the string st2_word line WL1 ₃ 7。

(38) Next, the control unit 22 performs the first-stage programming St of the string st3_word line WL1 ₃ 8。

(39) Next, the control unit 22 performs the second-stage programming St of the string st0_word line WL0 ₃ 9。

(40) Next, the control unit 22 performs the second-stage programming St of the string st1_word line WL0 ₃ 10。

(41) Next, the control unit 22 performs the second-stage programming St of the string st2_word line WL0 ₃ 11。

(42) Next, the control unit 22 performs the second-stage programming St of the string st3_word line WL0 ₃ 12。

(43) Next, the control unit 22 performs the first-stage programming St of the string st0_word line WL2 ₃ 13。

(44) Next, the control unit 22 performs the first-stage programming St of the string st1_word line WL2 ₃ 14。

(45) Next, the control unit 22 performs the first-stage programming St of the string st2_word line WL2 ₃ 15。

(46) Next, the control unit 22 performs the first-stage programming St of the string st3_word line WL2 ₃ 16。

(47) Next, the control unit 22 performs the programming St of the second stage of the string st0_word line WL1 ₃ 17。

(48) Next, the control unit 22 performs the programming St of the second stage of the string st1_word line WL1 ₃ 18。

(49) Next, the control unit 22 performs the second-stage programming St of the string st2_word line WL1 ₃ 19。

(50) Next, the control unit 22 performs the second-stage programming St of the string st3_word line WL1 ₃ 20。

In fig. 8C, the case where the number of strings St in the block is 4 has been described, but the number of strings St in the block may be 3 or less or 5 or more.

In this way, even if the strings St are plural, the order of programming of the program phases of the word lines WLi in one string St is the same as the case where the strings St are one. In the case of the nonvolatile memory 3 having a three-dimensional structure in which a plurality of strings St exist in a block, the combination position of the word line WLi and the string St is usually programmed by first programming the same word line number in a different string St and then performing the next word line number. In this order, when fig. 8A is combined by the number of strings St, for example, the order of fig. 8B or 8C is changed.

An example of the writing procedure in the programming sequence according to embodiment 1 will be described with reference to fig. 9 to 11. Fig. 9 to 11 show the writing steps in the case of the programming sequence shown in fig. 8B or 8C. As described above, the memory controller 2 advances the programming phase while crossing the word lines WLi in a discontinuous order, and thus performs programming with a set (here, a block) of one word line WLi as a set of programming timings.

Fig. 9 is a flowchart showing example 1 of the entire writing procedure of the amount of one block in embodiment 1. One block here has n+1 word lines WLi of word lines WL0 to WLn (n is a natural number). Fig. 10 is a flowchart showing a writing procedure in the first stage of embodiment 1, and fig. 11 is a flowchart showing a writing procedure in the second stage of embodiment 1.

As shown in fig. 9, when writing is started, the control section 22 executes programming of the first stage of the string St 0_word line WL0 (step S10). Next, the control section 22 executes the programming of the first stage of the string st1_word line WL0 (step S20). Thereafter, the control unit 22 performs the same processing as in steps S10 and S20 on each string St. Then, the control section 22 executes the programming of the first stage of the string st3_word line WL0 (step S30).

Further, the control section 22 executes the programming of the first stage of the string st0_word line WL1 (step S40). Next, the control section 22 executes the programming of the second stage of the string st0_word line WL0 (step S50). Next, the control section 22 executes the programming of the first stage of the string st1_word line WL1 (step S60). Thereafter, the control unit 22 repeatedly performs the processing as in steps S40, S50, and S60 on each word line WLi of each string St.

Then, the control section 22 performs the programming of the first stage of the string st0_word line WLn (step S70). Next, the control section 22 executes the programming of the second stage of the string st0_word line WLn-1 (step S80). Thereafter, the control unit 22 repeatedly performs the processing as in steps S70 and S80 on each word line WLi of each string St.

Then, the control section 22 performs the programming of the second stage of the string st3_word line WLn-1 (step S90). Next, the control section 22 executes the programming of the second stage of the string st0_word line WLn (step S100). Next, the control section 22 executes the programming of the second stage of the string st1_word line WLn (step S110). Thereafter, the control unit 22 performs the same processing as in steps S100 and S110 on each string St. Then, the control section 22 executes the programming of the second stage of the string st3_word line WLn (step S120).

Fig. 10 is a flowchart showing example 1 of the first-stage writing step. In the programming of the first stage, first, an input start command of Lower page data is input from the memory controller 2 to the nonvolatile memory 3 (step S210). Next, lower page data is input from the memory controller 2 to the nonvolatile memory 3 (step S215). Next, an input start command of Middle page data is input from the memory controller 2 to the nonvolatile memory 3 (step S220). Then, middle page data is input from the memory controller 2 to the nonvolatile memory 3 (step S225). Next, an input start command of Top page data is input from the memory controller 2 to the nonvolatile memory 3 (step S230). Then, top page data is input from the memory controller 2 to the nonvolatile memory 3 (step S235). Further, the first-stage program execution command is input from the memory controller 2 to the nonvolatile memory 3 (step S240), and the chip becomes busy (step S245).

At the time of data writing, a threshold voltage Vth is determined (step S250), and one or more program voltage pulses are applied (step S255). Then, data reading (verification) for confirming whether the memory cell has moved beyond the threshold boundary level is performed (step S260).

Further, it is confirmed whether the number of fail bits of the data in the Lower page, middle page, and Top page is smaller than the standard (determination criterion) (step S265). When the number of fail bits of the data is equal to or greater than the standard, the process of applying the programming pulse to the standard judgment is repeated (steps S255 to S265). Also, when the number of failure bits of the data is smaller than the standard, it becomes chip ready (step S270). In this way, by repeating the application, reading, and confirmation, the threshold value of the memory cell can be moved to a range of a predetermined threshold distribution.

As described above, the read level after application of the programming voltage pulse in the first-stage writing may be slightly different from the read level after the second-stage writing, and is preferably lower than the read level after the second-stage writing. Namely, vr1' is less than or equal to Vr1, vr4' is less than or equal to Vr4, vr5' is less than or equal to Vr5, vr8' is less than or equal to Vr8, vr9' is less than or equal to Vr9, vr12' is less than or equal to Vr12, and Vr14' is less than or equal to Vr14.

In the read after the programming voltage pulse is applied in the first-stage write, the read by Vr9 'and the read by Vr14' may be omitted, and after Vr9 'passes the read by Vr8', the write is completed after a predetermined number of programming voltage pulses are applied, and after Vr14 'passes the read by Vr13', the write is completed after a predetermined number of programming voltage pulses are applied.

This is because, as described above, by narrowing the interval between the threshold regions in which the data of the Middle page is different among the data after the programming in the first stage, even with simple control in which only a predetermined number of programming voltage pulses are applied, it is possible to ensure that the interval between the threshold regions in which the data of the Lower page and the Top page read in the second stage writing are different is sufficiently wide.

The reading after the application of the programming voltage pulses Vr8', vr9', vr12', and Vr14' may be omitted, and after the reading by Vr5', the writing may be completed after the application of the programming voltage pulses a predetermined number of times. Further, the reading after the application of the programming voltage pulses Vr4', vr5', vr8', vr9', vr12', vr14' may be omitted, and after the reading by Vr1', the writing may be completed after the application of the programming voltage pulses a predetermined number of times.

Fig. 11 is a flowchart showing example 1 of the second stage writing step. In the programming of the second stage, first, an input start command of Middle page data is input from the memory controller 2 to the nonvolatile memory 3 (step S310). Then, the data of the Middle page is input from the memory controller 2 to the nonvolatile memory 3 (step S320).

Next, an input start command of the data of the Upper page is input from the memory controller 2 to the nonvolatile memory 3 (step S330). Then, the Upper page data is input from the memory controller 2 to the nonvolatile memory 3 (step S340). Next, a program execution command of the second stage is input from the memory controller 2 to the nonvolatile memory 3 (step S350), and the chip becomes busy (step S360).

Thereafter, the control unit 22 reads Lower page and Top page data as IDL (Internal Data Load, internal data loading) (step S370). Then, vth (threshold voltage) of the programming destination of the Upper page is determined based on the Middle page data inputted first and the Lower page and Top page data of IDL (step S380). Then, using the determined Vth, data writing into the Upper page is performed. More specifically, the voltage values of the plurality of programming pulses are gradually increased so as to be the determined threshold voltage, and writing is performed (step S390). Memory cells that reach the target threshold voltage are excluded from the writing object.

After that, the written data is read (step S400), and it is checked whether the failure bit number is smaller than the standard (determination criterion) (step S410). When the number of fail bits of the data is equal to or greater than the standard, the process of applying the programming pulse to the standard judgment is repeated (steps S390 to S410). When the number of failure bits of the data is smaller than the standard, the chip becomes ready (step S420).

Here, the present embodiment has two features. The 1 st feature is that the data of the Middle page is already input during the programming in the first stage, and the threshold area after the first programming is the writing state of the data containing the Middle page, but the data of the Middle page is input again during the programming in the second stage. The 2 nd feature is that adjacent threshold regions in which data of Middle page is switched are narrowed in interval with each other in programming of the first stage, and conversely, adjacent threshold distributions in which data of Lower page and data of Top page are switched are widened in interval with each other. Thus, the reliability of the Lower page and Top page data read by IDL can be improved. On the other hand, if the data is read with IDL, there is a fear that the reliability of the data of the Middle page is lowered, but in the present embodiment, since the data of the Middle page used in the first-stage programming is input again, there is no fear that the reliability is lowered.

In order to improve the reliability of the read data of IDL, the control unit 22 may perform a plurality of reads, and take a majority of the read result in the page buffer in the chip, and use the read result as the next write data. Of course, the control unit 22 can perform a plurality of times of reading even in a normal reading operation, and take a majority of the reading result in the chip and use it as reading data to the outside.

Fig. 12 is a diagram for explaining the selection processing of the read result of a plurality of times. In fig. 12, as a result of reading predetermined page data, correct bits are indicated by circle marks (∈circle), and incorrect bits are indicated by fork marks (×). Fig. 12 shows the majority of the results obtained when three readings were performed.

In each bit, the majority of the results are determined to be erroneous (a) a case where all three times are erroneous and (b) a case where all two times are erroneous. If the probability of each bit being erroneous is set to p, then in the case of p=0.2, (a) the probability of three errors is p x p=0.2 x 0.2, the probability of (b) two errors is (1-p) ×p×p= (1-0.2) ×0.2×0.2.

Thus, the first and second substrates are bonded together, the majority result of three times is judged to be wrong (p X p) +3X (1) -p) ×p×p=0.104. In this way, the control unit 22 can improve the reliability of the read data by performing the selection processing of the read result a plurality of times by the page buffer 24 in the chip.

In order to improve the reliability of the read data of IDL in the second-stage write of word line WLn, control unit 22 may change the read voltage of word line WLn in IDL according to the data or threshold voltage written in the first-stage write of word line wln+1.

Further, the control unit 22 may change the non-selection voltage of the word line wln+1 in IDL in accordance with the data or the threshold voltage written in the first-stage write of the word line wln+1 in order to improve the reliability of the read data of IDL in the second-stage write of the word line WLn. At this time, the read voltage of the word line WLn may be changed at the same time to perform the reading.

One or more programming voltage pulses are applied while writing data to the Upper page. Then, the data read (verify) of the Upper page is performed to confirm whether or not the memory cell has moved beyond the threshold boundary level. The read level at this time is a predetermined level.

Further, it is confirmed whether the number of fail bits of the data in the Upper page is smaller than the standard. When the number of fail bits of data in the Upper page is equal to or greater than the standard, the process of applying the program voltage pulse to the verify is repeated. Also, when the number of failure bits of data is smaller than the standard, it becomes chip ready.

Here, a modification of the writing step shown in fig. 11 will be described. Fig. 13 is a flowchart showing a modification of the second-stage writing step according to embodiment 1. In addition, in the flowchart of fig. 13, the following steps are added: the IDL data obtained by reading the data programmed in the first stage is returned to the nonvolatile memory 3 after error correction. Specifically, first, a read command of the Lower page is input from the memory controller 2 to the nonvolatile memory 3 (step S510). Thereby, the chip becomes busy (step S512). Next, the control unit 22 reads the Lower page data with the threshold voltage of Vr 8'. The control unit 22 then determines the value of the read data to be "0" or "1" based on the read result at the threshold voltage of Vr8' (step S514). Thereafter, the chip becomes ready (step S516).

When the control unit 22 outputs the read Lower page data (step S518), the Lower page data is transmitted to the ECC circuit 10 (step S520). Thereby, the ECC circuit 10 performs ECC correction on the Lower page data (step S522).

Next, an input start command of the data of the Lower page is input from the memory controller 2 to the nonvolatile memory 3 (step S524). Thereby, the ECC circuit 10 inputs the data of the Lower page to the nonvolatile memory 3 (step S526).

Next, a read command of the Top page is input from the memory controller 2 to the nonvolatile memory 3 (step S528), and the chip becomes busy (step S530). After that, the control section 22 performs reading of Top page data with the threshold voltages of Vr2 'and Vr 10'. Then, the control section 22 decides the value of the read data as "0" or "1" based on the read results at the threshold voltages of Vr1', vr4', vr8', and Vr12' (step S532). Thereafter, the chip becomes ready (step S534).

When the control section 22 outputs the read Top page data (step S536), the Top page data is sent to the ECC circuit 10 (step S538). Thereby, the ECC circuit 10 performs ECC correction on the Top page data (step S540). Next, an input start command of data of Top page is input from the memory controller 2 to the nonvolatile memory 3 (step S542). Thereby, the ECC circuit 10 inputs the data of the Top page to the nonvolatile memory 3 (step S544).

After that, an input start command of data of the Middle page is input from the memory controller 2 to the nonvolatile memory 3 (step S546). The steps thereafter are the same as those of fig. 11. The threshold voltage Vth of the programming destination is determined based on Lower page data and Top page data from the ECC circuit 10, data of the Middle page that is input again, and data of the Upper page that is input newly.

In the second-stage programming described above, the data input to the nonvolatile memory 3 is only two pages, i.e., the Middle page and the Upper page. However, in the second phase, the threshold voltage Vth, which is the destination of programming of the memory cell, needs to be 4-page data including the Lower page and the Top page (threshold voltage Vth before starting the second phase). Therefore, in the programming at this stage, as preprocessing, the control section 22 performs the following operations: first, lower page data and Top page data are read, and the data are synthesized with the Middle page and Upper page which are input thereto to determine the threshold voltage Vth of the programming destination. The read level during the second-stage verification may be slightly different from the read level after the second-stage writing.

Here, a comparison of the processing steps of Foggy-Fine programming using 4-3-4-4 data encoding with the programming processing steps of the present embodiment will be described. FIG. 14A is a diagram illustrating the amount of data for a write buffer in Foggy-Fine programming with 4-3-4-4 data encoding. Fig. 14B is a diagram illustrating the data amount of the write buffer in the present embodiment. FIG. 14B shows an example of encoding with 1-4-5-5 data.

In fig. 14A and 14B, a time chart of data input and programming execution of block writing is shown on the upper stage side, and a time chart of a period required for holding data in a write buffer is shown on the lower stage side. Fig. 14A and 14B show a case where the number of strings St in one block is 1 for simplicity of description. When the number of strings St is plural, the data amount to be written into the buffer needs to be a multiple of the number of strings St.

In the case of Foggy-Fine programming of 4-3-4-4 data encoding, data input of 4 pages and programming of the 4 pages (programming of Foggy phase) are performed in the Foggy phase as the first phase. In the case of Foggy-Fine programming of 4-3-4-4 data encoding, data input of 4 pages and programming of the 4 pages (Fine phase programming) are also performed in the Fine phase as the second phase.

Further, on each of the word lines WL0, WL1, WL2, and …, it is necessary to store the data of 4 pages written in the Foggy phase in the write buffer until programming starts in the Fine phase.

In Foggy-Fine programming, 4 pages of data, lower/Middle/Upper/Top, are not written continuously to reduce the interference between adjacent memory cells. For example, after the Foggy phase to the word line WL0 is performed, the Foggy phase to the word line WL1 adjacent to the word line WL0 is performed before the Fine phase to the word line WL0 is performed. In addition, after the Foggy phase to the word line WL1 is performed, before the Fine phase to the word line WL1 is performed, the Foggy phase to the word line WL2 adjacent to the word line WL1 is performed. In this method, it is necessary to hold 4 pages of data, i.e., lower/Middle/Upper/Top, in the write buffer until the data input in the Fine phase, which is the final second phase, is completed. In addition, in order to reduce the interference between adjacent memory cells, it is necessary to hold the data on the plurality of word lines WLi in the write buffer. For example, when the Foggy phase is performed for the word line WL2, it is necessary to hold data of 4 pages for the word line WL1 and data of 4 pages for the word line WL2 in the write buffer. Thus, in the case of Foggy-Fine programming of 4-3-4-4 data encoding, it is necessary to keep up to 8 pages of data in the write buffer.

As shown in fig. 14B, in the programming of the present embodiment, for example, two-phase programming is used in 1-4-5-5 data encoding. In the programming of this embodiment, in the first stage, data input of 3 pages (Lower page, middle page, and Top page) and programming of the 3 pages (first programming) are performed. In the case of programming in the present embodiment, in the second phase, data input of two pages (Middle page and Upper page) and programming of one page of Upper page (second programming) are performed.

In addition, in addition to the Middle page input in both stages, the word lines WL0, WL1, WL2, and … may store data in the write buffer when data is input in each stage, and may delete data from the write buffer when programming is started. For example, if data is input in the first stage, the data is stored in the write buffer. Further, if programming is started in the first stage, the data of the Lower page and the Top page stored in the write buffer in advance may be deleted. Similarly, if data is input in the second phase, the data is stored in the write buffer. In addition, if programming is started in the second phase, the data stored in the write buffer in advance may be deleted entirely. Therefore, in the case of programming of the present embodiment, data of at most 4 pages of data held in the write buffer in advance is required.

In the programming of the present embodiment, 4 pages of data, lower/Middle/Upper/Top, are not written continuously in order to reduce the interference between adjacent memory cells. For example, after the first phase to the word line WL0 is performed, the first phase to the word line WL1 adjacent to the word line WL0 is performed before the second phase to the word line WL0 is performed. Similarly, after the first phase is performed to the word line WL1, the first phase is performed to the word line WL2 adjacent to the word line WL1 before the second phase is performed to the word line WL 1.

As described above, in the present embodiment, since page data other than the Middle page is only required for one-time programming, data written into the buffer can be discarded as soon as the data input is completed. Therefore, in the present embodiment, the number of pages that need to be held in the write buffer at the same time can be small.

After the page data programmed into the nonvolatile memory 3 is temporarily held in the write buffer in the RAM6, data is written into the nonvolatile memory 3 at the time of programming. In the present embodiment, the required capacity of the RAM6 can be reduced, and therefore, the cost can be reduced.

In addition, when Foggy-Fine programming is used, data transfer of all page data must be performed twice, and therefore, transfer time is required, and power consumption at the time of transfer is additionally required. In the present embodiment, since the page data other than the Middle page is completed by one data transfer per page, the transfer time and the power consumption can be suppressed to about 1/2.

Here, page reading processing will be described. The method of page reading differs depending on whether programming for the word line WLi including the read target page is before or after the writing of the second stage.

In the case before the second stage write, only the Lower page, middle page, and Top page of the recorded data are valid. Therefore, the control unit 22 reads data from the memory cells when the read page is the Lower page, the Middle page, or the Top page, but in the case of the other page (specifically, the Upper page), the control unit performs control to forcibly output "1" as read data in its entirety without performing the memory cell read operation.

On the other hand, when the word line WLi up to the second stage is completed, the control unit 22 reads the memory cell regardless of which page of the Top/Upper/Middle/Lower pages is the read page. In this case, the required read voltage differs depending on which page is to be read, and therefore, the control section 22 performs only the required reading in accordance with the selected page.

The specific processing steps of page reading are explained below. Fig. 15 is a flowchart showing the processing steps of page reading on the word line until programming has been completed to the first stage (programming of the second stage is not completed) in the memory system 1 according to embodiment 1. According to the 1-4-5-5 data encoding shown in fig. 6A, the boundary between the threshold states in which the Lower page data changes is one, and therefore, the control section 22 decides the data according to which of the two ranges separated by the boundary the threshold falls. For example, when the threshold voltage is smaller than Vr8', the control unit 22 performs control to output "1" as data of the memory cell. On the other hand, when the threshold voltage is greater than Vr8', the control unit 22 performs control to output "0" as data of the memory cell.

Since the number of boundaries between threshold states in which data of the Middle page changes is 3, the control unit 22 determines data according to which of 4 ranges separated by these boundaries the threshold value falls. Since the number of boundaries between threshold states in which the data of the Top page changes is 4, the control unit 22 determines the data according to which of 5 ranges separated by these boundaries the threshold value falls.

As shown in fig. 15, in the case of the word line WLi before the second-stage writing, the control section 22 selects a read page (step S610). When the read page is the Lower page, the control unit 22 performs reading with one read voltage (step S612). As described above, although this voltage is Vr8, in the case of the word line before the second-stage writing, there may be a margin between the read voltage and the threshold voltage, for example, vr8', as shown in (T2) of fig. 7. Then, the control unit 22 decides the value of the read data as "0" or "1" based on the read result at the threshold voltage of Vr8 (step S614).

When the read page is the Middle page, the control unit 22 performs reading with 3 read voltages (steps S616, S618, and S620). As described above, the voltages are Vr4, vr9, and Vr14, but in the case of the word line before the second-stage writing, there may be a margin of the read voltage and the threshold voltage, for example, vr4', vr9', and Vr14' instead of them, as shown in (T2) of fig. 7. Then, the control unit 22 decides the value of the read data as "0" or "1" based on the read result at the threshold voltage of Vr4, the read result at the threshold voltage of Vr9, and the read result at the threshold voltage of Vr14 (step S622). Here, as described above, since the interval between different threshold distributions of the data of the Middle page is narrowed and the read margin of the Middle page is narrowed, there is a possibility that the reliability of the value of the read data is significantly poor, and the Middle page data before the second-stage writing may be defined as invalid. In this case, when the read page is a Middle page, the control unit 22 may control to forcibly output all "1" as the output data of the memory cell.

In addition, when the read page is the Upper page, since the Upper page is not programmed in the first programming, the control unit 22 forcibly outputs "1" as output data in its entirety (step S624).

When the read page is the Top page, the control unit 22 performs reading with 4 read voltages (steps S626, S628, S630, S632). As described above, the voltages are Vr1, vr4, vr8, and Vr12, but in the case of the word line before writing in the second stage, as shown in (T2) of fig. 7, there may be a margin for the read voltage and the threshold voltage, for example, vr1', vr4', vr8', and Vr12', respectively, instead of these. Then, the control unit 22 decides the value of the read data as "0" or "1" based on the read result at the threshold voltage of Vr1, the read result at the threshold voltage of Vr4, the read result at the threshold voltage of Vr8, and the read result at the threshold voltage of Vr12 (step S634).

Fig. 16A is a flowchart showing the processing steps of page reading on the word line after programming has been completed to the second stage in the memory system according to embodiment 1. In the case where programming has been completed to the word line WLi of the second stage, the control section 22 selects a read page (step S650). When the read page is the Lower page, the control unit 22 reads at the one threshold voltage Vr8 (step S652). Then, the control unit 22 determines the value of the read data to be "0" or "1" based on the read result at the one threshold voltage Vr8 (step S654).

When the read page is the Middle page, the control unit 22 reads with the threshold voltages of Vr4, vr9, vr11, and Vr14 (steps S656, S658, S660, and S662). Then, the control unit 22 determines the value of the read data as "0" or "1" based on the read results at the threshold voltages of Vr4, vr9, vr11, and Vr14 (step S664).

When the read page is the Upper page, the control unit 22 reads with the threshold voltages of Vr2, vr6, vr10, vr13, and Vr15 (steps S666, S668, S670, S672, and S674). Then, the control unit 22 determines the value of the read data to be "0" or "1" based on the read results at the threshold voltages of Vr2, vr6, vr10, vr13, and Vr15 (step S676).

When the read page is the Top page, the control unit 22 reads with the threshold voltages of Vr1, vr3, vr5, vr7, and Vr12 (steps S678, S680, S682, S684, and S686). Then, the control unit 22 decides the value of the read data as "0" or "1" based on the read results at the threshold voltages of Vr1, vr3, vr5, vr7, and Vr12 (step S688).

Further, whether programming for word line WLi is before or after completion of the second phase write can be managed and identified by memory controller 2. In the memory system 1, since the memory controller 2 performs programming control, the memory controller 2 can easily refer to which address of the nonvolatile memory 3 is in what programming state as long as the memory controller 2 records the progress status thereof. In this case, when the memory controller 2 reads from the nonvolatile memory 3, it recognizes what programming state the word line WLi including the target page address is, and issues a read command corresponding to the recognized state. In addition, as another method, a flag (flag) unit may be provided for the word line WLi, the flag unit may be written in during the second-stage writing, and management/identification may be performed before the completion of the second-stage writing or after the writing in the nonvolatile memory 3 based on the data of the flag unit.

A modified example of the page reading process is described below. The page read processing according to a modification can be executed only after the second-stage write is performed for the programming of the word line WLi including the read target page. The page reading processing according to a modification is effective in the following aspects: in the case where all data of the word line of the read target is to be read, the reading speed is increased.

The data encoding suitable for the page reading processing according to the modification is, for example, encoding as shown in fig. 16B. A reading process according to a modification of the data encoding will be described below. In the page reading processing according to a modification, all pages of the Top/Upper/Middle/Lower pages are read.

Fig. 16C is a flowchart showing a reading process procedure according to a modification. Fig. 16D is a voltage waveform diagram of the selected word line, readyBusy signal line, and output data line. The control unit 22 sequentially reads the 15 total read voltages Vr15 to Vr 1. First, as shown in fig. 16D, reading is performed at Vr15, which is the highest voltage (step S690), and then, reading is continuously performed in order at a low reading voltage while lowering by 1 level each time (steps S691 to S707). When the reading required for determining the read data of each page is completed, the read data of the page can be outputted.

In the page reading processing according to the modification, when the reading is sequentially performed from Vr15 to Vr8 and the reading is completed (step S697), the data of the Lower page can be determined and output (step S698). In step S698, the data of the Lower page is determined based on the read data at the read voltage Vr 8.

Next, when the reading is completed up to Vr4 (step S702), the data of the Middle page is determined (step S703). In this step S703, the data of the Middle page is decided based on the read data at the read voltages Vr4, vr9, vr11, and Vr 14.

Next, when the reading is completed up to Vr2 (step S705), the data of the Upper page is determined (step S706). In step S706, the data of the Upper page is determined based on the read data at the read voltages Vr2, vr6, vr10, vr13 and Vr 15.

Next, when the reading is completed up to Vr1 (step S707), the data of the final Top page is determined (step S708). In this step S708, the data of the Top page is determined based on the read data at the read voltages Vr1, vr3, vr5, vr7, and Vr 12.

In the page reading processing according to the modification, the delay (latency) until the data of 1 page becomes output becomes longer, but the total time for reading all 4 pages can be shorter than the total time in the case of reading page by page described above. As shown in fig. 16D, the time required for charging the word line from zero to Vr15, which is a high voltage, is 1 time as a preparation for reading, and the amplitude of the voltage change when the read level is changed to the next voltage is small and the voltage is stabilized in a short time, so that the waiting time until the read voltage is stabilized can be shortened. Therefore, when reading is performed at all of the read voltages Vr15 to Vr1, the total of the transition times of the selected word lines becomes shorter, and as a result, the total read time can be increased in speed.

The data encoding of fig. 16B is described as an example, but basically, any data encoding can be applied. However, since the reading voltage is sequentially changed from the maximum voltage to the minimum voltage to perform the reading, the data can be outputted in the order of the pages for which the reading of the voltages necessary for specifying the data is completed. Therefore, depending on the manner of data encoding, care should be taken not to read in page order of Lower, middle, upper, top.

Thus, in embodiment 1, when programming the nonvolatile memory 3 (a 4-bit/cell NAND memory having a three-dimensional structure or a two-dimensional structure), 1-4-5-5 data encoding is used, and the programming phase is set to 2-phase system. Since the programming is performed in the 2-stage system in this way, the amount of data input during the data programming in each stage can be reduced, and the amount of write buffer required for the memory controller 2 can be suppressed. In addition, since the number of threshold boundaries is equal for each page, the variation in bit error rate between pages of the nonvolatile memory 3 can be reduced, and the cost for ECC can be reduced. In addition, since data is transferred only 1 time per page other than one page, transfer time and power consumption can be suppressed.

In addition, each program phase is performed across word line WLi on one side, so the amount of adjacent cell-to-cell interference with adjacent word line WLi can be reduced. In addition, since 1-4-5-5 data encoding is used, the amount of variation in the threshold distribution in the second programming becomes small, and thus the amount of interference between adjacent cells can be suppressed. In addition, by inputting data in both stages, one page (specifically, middle page) can expand IDL margin before the second stage, and the reliability of the write timing can be improved. Since 1-4-5-5 data encoding is used, the first-stage programming, i.e., the Lower page and the Middle page programming can be speeded up by setting the threshold boundary in the Lower page to one and the threshold boundary in the Middle page to two in the first-stage programming. Further, for the speed-up of the programming in the first stage, when the writing and the writing verification are repeated, the step voltage in the writing by boosting the writing voltage slightly is set to a value larger than that in the programming in the 2 nd stage, and the like, thereby enabling the speed-up.

(embodiment 2)

In embodiment 1, 1-4-5-5 data encoding is described as an example, but various modifications of data encoding are possible. The hardware configuration of the memory system 1 of embodiment 2 is common to the memory system 1 of embodiment 1. Fig. 17 to 25 show an example of data encoding in the memory system 1 according to embodiment 2. The memory system 1 of embodiment 2 uses data encoding other than 1-4-5-5 data encoding.

FIG. 17 is a diagram showing an example of 1-5-4-5 data encoding. In the example of fig. 17, the number of transitions in the threshold region at the end of the second programming is at most 3. Here, although the threshold region at the time of programming completion of the first phase and the threshold region at the time of programming completion of the second phase do not completely coincide in voltage distribution range, in the present specification, for convenience, the threshold region at the time of programming completion of the second phase, in which the voltage distribution range is closest to each threshold region at the time of programming completion of the first phase, will be referred to as a transition number, the number of threshold regions changed at the time of performing the second programming. In the case of fig. 17, in the first stage, data of Lower page, middle page, and Upper page are input to perform programming, and in the second stage, data of Top page and Middle page are input to perform programming. The data of the Middle page is repeatedly input in the first stage and the second stage. The interval of two threshold regions that can be separated by the data value of the Middle page at the programming completion time point of the first stage is narrower than the interval of the other threshold regions.

FIG. 18 is a diagram showing an example of 1-5-4-5 data encoding. In the example of fig. 18, the number of transitions in the threshold region at the end of the second programming is at most 3. In the case of fig. 18, in the first stage, data of Lower page, middle page, and Upper page is input to perform programming, and in the second stage, data of Top page and Upper page is input to perform programming. The data of the Upper page is repeatedly input in the first and second phases. The interval of two threshold regions, which can be separated by the data value of the Upper page at the programming completion time point of the first stage, is narrower than the interval of the other threshold regions.

FIG. 19 is a diagram showing an example of 3-5-2-5 data encoding. In the example of fig. 19, the number of transitions in the threshold region at the end of the second programming is at most 3. In the case of fig. 19, in the first stage, data of Lower page, middle page, and Upper page are input to perform programming, and in the second stage, data of Top page and Middle page are input to perform programming. The data of the Middle page is repeatedly input in the first stage and the second stage. The interval of two threshold regions that can be separated by the data value of the Middle page at the programming completion time point of the first stage is narrower than the interval of the other threshold regions.

FIG. 20 is a diagram showing an example of 3-3-4-5 data encoding. In the example of fig. 20, the number of transitions in the threshold region at the end of the second programming is at most 3. In the case of fig. 20, in the first stage, data of Lower page, middle page, and Upper page is input to perform programming, and in the second stage, data of Top page and Upper page is input to perform programming.

FIG. 21 is a diagram showing an example of 2-3-5-5 data encoding. In the example of fig. 21, the number of transitions in the threshold region at the end of the second programming is 5 at the maximum. In the case of fig. 21, in the first stage, data of Lower page, middle page, and Top page is input to perform programming, and in the second stage, data of Top page and Upper page is input to perform programming. The data of the Top page is repeatedly input in the first and second phases. In the case of fig. 21, at the point in time when programming of the first phase is completed, the data of the Top page is the same in either 0 or 1,3 threshold regions, and the total number of threshold regions becomes 5. This can expand the interval between the threshold regions, and can accurately read data at the time point when programming is completed in the first stage.

Fig. 22 is a diagram showing an example of 3-2-5-5 data encoding. In the example of fig. 22, the number of transitions in the threshold region at the end of the second programming is 5 at the maximum. In the case of fig. 22, in the first stage, data of Lower page, middle page, and Top page is input to perform programming, and in the second stage, data of Top page and Upper page is input to perform programming. The data of the Top page is repeatedly input in the first and second phases. In the case of fig. 22, at the point in time when programming of the first phase is completed, the data of the Top page is either 0 or 1, and the two threshold regions are the same, and the total number of threshold regions is 6.

Fig. 23 is a diagram showing an example of 3-4-4-4 data encoding. In the example of fig. 23, the number of transitions in the threshold region at the end of the second programming is 7 at the maximum. In the case of fig. 23, in the first stage, data of Lower page, middle page, and Upper page is input to perform programming, and in the second stage, data of Top page and Upper page is input to perform programming. The data of the Upper page is repeatedly input in the first and second phases. The interval of two threshold regions, which can be separated by the data value of the Upper page at the programming completion time point of the first stage, is narrower than the interval of the other threshold regions.

Fig. 24 is a diagram showing an example of 3-4-4-4 data encoding. In the example of fig. 24, the number of transitions in the threshold region at the end of the second programming is 8 at the maximum. In the case of fig. 24, in the first stage, data of Lower page, middle page, and Top page is input to perform programming, and in the second stage, data of Top page and Upper page is input to perform programming. The data of the Top page is repeatedly input in the first and second phases. In the case of fig. 24, at the point in time when programming of the first phase is completed, the data of the Top page is either 0 or 1, and the two threshold regions are the same, and the total number of threshold regions is 6.

Fig. 17 to 24 show only examples of data encoding, and other data encoding may be employed.

For example, fig. 25 to 27 below are also examples of the maximum number of transitions in the threshold region at the end of the second programming, in addition to fig. 17 to 20. FIG. 25 is a diagram showing an example of 1-4-5-5 data encoding. In the example of fig. 25, 6 different threshold regions are generated at the point in time when the first programming is completed. The threshold region where the Top page is 1 and the Lower page is 1 and the threshold region where the Middle page is 0 and the Lower page is 1 are the same threshold regions, regardless of whether the Top page is 0 or 1. Therefore, 8 threshold regions should be generated originally, but are summarized into 6 threshold regions.

Fig. 26 is a diagram showing an example of 2-5-3-5 data encoding. In the example of fig. 26, 7 different threshold regions are generated at the point in time when the first programming is completed. The threshold area of the Top page is equal to the threshold area of the middle page 1 and the Lower page 1, regardless of whether the Top page is 0 or 1. Therefore, 8 threshold regions should be generated originally, but 7 threshold regions are summarized.

FIG. 27 is a diagram showing an example of 3-4-5-3 data encoding. In the example of fig. 27, 7 different threshold regions are generated at the point in time when the first programming is completed. The threshold area of the Top page is equal to the threshold area of the middle page 1 and the Lower page 1, regardless of whether the Top page is 0 or 1. Therefore, 8 threshold regions should be generated originally, but 7 threshold regions are summarized.

In addition, other examples of data encoding are also contemplated. In the following, a diagram showing code allocation for each data code is listed. Fig. 28 shows an example of 3-2-5-5 data encoding, fig. 29 shows an example of 3-2-5-5 data encoding, and fig. 30 shows an example of 1-5-5-4 data encoding. Fig. 31 shows an example of 1-5-4-5 data encoding, fig. 32 shows an example of 1-4-5-5 data encoding, and fig. 33 shows an example of 1-5-3-6 data encoding. Fig. 34 shows an example of 1-3-6-5 data encoding, fig. 35 shows an example of 1-2-6-6 data encoding, and fig. 36 shows an example of 1-2-6-6 data encoding.

Fig. 37 shows an example of 1-2-6-6 data encoding, fig. 38 shows an example of 1-4-6-4 data encoding, and fig. 39 shows an example of 1-4-4-6 data encoding. Fig. 40 shows an example of 1-4-6-4 data encoding, fig. 41 shows an example of 1-4-4-6 data encoding, and fig. 42 shows an example of 2-5-2-6 data encoding. Fig. 43 shows an example of 2-5-2-6 data encoding, fig. 44 shows an example of 2-5-2-6 data encoding, and fig. 45 shows an example of 3-3-3-6 data encoding. Fig. 46 shows an example of 3-3-6-3 data encoding, fig. 47 shows an example of 2-3-4-6 data encoding, and fig. 48 shows an example of 3-4-2-6 data encoding.

Fig. 49 shows an example of 2-3-4-6 data encoding, fig. 50 shows an example of 3-2-6-4 data encoding, and fig. 51 shows an example of 3-2-4-6 data encoding. Fig. 52 shows an example of 3-2-6-4 data encoding, fig. 53 shows an example of 3-4-2-6 data encoding, and fig. 54 shows an example of 3-2-4-6 data encoding. Fig. 55 shows an example of 5-3-2-5 data encoding, fig. 56 shows an example of 3-5-2-5 data encoding, and fig. 57 shows an example of 3-2-5-5 data encoding. Fig. 58 shows an example of 2-3-5-5 data encoding, fig. 59 shows an example of 2-3-5-5 data encoding, and fig. 60 shows an example of 2-3-5-5 data encoding.

Fig. 61 shows an example of 5-4-2-4 data encoding, fig. 62 shows an example of 4-5-2-4 data encoding, and fig. 63 shows an example of 5-4-2-4 data encoding. Fig. 64 shows an example of 2-4-5-4 data encoding, fig. 65 shows an example of 2-4-5-4 data encoding, and fig. 66 shows an example of 2-5-4-4 data encoding. Fig. 67 shows an example of 2-5-4-4 data encoding, fig. 68 shows an example of 2-5-4-4 data encoding, and fig. 69 shows an example of 1-5-4-5 data encoding. Fig. 70 shows an example of 1-4-5-5 data encoding, fig. 71 shows an example of 1-5-5-4 data encoding, and fig. 72 shows an example of 1-4-5-5 data encoding.

Fig. 73 shows an example of 1-5-5-4 data encoding, fig. 74 shows an example of 1-5-4-5 data encoding, and fig. 75 shows an example of 1-5-5-4 data encoding. Fig. 76 shows an example of 1-5-4-5 data encoding, fig. 77 shows an example of 1-4-5-5 data encoding, and fig. 78 shows an example of 1-4-5-5 data encoding. Fig. 79 shows an example of 1-4-5-5 data encoding, fig. 80 shows an example of 1-4-5-5 data encoding, and fig. 81 shows an example of 3-5-4-3 data encoding. Fig. 82 shows an example of 3-4-5-3 data encoding, fig. 83 shows an example of 3-5-3-4 data encoding, and fig. 84 shows an example of 3-4-3-5 data encoding.

Fig. 85 shows an example of 3-4-5-3 data encoding, fig. 86 shows an example of 3-4-3-5 data encoding, and fig. 87 shows an example of 3-3-5-4 data encoding. Fig. 88 shows an example of 3-3-5-4 data encoding, fig. 89 shows an example of 4-5-3-3 data encoding, and fig. 90 shows an example of 3-5-4-3 data encoding. Fig. 91 shows an example of 3-4-5-3 data encoding, fig. 92 shows an example of 3-3-4-5 data encoding, and fig. 93 shows an example of 3-3-4-5 data encoding.

Fig. 94 shows an example of 3-3-4-5 data encoding, fig. 95 shows an example of 3-4-5-3 data encoding, and fig. 96 shows an example of 3-3-5-4 data encoding. Fig. 97 shows an example of 3-3-4-5 data encoding, fig. 98 shows an example of 4-3-4-4 data encoding, and fig. 99 shows an example of 3-4-4-4 data encoding. Fig. 100 shows an example of 3-4-4-4 data encoding, fig. 101 shows an example of 4-3-4-4 data encoding, and fig. 102 shows an example of 3-4-4-4 data encoding. Fig. 103 shows an example of 3-4-4-4 data encoding, fig. 104 shows an example of 3-4-4-4 data encoding, and fig. 105 shows an example of 3-4-4-4 data encoding. Fig. 106 shows an example of 4-4-3-4 data encoding, and fig. 107 shows an example of 4-4-3-4 data encoding.

In this way, by repeatedly inputting data of a partial page in the first stage and the second stage, data of other pages is inputted and programmed only in one of the first stage and the second stage, it is possible to reduce inter-cell interference, reduce the capacity of the write buffer, and suppress variation in bit error rate when writing data of each bit. In particular, in the case of 1-4-5-5, 1-5-4-5, 3-3-4-5, or 3-5-2-5 data encoding, the number of boundaries of each page of data is equal, and the transition number of the threshold region at the time of programming in the second stage is 3 or less, so that deviation in bit error rate can be suppressed, and mutual interference between cells can be reduced.

(embodiment 3)

Embodiment 3 provides the memory system 1 with a reduced write buffer capacity compared with embodiment 1 and embodiment 2.

The hardware configuration of the memory system 1 according to embodiment 3 is common to the memory systems 1 according to embodiments 1 and 2. In embodiment 3, the page buffer 24 in the nonvolatile memory 3 is continuously held after the first-stage programming is started for the page data that is repeatedly input in the second-stage programming as well as the first-stage programming. Thus, the step of inputting data of the page can be omitted in the programming of the second stage, and the data input of all pages can be made only once. This reduces the capacity of the write buffer.

In the present embodiment, the second phase programming of the word line WLn-1 and the first phase programming of the word line WLn are performed collectively. As such, for the data of the bit that is repeatedly input in the first-stage programming and the second-stage programming among the 1 st to 4 th bits (Lower page, middle page, upper page, top page), the page buffer 24 stores the data of the bit before starting the first-stage programming and can be discarded or invalidated after starting the second-stage programming. In the following, an example of using the same 1-4-5-5 data coding as that described in fig. 6A of embodiment 1 will be described.

In the flowchart of programming shown in fig. 9, the execution timing of the first-stage programming and the second-stage programming deviates, and respective programming commands and programming data inputs are made at the time of the respective programming. In contrast, in the present embodiment, the program command and the program data are inputted in the first stage and the second stage as intensively as possible.

For example, as shown in FIG. 8B, the programming of the first phase of word line WLn and the second phase of word line WLn 1 must be performed continuously, except for the beginning and ending ends of the block. In this embodiment, this part is then input as a unified command. That is, by one command input, the respective program data of Lower page, middle page and Top page of word line WLn and Upper page of word line WLn-1 are inputted collectively. This is an input of the same amount of data as the amount by which the Lower/Middle/Upper/Top page data set (but in this case the same page within the word line WLi) is input by one-time programming command in the case of using Foggy-Fine.

As described above, by intensively inputting the program command and the program data, the frequency of command input and/or polling (periodic check of whether the chip returns from busy to ready) in the control by the memory controller 2 is reduced, and the control of the memory system 1 can be speeded up and simplified.

An example of the writing procedure in the programming sequence according to embodiment 3 will be described with reference to fig. 108 and 109. In fig. 108 and 109, the writing steps in the case of the programming sequence shown in fig. 8B are shown.

Fig. 108 is a flowchart showing a procedure of writing the entire amount of one block according to embodiment 3. One block here has n+1 word lines WLi of word lines WL0 to WLn (n is a natural number). As shown in fig. 108, when writing is started (step S710), the first-stage programming process of the word line WL0 of the strings St0 to St3 is performed (step S712). Thus, the control unit 22 performs the first-stage programming of the word line WL0 of the strings St0 to St3 (step S714).

The control unit 22 performs the first-stage programming of the string st0_word line WL1 and the second-stage programming of the string st0_word line WL0 (step S716).

Next, the control unit 22 performs the first-stage programming of the string st1_word line WL1 and the second-stage programming of the string st1_word line WL0 (step S718). Next, the control unit 22 performs the first-stage programming of the string st2_word line WL1 and the second-stage programming of the string st2_word line WL0 (step S720). Thereafter, the control unit 22 repeatedly performs the same process on each word line WLi of each string.

Next, the first-stage programming of the string st0_word line WLn and the second-stage programming of the string st0_word line WLn-1 are performed (step S722). Next, the control unit 22 performs the first-stage programming of the string st1_word line WLn and the second-stage programming of the string st1_word line WLn-1 (step S724). Thereafter, the control unit 22 repeatedly performs the same process on each word line WLi of each string.

Next, the control unit 22 performs the first-stage programming of the string st3_word line WLn and the second-stage programming of the string st3_word line WLn-1 (step S726). Next, the control unit 22 executes the second-stage programming of the word lines WLn of the strings St0 to St3 (steps S728, S730, S732).

Thus, at the beginning of the block, programming in only the first phase is performed as in embodiment 1, and at the end of the block, programming in only the second phase is performed as in embodiment 1. In this case, only the first-stage programming is performed in accordance with the steps shown in fig. 8B, and only the second-stage programming is performed in accordance with the steps shown in fig. 8C. In the flowchart of fig. 108, the first phase programming of the word line WLn and the second phase programming of the word line WLn-1 are performed intensively except for the beginning and the end of the block. Thus, the frequency of command input and/or polling by the memory controller 2 is reduced, and the processing of the memory system 1 can be speeded up.

Fig. 109 is a flowchart showing the writing procedure in the first and second stages according to embodiment 3. As shown in fig. 109, in the first-stage and second-stage programming, after the first-stage programming is performed, the second-stage programming is performed next. Specifically, first, an input start command of Upper page data of the word line WLn-1 is input from the memory controller 2 to the nonvolatile memory 3 (step S750). Then, the data of the Upper page of the word line WLn-1 is inputted from the memory controller 2 to the nonvolatile memory 3 (step S752).

Next, an input start command of Lower page data of the word line WLn is input from the memory controller 2 to the nonvolatile memory 3 (step S754). Then, the data of the Lower page of the word line WLn is input from the memory controller 2 to the nonvolatile memory 3 (step S756).

Next, an input start command of Middle page data of the word line WLn is input from the memory controller 2 to the nonvolatile memory 3 (step S758). Then, the data of the Middle page of the word line WLn is input from the memory controller 2 to the nonvolatile memory 3 (step S760). The data of the Middle page is not only input to the nonvolatile memory 3 but also stored in the page buffer 24. After storing in the page buffer 24, the Middle data written into the buffer can be discarded or invalidated.

Next, an input start command of Top page data of the word line WLn is input from the memory controller 2 to the nonvolatile memory 3 (step S762). Then, the data of the Top page of the word line WLn is input from the memory controller 2 to the nonvolatile memory 3 (step S764).

Then, the first-stage and second-stage program execution commands are input from the memory controller 2 to the nonvolatile memory 3 (step S766), and the chip becomes busy (step S768).

After that, one or more program voltage pulses are applied to the Lower page, middle page, and Top page of the word line WLn (step S770). Then, in order to confirm whether or not the memory cell has moved beyond the threshold boundary level, data reading of the Lower page and the Top page of the word line WLn is performed (step S772).

Further, it is confirmed whether the number of fail bits of the data in the Lower page and the Top page is smaller than the standard (step S774). When the number of invalidation bits of data in the Lower page and the Top page is equal to or greater than the standard, the processing in steps S770 to S774 is repeated. Also, when the fail bit number of the data is smaller than the standard, the Lower page and Top page data of the word line WLn-1 are read (step S776).

Then, the threshold voltage Vth of the programming destination of the Upper page is determined based on the Lower and Top data of the word line WLn-1 and the data of the Middle page read from the page buffer 24 (step S778). Then, using the determined threshold voltage Vth, data writing into the Upper page of the word line WLn-1 is performed (step S780).

When writing data to the Upper page, one or more programming voltage pulses are applied to the Upper page of word line WLn 1. Then, in order to confirm whether or not the memory cell has moved beyond the threshold boundary level, the Upper page of word line WLn-1 is read for data (step S782).

Further, a verification is performed to confirm whether or not the number of invalid bits of the data in the Upper page is smaller than the standard (step S784). When the number of fail bits of data in the Upper page is equal to or greater than the standard, the programming voltage pulse application, the data reading, and the data verification are repeated. Also, when the number of failure bits of the data is smaller than the standard, it becomes chip ready (step S786).

In addition, in the programming of the first stage for the same word line, the data input start command for a plurality of pages and the order of pages in the data input process are arbitrary, and any page may be input first. In the programming of the second phase for the same word line, the data input start command for a plurality of pages and the order of the pages in the data input process are also arbitrary. However, the order of the respective word line numbers and the programming process of the two phases must be the order shown in fig. 109.

Thus, in FIG. 109, a case is illustrated where the programming of the first phase of word line WLn is performed prior to the programming of the second phase of word line WLn 1. This is because, by performing the programming of the first stage of the word line WLn first, the cell of the word line WLn-1 which is written with the threshold voltage Vth of 16 values is not affected by the neighboring cell.

As described above, in the present embodiment, data of 4 pages, that is, upper page data of the word line WLn-1 and Lower page data, middle page data, and Top page data of the word line WLn, are sequentially input.

In another modification, after the input of the program command, the data of the Lower page, middle page, and Top page of the word line WLn-1 is read as IDL, and then the Lower page, middle page, and Top page of the word line WLn are programmed, and then the threshold voltage Vth of the programming destination of the Upper page of the word line WLn-1 is determined, and the Upper page of the word line WLn-1 is programmed with the determined threshold voltage Vth. By doing so, the data of the Lower page, middle page, and Top page of word line WLn-1 of IDL can be read before being subjected to the inter-cell interference caused by the writing of word line WLn.

Further, the actual execution order of programming by the commands of the first phase of word line WLn and the second phase of word line WLn-1 in the present embodiment taken together may be changed. That is, the Lower page, middle page, and Top page programming of word line WLn shown in FIG. 109, and the Lower page, middle page, and Top page data reading of word line WLn 1, which is IDL, can be exchanged. By performing the data reading of the Lower page, middle page, and Top page of the word line WLn-1 before the programming of the Lower page, middle page, and Top page of the word line WLn, IDL can be performed without being affected by the programming of the Lower page, middle page, and Top page of the word line WLn.

Thus, in embodiment 3, the programming of the second stage of the word line WLn-1 and the programming of the first stage of the word line WLn are intensively performed, and thus the frequency of command input and/or polling is reduced. Therefore, the memory system 1 can be speeded up and control can be simplified.

Fig. 110 is a diagram for explaining the write buffer amount (buffer data amount) in programming according to embodiment 3. In this embodiment, two phases of programming are used in the 1-4-5-5 data encoding. In the programming of this embodiment, in the first stage, data input of 3 pages (Lower page, middle page, and Top page) and programming of the 3 pages (first programming) are performed. In the case of programming in the present embodiment, data input of 1 page (Upper page) and programming of 1 page (second programming) of Upper page are performed in the second phase.

In addition, the word lines WL0, WL1, WL2, and … may be each configured to store data in a write buffer at the time of data input at each stage, or may be each configured to delete data from the write buffer at the time of programming start. For example, if data is input in the first stage, the data is stored in the write buffer. Further, when programming is started in the first stage, the data of the Lower page, the Top page, and the Middle page stored in the write buffer in advance may be deleted. However, the data of the Middle page is also used in the second stage, and thus needs to be stored in the page buffer 24 until the programming in the second stage starts. Similarly, if data is input in the second stage, the data is stored in the write buffer. In addition, when programming is started in the second phase, the data stored in the write buffer in advance may be deleted entirely. Therefore, in the case of programming in this embodiment, the data to be held in the write buffer in advance, that is, the data of the maximum 3 pages, is required, and may be smaller than that in embodiment 1.

As described above, in the present embodiment, since all page data is required only in one-time programming, data written into the buffer can be discarded as long as the data input is completed. Therefore, in the present embodiment, the number of pages that need to be held in the write buffer at the same time can be smaller than in embodiment 1.

In addition, since each page is completed by one data transfer in the present embodiment, the transfer time of page data can be reduced as compared with embodiment 1, and the power consumption at the time of transfer can be reduced.

The page reading process in this embodiment is the same as the process steps described in embodiment 1, and therefore, description thereof is omitted.

In addition, in the present embodiment, in order to newly hold data of a page continuously, the page buffer 24 inside the NAND flash memory needs to be added. In programming of a NAND flash memory in which one string exists within a block as shown in fig. 8A, the amount of page buffer 24 that needs to be increased is the amount of one page of data. In contrast, in programming a NAND flash memory in which 4 strings exist in a block as shown in fig. 8B or 8C, the amount of page buffer 24 that needs to be increased is the amount of 4 pages of data. This is because, after programming of the first phase of one string is performed, programming of the first phase of the other three strings must be performed until programming of the second phase of the same string is performed, and as a result, data of 1 page amount needs to be held for each of 4 all strings.

In the present embodiment, 1-4-5-5 data encoding is described as an example, but various modifications of data encoding are possible, and it is obvious that the above-described embodiments can be realized.

In the above-described embodiments 1 to 3, the case where the nonvolatile memory 3 is configured using the NAND memory 5 has been described, but other types of nonvolatile memories 3 such as ReRAM (Resistive Random Access Memory), MRAM (magnetic-Resistive Random Access Memory), PRAM (Phase Change Random Access Memory), feRAM (Ferroeletric Random Access Memory) may be used.

In the above-described embodiments 1 to 3, the case where the data of 3 pages is written in the first-stage programming and the data of 2 pages is written in the second-stage programming has been described, but the allocation of the number of pages in the first-stage programming and the number of pages in the second-stage programming may be changed. For example, data of 2 pages may be written in the first-stage programming and data of 3 pages may be written in the second-stage programming.

Several embodiments of the present disclosure have been described, but these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments and/or modifications thereof are included in the scope and/or gist of the invention, and are included in the invention described in the claims and the scope equivalent thereto.

Claims

1. A memory system is provided with:

a nonvolatile memory having a plurality of memory cells each capable of storing 4-bit data represented by 1 st to 4 th bits with 16 threshold regions including a 1 st threshold region indicating an erased state in which data has been erased and a 2 nd to 16 th threshold regions indicating a written state in which data has been written at a higher voltage level than the 1 st threshold region; and

A memory controller that causes the nonvolatile memory to perform a 2 nd program for writing the 3 rd bit data after causing the nonvolatile memory to perform a 1 st program for writing the 1 st bit, the 2 nd bit, and the 4 th bit data,

the largest value among the 15 boundaries existing between the 1 st threshold region and the adjacent threshold region among the 16 th threshold region, of the number of 1 st boundaries used to determine the value of the 1 st bit data, the number of 2 nd boundaries used to determine the value of the 2 nd bit data, the number of 3 rd boundaries used to determine the value of the 3 rd bit data, and the number of 4 th boundaries used to determine the value of the 4 th bit data is 5, the second largest value is 4,

the memory controller is configured to cause the nonvolatile memory to perform the 1 st program so that a threshold region in the memory cell becomes a 17 th threshold region indicating an erased state in which data has been erased, and any one of 18 th to 24 th threshold regions indicating a written state in which data has been written, the voltage level of which is higher than that of the 17 th threshold region, based on the 1 st bit, the 2 nd bit, and the 4 th bit data,

The memory controller is configured to cause the nonvolatile memory to perform the 2 nd programming such that a threshold region in the memory cell becomes a certain threshold region among two threshold regions from the 17 th threshold region to the 24 th threshold region to the 1 st threshold region to the 16 th threshold region in accordance with the 3 rd bit data,

the number of threshold regions between the threshold region having the lowest voltage level and the threshold region having the highest voltage level among the two threshold regions is within two,

the memory controller is configured to input the 2 nd bit data and the 3 rd bit data to the nonvolatile memory when the nonvolatile memory is subjected to the 2 nd programming.

2. The memory system according to claim 1,

the memory controller causes the nonvolatile memory to perform the 1 st programming and the 2 nd programming such that the number of the boundaries, the 2 nd bit value, the number of the boundaries, the 3 rd bit value, and the number of the boundaries, the 4 th bit value, which are different, existing in 15 boundaries between adjacent ones of the 1 st threshold region to the 16 th threshold region are sequentially 1, 4, 5, or 1, 5, 4, 5, or 3, 4, 5.

3. A memory system is provided with:

the number of 1 st boundaries used to determine the value of the 1 st bit data, the number of 2 nd boundaries used to determine the value of the 2 nd bit data, the number of 3 rd boundaries used to determine the value of the 3 rd bit data, and the number of 4 th boundaries used to determine the value of the 4 th bit data, which are present in 15 boundaries between adjacent threshold regions of the 1 st threshold region to the 16 th threshold region, are 3, 5, 2, 5 in this order,

4. The memory system according to claim 1 to 3,

the memory controller causes the nonvolatile memory to perform the 1 st programming such that a difference in voltage level between two threshold regions different in value of the 2 nd bit data among the 17 th to 24 th threshold regions is smaller than a difference in voltage level between two threshold regions different in value of the 1 st bit data and smaller than a difference in voltage level between two threshold regions different in value of the 4 th bit data.

5. The memory system according to claim 4,

the memory controller causes the nonvolatile memory to perform the 2 nd programming such that an interval of adjacent threshold regions among 4 threshold regions obtained by performing the 2 nd programming with the 3 rd bit data is wider for the two threshold regions than an interval of the two threshold regions at the 1 st programming in which values of the 2 nd bit data are different.

6. The memory system according to claim 1 to 3,

the 1 st bit is the lower bit of the lowest bit, the 2 nd bit is the next lower median, the 3 rd bit is the next higher upper bit, and the 4 th bit is the first bit of the highest bit.

7. The memory system according to claim 1 to 3,

a 1 st memory unit which is volatile, the 1 st memory unit storing the 1 st to 4 th bits of data,

the data of the bit stored in the 1 st to 4 th bits of the 1 st memory section, which is repeatedly input at the 1 st and 2 nd programming, can be discarded or invalidated after the 2 nd programming is started, and the data of the other bits can be discarded or invalidated after the 1 st programming is started.

8. A memory system according to any one of claims 1 to 3, comprising:

a volatile 1 st storage unit that stores the 1 st to 4 th bits of data; and

a non-volatile 2 nd memory unit that stores data of a bit of the 1 st to 4 th bits, the bit being repeatedly input in the 1 st program and the 2 nd program,

the 1 st to 4 th bit data stored in the 1 st storage part can be discarded or become invalid after the 1 st programming is started,

the data of the 1 st bit to the 4 th bit stored in the 2 nd memory section, which is the bit repeatedly input in the 1 st program and the 2 nd program, is stored in the 2 nd memory section before the 1 st program is started, and can be discarded or become invalid after the 2 nd program is started.

9. The memory system according to claim 8,

the 2 nd memory section is provided in units of word lines.

10. The memory system according to claim 1 to 3,

the plurality of memory cells in the nonvolatile memory have a plurality of 1 st memory cells connected to a 1 st word line and a plurality of 2 nd memory cells connected to a 2 nd word line adjacent to the 1 st word line,

the memory controller causes the 1 st programming to be performed on the 2 nd memory cells after causing the 1 st programming to be performed on the 1 st memory cells, and then causes the 2 nd programming to be performed on the 1 st memory cells.

11. The memory system according to claim 1 to 3,

the nonvolatile memory has at least a 1 st word line and a 2 nd word line to which two or more memory cells are connected,

the memory controller instructs the nonvolatile memory to sequentially perform the 1 st programming for memory cells connected to the 1 st word line and the 2 nd programming for memory cells connected to the 2 nd word line with sequential command and data inputs.

12. The memory system according to claim 1 to 3,

The nonvolatile memory includes a control unit that determines a threshold voltage of data of a bit programmed in the 2 nd program based on data obtained by reading data programmed in the 1 st program, the 2 nd data repeatedly input in the 1 st program and the 2 nd program, and the 3 rd input data programmed in the 2 nd program.

13. The memory system of claim 12,

an error correction unit for reading the data programmed by the 1 st programming and correcting the error,

the control unit determines the threshold voltage of the bit data programmed in the 2 nd program based on the data subjected to error correction by the error correction unit, the 2 nd bit data, and the 3 rd bit input data.