JP6698412B2 - Timing controller, electronic device using the same, vehicle-mounted or medical display device - Google Patents

Description

  The present invention relates to a timing controller that receives image data from a graphic controller or another device and transmits information to a gate driver or a source driver.

  FIG. 1 is a block diagram of an image display system. The image display system 100R includes a display panel 102 such as a liquid crystal panel or an organic EL panel, a gate driver 104, a source driver 106, a graphic controller 110, and a timing controller 200R. The graphic controller 110 generates image data to be displayed on the display panel 102. The pixel (RGB) data included in this image data is transmitted to the timing controller 200R in a serial format.

The timing controller 200R receives image data and generates various control signals/timing signals (synchronization signals). The gate driver 104 sequentially selects the scanning line L _S of the display panel 102 in synchronization with the signal from the timing controller 200R. The RGB data is also supplied to the source driver 106.

  Normally, the timing controller 200R and the graphic controller 110 are connected by a differential serial interface. During the period from the start of activation of the image display system 100R to the establishment of the serial interface link between the timing controller 200R and the graphic controller 110, image data cannot be transmitted and therefore an image cannot be displayed on the display panel 102. Alternatively, if the link is disconnected once due to noise or the like after the link is established, an image cannot be displayed on the display panel 102 until the link is established again. In addition, the same applies when a cable is disconnected or disconnected, or when a part of the serial interface or the graphic controller 110 fails. In this specification, a state in which an image cannot be displayed as described above is referred to as a “display-disabled state”.

  The conventional timing controller 200R may be equipped with a function for displaying some information on the display panel 102 in a display-disabled state. For example, the timing controller 200R holds a predetermined failsafe display pattern 201. Examples of the display pattern 201 include a color bar and a monochrome screen. Then, the timing controller 200R transmits the fail-safe display pattern 201 to the source driver 106 as a substitute for the image data from the graphic controller 110 in the display-disabled state.

JP, 6-317782, A JP, 2002-169524, A

  As a result of examining the image display system 100R of FIG. 1, the present inventor has come to recognize the following problems. In the image display system 100R of FIG. 1, it is possible to prevent the display panel 102 from completely blacking out in the display disabled state. However, the displayable pattern 201 needs to be determined at the design stage of the image display system 100R, and real-time and useful information cannot be displayed.

  The present invention has been made in view of the above problems, and one of exemplary objects of a certain aspect thereof is a timing controller capable of displaying useful information in real time on a display panel in a display-disabled state or a normal state. Is provided.

  One aspect of the present invention relates to a timing controller. The timing controller is a main input interface for receiving input image data and a memory for holding a plurality of segment data corresponding to a plurality of segments forming a segment character, and each segment data is an image frame of the corresponding segment. Based on the memory, which describes the ON/OFF of the upper pixel, the sub input interface that receives the sub data that specifies the segment type character to be displayed, and the sub data of each of the multiple segments and the multiple segment data. A segment decoder for converting a segment type character into a raster image, an image processing circuit for generating output image data to be displayed on a display panel based on at least one of input image data and output data of the segment decoder, and output image data Is output to the data driver.

According to this aspect, it is possible to display, on the display panel, information using an arbitrary segment-type character designated in real time by sub-data instead of a predetermined display pattern. By using the segment type character, it is not necessary to hold bitmap information for each of a plurality of alphabetic and numeric characters, so that the memory on the timing controller side can be small.
In the present specification, the “segment type character” includes characters such as 16 segments, 14 segments and 7 segments, as well as a dot matrix type character composed of a plurality of dots.

The segment decoder receives a first luminance value that designates the color of the segment type character and a second luminance value that designates the background color, and controls the multiplexer based on the multiplexer that selects one and the sub data and the segment data. And a timing generator.
As a result, the segment type character can be made into a raster image with a simple configuration.

The image processing circuit may select one of the input image data and the output data of the segment decoder to generate output image data.
As a result, in the display-disabled state, it is possible to display information using segment characters.

The image processing circuit may generate the output image data by superposing the input image data and the output data of the segment decoder.
As a result, not only in the non-displayable state, but also in the normal state, it is possible to display information using the segment type character.

  The image processing circuit (i) selects one of the input image data and the output data of the segment decoder and generates the output image data, and (ii) superimposes the input image data and the output data of the segment decoder and outputs them. The mode for generating image data may be switchable.

The segment type character may be designed such that two or more segments have the same shape. The segment data of two or more segments having the same shape may include shape data indicating the shape of the segment and data indicating the movement amount.
As a result, the data amount of segment data can be significantly reduced, and the circuit area of the timing controller can be reduced.

The sub-data may include a plurality of bits that indicate on/off of a plurality of segments.
As a result, the segment type character can be freely designed, and the user can use his or her own character.

The sub data may include a character code that specifies a segment type character. The timing controller may include a character decoder that converts a character code into a plurality of bits indicating ON/OFF of a plurality of segments.
In this case, the user may specify the code of the character to be displayed without paying attention to the shape of the segment.

  The sub data may further include first data that specifies the size of the segment type character. The memory may store segment data for each size. As a result, it is possible to increase the visibility or increase the amount of information. For example, a usage method is provided in which the font size is changed according to the importance of information.

  The sub data may further include second data that specifies an interval between the segment type characters. Thereby, visibility can be improved.

  The sub data may further include third data that specifies whether or not the segment type character is transparent.

The sub-input interface may be an SPI (Serial Peripheral Interface) or an I ² C (Inter-Integrated Circuit) interface. Since these are widely used interfaces, they are easy to implement.

In an aspect, the timing controller may be integrated on a single semiconductor substrate.
"Integrated integration" includes the case where all the components of the circuit are formed on the semiconductor substrate and the case where the main components of the circuit are integrated, and some of them are used for adjusting the circuit constants. A resistor or a capacitor may be provided outside the semiconductor substrate.

  Another aspect of the present invention relates to an electronic device. The electronic device may include any of the timing controllers described above.

  Another aspect of the present invention relates to a vehicle-mounted display device or a medical display device. These display devices may include any of the timing controllers described above.

  It should be noted that an arbitrary combination of the above components or a conversion of the expression of the present invention among methods, devices and the like is also effective as an aspect of the present invention.

  According to an aspect of the present invention, useful information can be displayed on a display panel in real time in a display-disabled state or a normal state.

It is a block diagram of an image display system. It is a block diagram of a timing controller according to an embodiment. FIGS. 3A to 3C are views for explaining segment type characters. FIG. 4A is a diagram showing an example of the sub-image, and FIG. 4B is a diagram showing an example of the address map of the register. 5A is a block diagram showing a configuration example of the image processing circuit, and FIG. 5B is a block diagram showing a configuration example of the image processing circuit. It is a block diagram which shows the structural example of a segment decoder. FIGS. 7A and 7B are operation waveform diagrams of the segment decoder of FIG. 8A to 8C are diagrams for explaining compression of segment data. 9A and 9B are diagrams showing a vehicle-mounted display device using a timing controller. It is a perspective view which shows an electronic device. It is a block diagram of a part of timing controller concerning a 1st modification. It is a part block diagram of the timing controller which concerns on a 2nd modification. 13A and 13B are diagrams showing segment type characters according to the seventh modified example. 14A and 14B are diagrams showing segment type characters according to the eighth modification. FIG. 15A is a diagram showing description data representing the segment type character of FIG. 14A, and FIG. 15B is a diagram showing description data representing the segment type character of FIG. 14B. is there. It is a figure which shows a part of timing controller which concerns on an 8th modification.

  Hereinafter, the present invention will be described based on preferred embodiments with reference to the drawings. The same or equivalent constituent elements, members, and processes shown in each drawing are denoted by the same reference numerals, and duplicated description will be omitted as appropriate. Further, the embodiments are merely examples and do not limit the invention, and all the features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In the present specification, "the state in which the member A is connected to the member B" means that the members A and B are electrically connected in addition to the case where the members A and B are physically directly connected. It also includes the case of being indirectly connected via another member that does not affect the connection state.
Similarly, the "state in which the member C is provided between the member A and the member B" means that the member A and the member C are directly connected to each other or the member B and the member C are directly connected to each other. It also includes the case of being indirectly connected via another member that does not affect the connection state.

  FIG. 2 is a block diagram of the timing controller 200 according to the embodiment. The timing controller 200 receives input image data from the graphic controller 110, supplies output image data to the source driver 106, and controls signals/synchronization to the gate driver 104 and the source driver 106, similarly to the image display system 100R of FIG. Output a signal. The timing controller 200 may be a functional IC integrated on one semiconductor substrate.

  The timing controller 200 includes a main input interface 202, an image processing circuit 204, an output interface circuit 208, a sub input interface 210, a memory 212, and a segment decoder 220.

  The main input interface 202, the image processing circuit 204, and the output interface circuit 208 are circuit blocks related to the display of image data from the graphic controller 110, and may be the same as those provided in the conventional timing controller 200R. The main input interface 202 is connected to the graphic controller 110 via the first line 112 and receives the input image data S1. As an interface between the main input interface 202 and the graphic controller 110, a differential high speed serial interface such as LVDS (Low Voltage Differential Signaling) can be adopted.

  The image processing circuit 204 performs various signal processing on the input image data S1 received by the main input interface 202. The signal processing of the image processing circuit 204 is not particularly limited, and a known technique may be used. For example, γ correction, FRC (Frame Rate Control) processing, RGB mapping, etc. are exemplified. The output interface circuit 208 outputs the output image data S2 processed by the image processing circuit 204 to the source driver 106.

  The above is the basic configuration of the timing controller 200. The timing controller 200 can display an image based on the sub data S3 (hereinafter referred to as a sub image) instead of or in addition to the image based on the input image data S1 (hereinafter referred to as a main image). Regarding the display of the sub image, the timing controller 200 is provided with a sub input interface 210, a memory 212, and a segment decoder 220.

  The sub-image is generated by using the segment type character. FIGS. 3A to 3C are views for explaining segment type characters. The segment type character 800 is represented by a combination of ON and OFF of a plurality of segments 802. FIG. 3A shows a 16-segment type character, and the 16 segments 802 are provided with convenient identifiers AP. FIG. 3B shows an example of a code representing a 16 segment type character. A 16-segment character can be represented by 16-bit, that is, 2-byte data. Therefore, if a 2-byte register (214 in FIG. 2) is prepared for each character, the character or symbol to be displayed can be specified uniquely. can do.

  FIG. 3C shows an example of the 16-segment type character. In Fig. 3(c), uppercase alphabets, Arabic numerals, and other symbols +, -, #, * are shown, but in addition, lowercase alphabets, Greek numerals, other symbols, Japanese Hiragana, It is also possible to represent characters in katakana, kanji, and other languages.

Returning to FIG. The sub-input interface 210 is connected to the graphic controller 110 via a second line 114 independent of the first line 112. As the sub input interface 210, for example, a register access type interface such as SPI (Serial Peripheral Interface) or I ² C interface can be adopted.

  The graphic controller 110, instead of or in addition to the input image data S1, generates sub-data S3 designating a segment type character to be displayed on the display. The sub input interface 210 receives the sub data S3 via the second line 114. Due to the independence of the first line 112 and the second line 114, even if the first line 112 fails, or even before the link between the main input interface 202 and the graphic controller 110 is established at system startup, the sub input It should be noted that the interface 210 can receive the sub data S3 from the graphic controller 110.

  FIG. 4A is a diagram showing an example of the sub-image 900. The sub-image 900 displayed on the display panel 102 may include a plurality of segment-type characters 800. In the present embodiment, the regions R1 to RN in which the segment character 800 can be displayed are fixed for simplification of the description and easy understanding. Therefore, in the sub data S3, the information designating the position is not included. It shall not be included. The sub data S3 specifies a character to be displayed for each area R.

  In the present embodiment, as shown in FIG. 3B, the sub-data S3 has a plurality of bits (16 bits=here, 16 bits=indicating ON/OFF of the plurality of segments 802 (A to P) for each character. 2 bytes). As a result, the user of the timing controller 200 can be provided with the degree of freedom in using arbitrary characters.

  FIG. 4B is a diagram showing an example of the address map of the register 214. For example, to the register of the sub input interface 210, an address of 2 bytes is assigned to each region R. For example, addresses 0 to 1 correspond to the region R1 and addresses 2 to 3 correspond to the region R2. The graphic controller 110 writes the value representing the character to be displayed, that is, the sub data S3, at the address corresponding to each area R.

Memory 212, for a plurality of segments (A-P in FIG. 3 (a)), on the pixel on the image frame, holds a plurality of segment data _S4 A to S4 _P describing off. The memory 212 may be a non-volatile memory such as a ROM (Read Only Memory). For example, the segment data S4 _A represents the segment A, and the segment data S4 _B represents the segment B. Details of the segment data S4 will be described later.

  The segment decoder 220 converts the segment type character 800 to be displayed into a raster image (conversion into a bit map format) based on the sub data S3 and the plurality of segment data S4. The output data S5 of the segment decoder 220 is image data (sub-image data) of the segment character 800 designated by the sub-data S3.

  The input image data S1 and the sub-image data S5 generated by the segment decoder 220 are input to the image processing circuit 204. The image processing circuit 204 generates output image data S2 to be displayed on the display panel based on the input image data S1 and the sub image data S5.

  There are several possible variations in the processing by the image processing circuit 204 and its configuration.

  For example, the image processing circuit 204 may select (i) one of the input image data S1 and the sub image data S5 and generate the output image data S2. FIG. 5A is a block diagram showing a configuration example of the image processing circuit 204. The image processing circuit 204 receives the input image data S1 and the sub-image data S5 at its input stage and responds to the control signal SEL1. A multiplexer 205 for selecting one of the two may be provided. The processor 206 in the subsequent stage performs predetermined signal processing on the image data selected by the multiplexer 205. The image processing circuit 204 may select the sub image data S5 before the link between the main input interface 202 and the graphic controller 110 is established. The sub image data S5 may be selected when the interface between the main input interface 202 and the graphic controller 110 is out of order. When the input image data S1 is normally input, the image processing circuit 204 selects the input image data S1. Alternatively, the image processing circuit 204 may select one of the input image data S1 and the sub-image data S5 based on the control data from the graphic controller 110.

  Alternatively, the image processing circuit 204 may (ii) generate the output image data S2 by superimposing the input image data S1 and the sub image data S5. FIG. 5B is a block diagram showing a configuration example of the image processing circuit 204, and may include a synthesizing circuit 207 for superposing the input image data S1 and the sub-image data S5. Processing such as α blending can be used for superimposing the images. Alternatively, the sub-image data S5 may be drawn in the regions R1 to RN in which the sub-image 900 of FIG. 4A is displayed, and the input image data S1 may be drawn in the other regions. The processor 206 subjects the image combined by the combining circuit 207 to predetermined signal processing.

  Alternatively, the main input interface 202 may be switchable between a mode for selecting one of the input image data S1 and the sub-image data S5 and a mode for superimposing them. That is, the functions of both FIG. 5A and FIG. 5B may be provided.

  According to the timing controller 200 according to the embodiment, not the predetermined display pattern as shown in FIG. 1 but the information using the arbitrary segment type character designated in real time by the sub data S3 is displayed on the display panel 102. can do.

  Further, the timing controller 200 uses the segment type character. If the bitmap information of each of a plurality of alphabetic and numeric characters is held, and if one character is X×Y pixels, it is necessary to prepare bitmap data of X×Y bits for each character. Yes, huge memory is required. On the other hand, in this embodiment, the memory of the timing controller can be downsized.

  The present invention extends to various devices and circuits understood as the block diagram and circuit diagram of FIG. 2 or derived from the above description, and is not limited to a specific configuration. Hereinafter, a more specific configuration example will be described for the purpose of helping understanding of the essence of the invention and circuit operation and clarifying them, not for narrowing the scope of the invention.

FIG. 6 is a block diagram showing a configuration example of the segment decoder 220. The segment decoder 220 includes a font color generator 222, a background color generator 224, a multiplexer 226, and a timing generator 228. The font color generation unit 222 generates a first brightness value L1 that specifies the color (font color) of the segment character 800. The background color generator 224 generates a second brightness value L2 that specifies the background color. The multiplexer 226 receives the first luminance value L1 and the second luminance value L2, and selects one according to the selection signal SEL2. The timing generator 228 controls the multiplexer 226 based on the sub data S3 and the segment data S4. For example, the timing generator 228 converts the sub-image designated by the sub-data S3 into a raster image in synchronization with the pixel clock CLK _PIX . As a result, the segment type character can be made into a raster image with a simple configuration. The configuration of the segment decoder 220 is not limited to this.

FIGS. 7A and 7B are operation waveform diagrams of the segment decoder 220 shown in FIG. FIG. 7A shows pixels PIX of three lines (L _i , L _i+1 , L _i+2 ) of the display panel 102. Pixels included in the turned-on segment are shown in black. The timing controller 200 generates RGB data from the upper line to the lower line, from the left pixel to the right pixel in each line, in synchronization with the pixel clock CLK _PIX . As shown in FIG. 7B, the timing generator 228 generates the selection signal SEL2 so as to obtain a sub-image based on the sub-data S3 in synchronization with the pixel clock CLK _PIX .

  Next, the segment data S4 will be described. If the segment character 800 has vertical Y pixels and horizontal X pixels, one character includes X×Y pixels. Therefore, each segment data S4 can be represented by Y×X bits (when not compressed as described later). However, when the number of pixels increases, the capacity of the memory that stores the segment data S4 increases. As an example, if Y=521 and X=380, ROMs of 521×380 bits per segment data and 16×521×380 bits for all segments A to P are required.

  In order to solve this problem, the segment type character 800 of FIG. 3A is designed so that a plurality of segments have the same shape. For example, the first group including the segments A, B, P, L, E, and F has the same shape and the positions are shifted. The second group including the plurality of segments H, J, C, G, N, and D has the same shape, the third group including the plurality of segments I and M has the same shape, and the plurality of segments O. , K has the same shape for the fourth group.

  Therefore, for a group including two or more segments having the same shape, the segment data S4 can be composed of shape data S7 indicating the shape of the segment and data S6 indicating the movement amount. As a result, the data amount of the segment data can be significantly reduced and the circuit area of the timing controller can be reduced.

  8A to 8C are diagrams for explaining compression of segment data. Here, attention is paid to the first group. FIG. 8A shows a segment type character 800 having a font size 521 (height Y=521 pixels, width X=380 pixels) as an example. FIG. 8B shows a shape 804 common to the segments A, B, P, L, E, F of the first group. This shape has a height of y pixels (y<Y) and a width of x pixels (x<X), and this shape 804 can be represented by x×y bits. For example, when x=130 pixels and y=45 pixels, the shape data S7 has 130×45 bits.

Each of the segments A, B, P, L, F, and E represents the common shape data S7 that is moved from a certain reference position (x ₀ , y ₀ ) by Δx in the horizontal direction and Δy in the vertical direction. be able to. The movement of the segment P is shown in FIG. The maximum movement amount in the horizontal direction is X=380 pixels, and the maximum movement amount in the vertical direction is Y=521 pixels. Therefore, the data S6 indicating the movement amount of each segment is (X+Y) bits at most.

That is, for the first group including the segments A, B, P, L, F, E, the amount of segment data is
(I) Shape data S7 (x×y bits) common to a plurality of segments
(Ii) Movement data S6 (X+Y) for each segment x number of segments (6)
Is the sum of That is, the data amount Z of the segment data of the first group when compressed is
Z=x×y+6×(X+Y) bits.
On the other hand, in the case of non-compression, the data amount Z′ of the segment data of the first group is
Z′=(X×Y)×6
Becomes

  Assuming that X=380, Y=521, x=130, and y=45, the compressed data amount is Z=111256 bits, and the uncompressed data amount is Z′=1187880 bits, which is compressed to 1% or less. be able to.

  The segment data can be similarly compressed for the second to fourth groups. The data format of the segment data is not limited to the one described here.

  Finally, the application of the timing controller 200 will be described. 9A and 9B are diagrams showing an in-vehicle display device 600 using the timing controller 200. The in-vehicle display device 600 is embedded in the console 602 in the front of the cockpit, and is installed in the speedometer 604, the tachometer 606 indicating the engine speed, the remaining fuel amount 608, the hybrid vehicle and the electric vehicle from the processor on the vehicle side. For example, the input image data S1 including the remaining amount of the battery is received and displayed (FIG. 9A).

  In such a vehicle-mounted display device 600, when a situation in which the input image data S1 cannot be displayed occurs, the display panel 102 is blacked out, which hinders driving. When the timing controller 200 is mounted on the in-vehicle display 600, even when the input image data S1 cannot be displayed, alternative information (for example, vehicle speed 610, engine speed 612, remaining fuel amount, remaining battery amount, etc.) By generating the sub-data S3 representing the above and inputting it to the in-vehicle display device 600, significant information can be displayed in real time using the segment type character. This can improve safety.

  Alternatively, at the time of turning on the ignition of the vehicle, when the vehicle-mounted display device 600 is activated, a character string such as "PLEASE WAIT..." or the current time is displayed until the input image data S1 can be displayed. , And can be displayed as the sub image data S5.

  The timing controller 200 can also be used in a medical display device. The medical display device displays information required by doctors and nurses during examination, treatment or surgery. In the medical display device, it is possible to display important information (for example, the heart rate and blood pressure of the patient) as the sub-image data S5 even when the input image data S1 cannot be displayed.

  FIG. 10 is a perspective view showing the electronic device 500. The electronic device 500 of FIG. 10 may be a notebook PC, a tablet terminal, a smart phone, a portable game machine, an audio player, or the like. The electronic device 500 includes a graphic controller 110, a display panel 102, a gate driver 104, and a source driver 106 that are built in a housing 502. A transmission device 120 including a differential transmitter, a transmission line, and a differential receiver may be provided between the timing controller 200 and the graphic controller 110.

  The present invention has been described above based on the embodiment. This embodiment is merely an example, and it will be understood by those skilled in the art that various modifications can be made to the combinations of their respective constituent elements and processing processes, and that such modifications are also within the scope of the present invention. is there. Hereinafter, such modified examples will be described.

(First modification)
The data format of the sub data S3 is not limited to that of the embodiment. FIG. 11 is a block diagram of a part of the timing controller 200a according to the first modification. In this modification, the sub data S3′ from the graphic controller 110 includes a character code designating a segment type character. The character code may be an ASCII (American Standard Code for Information Interchange) code. The segment decoder 220 of the timing controller 200a further includes a character decoder 230 that converts a character code into a plurality of bits indicating ON and OFF of a plurality of segments.

  In this modification, usable characters and symbols are limited to standard numbers and alphabets. The user may specify the code of the character to be displayed without being aware of the shape of the segment.

(Second modified example)
FIG. 12 is a block diagram of a part of the timing controller 200b according to the second modification. The timing controller 200b further includes an image generation unit 232 that generates local sub data S3b. The image generation unit 232 writes the sub data S3b in the register 214. The segment decoder 220b uses the sub data S3a input from the outside to the sub input interface 210 and the sub data S3b generated inside the timing controller 200b, which is written in the register 214, to generate a raster image of the segment character. Turn into. This makes it possible to display debug information, error information, etc. of the timing controller 200b.

(Third modification)
The format of the sub input interface 210 is not limited to the register access type. For example, similar to the first line 112, differential serial transmission may be used, or it can be designed with an arbitrary interface.

(Fourth modification)
In the embodiment, the font sizes and positions of the plurality of segment-type characters 800 forming the sub-image 900 are fixed, but the present invention is not limited thereto. For example, the font size of the segment character 800 may be selectable from a plurality of font sizes. In this case, the segment data S4 may be prepared for each font size, and the data specifying the font size may be added to the sub data S3.

  Further, the drawing position of each of the plurality of segment type characters 800 may be designated. That is, the coordinates of the plurality of regions R1 to RN may be variable. In this case, the sub data S3 may include data instructing the character spacing. Although the case where the sub-image 900 has one line has been described with reference to FIG. 4A, the sub-image 900 may include a plurality of lines of character strings.

  In addition, the sub-data S3 may include parameters that specify drawing positions in the height direction, such as bottom-alignment, top-alignment, and center-alignment, for a plurality of segment-type characters 800 drawn in the same line.

  Further, the sub data S3 may further include third data that specifies whether or not the segment type character is transparent.

(Fifth Modification)
When the sub-images are superimposed and drawn with the main image as the background, the pixel sequence corresponding to the main image may be input as the second luminance value L2 in FIG.

(Sixth Modification)
Although the 16-segment type character has been described in the embodiment, the present invention is not limited thereto, and is a 14-segment type (A and B in FIG. 3A are one segment, E and F are one segment), or 7 segments. A mold (A, H, J, P, G, N, F in FIG. 3A) or the like may be used.

(Seventh modification)
13A and 13B are diagrams showing segment type characters according to the seventh modification. The segment type character 800a is a dot matrix type character composed of a plurality of dots 806. Although a 4×7 dot matrix is shown in FIG. 13, the number of dots in the vertical and horizontal directions is not particularly limited. The plurality of dots 806 can be understood as the plurality of segments 802. Note that dot 806 includes multiple pixels rather than one pixel on display panel 102. Further, the dot shape 806 is not limited to a rectangle, and may be a circle, a rhombus, an octagon, or any other shape.

  The memory 212 holds, for each of the plurality of dots 806, a plurality of segment data describing ON/OFF of pixels on the image frame. In the dot matrix type character, a plurality of dots 806 can have the same shape, and the segment data can be compressed by the method described with reference to FIGS.

  A 4×7 dot matrix character can be represented by 28-bit data. Therefore, if a 4-byte (32-bit) register (214 in FIG. 2) is prepared for each character, the character or symbol to be displayed can be displayed. Can be uniquely specified.

(8th modification)
14A and 14B are diagrams showing segment type characters according to the eighth modification. FIG. 14A shows an uppercase letter A, and FIG. 14B shows an uppercase letter C. In this modification, each segment-type character is composed of a combination of segments of a plurality of types (four types A to D in this example). The shape of each segment is not limited to a rectangle.

  In this modified example, the plurality of segment data S4 described above correspond to a plurality of types of segments, and each segment data S4 has a shape of a corresponding type of segment (for example, ON/OFF of a pixel on an image frame). Describe.

  In this modified example, each segment-type character has (i) type data that specifies the type of each of the plurality of segments used therein, and (ii) position data that specifies the position of each of the plurality of segments used therein, including.

The description data indicating a certain character “#” will be represented as S30[#]. 15A is a diagram showing the description data S30 _[A] representing the segment type character "A" of FIG. 14A, and FIG. 15B is the segment type character "A" of FIG. 14B. It is a figure which shows the description data S30 _[C] showing "C".

The segment type character 300 of FIG. 14A is composed of eight segments 301 to 308. Therefore, the description data S30 _[A] includes type data S31 that specifies the type of each of the eight segments 301 to 308, and position data S32 that specifies the position of each of the eight segments 301 to 308. The position may be, for example, the coordinates of the upper left vertex of each segment, or may be another vertex.

The segment-type character 400 in FIG. 15A is composed of eight segments 401 to 408. Therefore, the description data S30 _[C] includes type data S31 that specifies the type of each of the eight segments 401 to 408 and position data S32 that specifies the position of each of the eight segments 401 to 408.

The description data S30 may be defined for each character desired to be used. For example, 26 pieces of description data S30 _{[A] to} S30 _{[ Z]} can be defined for uppercase alphabets A to _Z , and 26 pieces of description data S30 _{[a] to} S30 _[a] can be defined for lowercase alphabets a to z _. Can be defined, and ten descriptive data S30 _{[0] to} S30 _[9] can be defined for the numbers 0-9. In addition, you may define Greek letters, Hiragana, Katakana, and Kanji.

  FIG. 16 is a diagram showing a part of the timing controller 200c according to the eighth modification. In the memory 212, in addition to the segment data S4 for each type, type data S30 for each segment type character is stored. The segment decoder 220 receives the sub data S3 designating the segment type character to be displayed, and reads the description data S30 corresponding to the segment type character.

For example, when the sub data S3 indicates the display of the alphabet "A", the segment of type A is (x ₁ , y ₁ ) for the segment 301 based on the type data S30 _[A] of FIG. To place. Similarly, for the segment 302, the segment of type A is arranged at (x ₂ , y ₂ ). As a result, arbitrary characters and symbols can be displayed.

  Although the present invention has been described by using specific words and phrases based on the embodiments, the embodiments merely show the principle and application of the present invention, and the embodiments are defined in the claims. Many modifications and changes in arrangement are possible without departing from the concept of the present invention.

100... Image display system, 102... Display panel, 104... Gate driver, 106... Source driver, 110... Graphic controller, 112... First line, 114... Second line, 200... Timing controller, 201... Display pattern, 202... Main input interface, 204... Image processing circuit, 205... Multiplexer, 206... Processor, 207... Combining circuit, 208... Output interface circuit, 210... Sub input interface, 212... Memory, 214... Register, 220... Segment decoder, 222... Font color generation unit, 224... Background color generation unit, 226... Multiplexer, 228... Timing generator, 230... Character decoder, 232... Image generation unit, S1... Input image data, S2... Output image data, S3... Sub data, S4... Segment data, S5... Sub image data, L1... First luminance value, L2... Second luminance value, 500... Electronic device, 600... In-vehicle display, 800... Segment character, 900... Sub image.

Claims (19)

A main input interface for receiving input image data,
A memory for holding a plurality of segment data corresponding to a plurality of segments forming a segment type character, each segment data describing ON/OFF of a pixel on an image frame of the corresponding segment. When,
A sub input interface that receives sub data that specifies the segment type character to be displayed,
A segment decoder for converting the segment-type character into a raster image based on the sub-data and the plurality of segment data,
An image processing circuit that generates output image data to be displayed on a display panel based on at least one of the input image data and the output data of the segment decoder,
An output interface for outputting the output image data to a data driver,
Bei to give a,
The segment type character is designed so that two or more segments have the same shape,
The timing controller , wherein the segment data of the two or more segments having the same shape includes shape data indicating a shape of the segment and data indicating a movement amount in a vertical direction and a horizontal direction . The segment decoder is
A multiplexer that receives a segment luminance value corresponding to ON and a background luminance value corresponding to OFF and selects one of them,
A timing generator for controlling the multiplexer based on the sub-data and the segment data,
The timing controller according to claim 1, further comprising:   The timing controller according to claim 1 or 2, wherein the image processing circuit selects one of the input image data and the output data of the segment decoder to generate the output image data.   The timing controller according to claim 1, wherein the image processing circuit generates the output image data by superimposing the input image data and the output data of the segment decoder. The image processing circuit,
(I) a mode in which one of the input image data and the output data of the segment decoder is selected to generate the output image data,
(Ii) a mode in which the input image data and the output data of the segment decoder are overlapped to generate the output image data,
3. The timing controller according to claim 1, wherein the timing controller is switchable. The sub-data includes a plurality of bits for turning on and off the plurality of segments,
The sub input interface, a timing controller according to any one of claims 1 to 5, characterized in that it comprises a register for storing said plurality of bits.   A main input interface for receiving input image data,
  A memory for holding a plurality of segment data corresponding to a plurality of segments forming a segment type character, each segment data describing ON/OFF of a pixel on an image frame of the corresponding segment. When,
  A sub input interface that receives sub data that specifies the segment type character to be displayed,
  A segment decoder for converting the segment-type character into a raster image based on the sub-data and the plurality of segment data,
  An image processing circuit that generates output image data to be displayed on a display panel based on at least one of the input image data and the output data of the segment decoder,
  An output interface for outputting the output image data to a data driver,
  Equipped with
  The sub-data includes a plurality of bits for turning on and off the plurality of segments,
  The timing controller, wherein the sub-input interface includes a register that stores the plurality of bits. The sub data includes a character code that specifies the segment type character,
7. The timing controller according to claim 1, wherein the timing controller further includes a character decoder that converts the character code into a plurality of bits indicating ON and OFF of the plurality of segments. The segment-type character is composed of a combination of segments of different shapes,
The plurality of segment data correspond to a plurality of types of segments,
The memory holds description data for each of the segment type characters,
The description data includes type data that specifies the type of each of the plurality of segments used for the corresponding segment-type character, and (ii) position data that indicates the position of each of the plurality of segments used for it. The timing controller according to any one of claims 1 to 5, which is characterized.   A main input interface for receiving input image data,
  A memory for holding a plurality of segment data corresponding to a plurality of segments forming a segment type character, each segment data describing ON/OFF of a pixel on an image frame of the corresponding segment. When,
  A sub input interface that receives sub data that specifies the segment type character to be displayed,
  A segment decoder for converting the segment-type character into a raster image based on the sub-data and the plurality of segment data,
  An image processing circuit that generates output image data to be displayed on a display panel based on at least one of the input image data and the output data of the segment decoder,
  An output interface for outputting the output image data to a data driver,
  Equipped with
  The segment type character is composed of a combination of a plurality of types of segments having different shapes,
  The plurality of segment data correspond to a plurality of types of segments,
  The memory holds description data for each of the segment type characters,
  The description data includes type data that specifies the type of each of the plurality of segments used for the corresponding segment-type character, and (ii) position data that indicates the position of each of the plurality of segments used for it. A characteristic timing controller. A main input interface for receiving input image data,
A sub-input interface for receiving sub-data designating a segment-type character to be displayed, wherein the segment-type character is composed of a combination of a plurality of types of segments having different shapes, and a sub-input interface,
(I) For each segment type, hold segment data that describes its shape, and (ii) for each segment-type character, specify type data for each of the plurality of segments used for it, and A memory that holds position data indicating the position of each of the plurality of segments used, and
A segment decoder for converting the segment type character designated by the sub data into a raster image based on the sub data, the segment data, the type data and the position data,
An image processing circuit that generates output image data to be displayed on a display panel based on at least one of the input image data and the output data of the segment decoder,
An output interface for outputting the output image data to a data driver,
A timing controller comprising: The sub input interface, SPI (Serial Peripheral Interface) or timing controller according to any one of the ^{I 2 C (Inter-Integrated Circuit} ) according to claim 1 to 11, characterized in that an interface. The sub-data, the timing controller according to any of claims 1 12, further comprising a first data to specify the size of the segmented character. The sub-data, the timing controller according to any one of claims 1 to 13, further comprising a second data specifying the spacing of the segmented character. The sub-data, the timing controller according to any of claims 1 to 14, characterized by further comprising a third data specifying the presence or absence of transmission of the segmented character. The segment decoder selects one of the sub data externally input to the sub input interface and the sub data generated inside the timing controller, and based on the selected sub data, the segment type character. 16. The timing controller according to claim 1, wherein the timing controller can be converted into a raster image. The timing controller as claimed in any of claims 1 16, characterized in that it is integrated on a single semiconductor substrate. Vehicle or display device of the medical, characterized in that it comprises a timing controller according to any of claims 1-17. An electronic apparatus comprising: a timing controller according to any of claims 1-17.

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