JP6593336B2 - Device manufacturing method - Google Patents

Description

The present invention also relates layered structure constituting at least a part of an electronic device formed on transcription on a substrate for device fabrication how to manufacture the electronic device by transferring to a transfer substrate.

  Japanese Patent Application Laid-Open No. 2006-302814 discloses a method for forming an organic electroluminescence layer. Briefly, first, a hole transport layer is formed on the first endless belt by a coating method (inkjet method or the like), and a light emitting layer is formed on the second endless belt by a coating method (inkjet method or the like). The electron transport layer is formed on the endless belt 3 by a coating method (inkjet method or the like). Then, the hole transport layer formed on the first endless belt is transferred to the sheet-like substrate supplied from the supply roll, and then the light emitting layer formed on the second endless belt is transferred to the hole transport layer. The organic electroluminescence layer is formed by transferring the electron transport layer formed on the third endless belt onto the light emitting layer.

  However, for example, when manufacturing an electronic device including a semiconductor element such as a thin film transistor, the film is formed in a vacuum space where the film thickness and the like are easily controlled in order to improve the performance and yield of the semiconductor element and stabilize the characteristics. It is desirable to perform this, and it is difficult to manufacture a highly accurate electronic device by a transfer method such as the technique described in Japanese Patent Application Laid-Open No. 2006-302814.

  On the other hand, a method for manufacturing an electronic device on a glass substrate and transferring the completed electronic device from the glass substrate to another final substrate (for example, a flexible resin film or a plastic plate) is widely and generally performed. However, in this case, an electronic device manufacturer forms a film in a vacuum space to form a layer constituting the electronic device on a glass substrate, or development processing, etching processing, CVD processing, or sputtering processing using photolithography. Etc. are repeated according to the laminated structure of the electronic device to create an electronic device, and then the completed electronic device is transferred to the final substrate. Therefore, electronic device manufacturers add to the manufacturing costs of creating a finished electronic device on a glass substrate using equipment that performs a number of deposition processes that form the layer structure of the electronic device on the glass substrate. In addition, a manufacturing cost (equipment) for transferring (transferring) the electronic device on the glass substrate onto the final substrate is also required. For this reason, it is difficult to reduce the product price of the final electronic device (LCD-type or organic EL-type display panel, touch panel, etc.), which places a heavy burden on the manufacturer of the electronic device.

A first aspect of the present invention is a device manufacturing method in which at least a part of a laminated structure of a thin film transistor constituting an electronic device is formed on a first substrate, and then the laminated structure is transferred onto a second substrate. A first conductive layer made of a conductive material is uniformly formed on the first substrate, and a functional layer made of at least one of an insulating material and a semiconductor is formed on the first conductive layer ; Forming any one of the source electrode, the drain electrode, and the gate electrode of the thin film transistor in the second conductive layer made of a conductive material formed on the functional layer by processing using an optical patterning method , A first step of forming the stacked structure of the first conductive layer, the functional layer, and the second conductive layer; and the first substrate so that the second conductive layer is positioned on the second substrate side. And the second group Preparative temporarily close or close contact so, the second step of transferring the layered structure on the second substrate, the first conductive became transferred surface of the laminated structure on the second substrate the layer by machining process using the photo-patterning method, including a further processing step of forming the other of the source electrode and the drain electrode and the gate electrode of the thin film transistor.

It is a figure which shows the structure of the film-forming apparatus which forms a thin film on the board | substrate of 1st Embodiment. It is a figure which shows the structure of the laminator apparatus for transcribe | transferring the laminated structure formed in the 1st board | substrate of 1st Embodiment to the 2nd board | substrate. It is a flowchart which shows an example of the process of the manufacturing method of bottom contact type TFT. It is a flowchart which shows an example of the process of the manufacturing method of bottom contact type TFT. 5A to 5F are cross-sectional views showing the manufacturing progress state of the TFT manufactured by the steps shown in FIGS. 6A to 6D are cross-sectional views showing the manufacturing progress state of the TFT manufactured by the steps shown in FIGS. 3 and 4. It is a flowchart which shows an example of the process of the manufacturing method of top contact type TFT. It is a flowchart which shows an example of the process of the manufacturing method of top contact type TFT. 9A to 9D are cross-sectional views showing the manufacturing progress state of the TFT manufactured by the steps shown in FIGS. 7 and 8. 10A to 10C are cross-sectional views showing the manufacturing progress state of the TFT manufactured by the steps shown in FIGS. 10 is a flowchart showing an example of a process of a method for manufacturing a top contact type TFT in Modification 1 of the first embodiment. 10 is a flowchart showing an example of a process of a method for manufacturing a top contact type TFT in Modification 1 of the first embodiment. 13A to 13F are cross-sectional views showing the manufacturing progress state of the TFT manufactured by the steps shown in FIGS. 11 and 12. 14A to 14F are cross-sectional views showing the manufacturing progress state of the TFT manufactured by the steps shown in FIGS. In the modification 3 of 1st Embodiment, it is sectional drawing when an alignment mark is formed in the 2nd conductive layer. In the modification 3 of 1st Embodiment, it is sectional drawing when a window part is formed in the 1st conductive layer. It is a figure which shows the structure of the laminator apparatus in the modification 4 of 1st Embodiment. It is a figure which shows the structure of the laminator apparatus in the modification 5 of 1st Embodiment. It is a figure which shows an example of the pixel circuit of the organic electroluminescent display in 2nd Embodiment. FIG. 20 is a diagram showing a specific structure of the pixel circuit shown in FIG. 19. FIG. 21 is a flowchart showing an example of a process of the pixel circuit manufacturing method shown in FIG. 20. FIG. FIG. 21 is a flowchart showing an example of a process of the pixel circuit manufacturing method shown in FIG. 20. FIG. It is sectional drawing of the laminated structure formed on the 1st board | substrate by the process of step S101-step S105 of FIG. It is sectional drawing of the laminated structure by which the 2nd conductive layer was processed by the process of step S106-step S111 of FIG. It is a top view of the laminated structure shown in FIG. It is sectional drawing when the laminated structure currently formed in the 1st board | substrate by step S113 of FIG. 21 was transcribe | transferred to the 2nd board | substrate. It is sectional drawing of the laminated structure by which the 1st conductive layer was processed by the process of step S114-step S118 of FIG. It is a top view of the laminated structure shown in FIG. FIG. 28 is a cross-sectional view of the contact hole portion shown in FIG. 27 when the functional layer is etched by the processes of steps S119 to S122 of FIG. FIG. 23 is a cross-sectional view when an electroless plating contactor is formed in the contact hole shown in FIG. 29 by the process of step S123 of FIG. It is a figure which shows the modification of the film-forming apparatus shown in FIG. It is a figure which shows the other structural example of the laminated structure of top contact type TFT, and the transfer example of the laminated structure. It is a figure which shows the state which used the planarization film | membrane in the case of the transfer shown in FIG. FIG. 34A to FIG. 34D are diagrams showing a manufacturing process of the laminated structure when the electronic device laminated structure shown in FIG. 23 to FIG. 30 is improved. It is a figure which shows the planar arrangement structure of the laminated structure shown in FIG. 34D formed on the 1st board | substrate. 36A is a view showing a state immediately after the stacked structure shown in FIG. 34D formed on the first substrate is transferred to the second substrate by the transfer step, and FIG. 36B is a view showing the first conductive layer shown in FIG. 36A. It is a figure which shows a mode that the gate electrode, the source electrode, etc. were formed in FIG. It is a figure which shows an example of the planar arrangement configuration of TFT of FIG. 36B.

  A device manufacturing method and a transfer substrate according to an aspect of the present invention will be described in detail below with reference to the accompanying drawings by listing preferred embodiments. In addition, the aspect of this invention is not limited to these embodiment, What added the various change or improvement is included.

[First Embodiment]
FIG. 1 is a diagram showing a configuration of a film forming apparatus 10 that forms a thin film on a substrate (hereinafter referred to as a first substrate) P1. The first substrate P1 is a flexible sheet-like substrate (sheet substrate), and the film forming apparatus 10 is a supply roll obtained by winding the first substrate (transfer substrate, supporting substrate) P1 in a roll shape. 12 has a so-called roll-to-roll structure in which the first substrate P1 supplied from 12 is sent out, and after the film-forming process is performed on the sent first substrate P1, the collection roll 14 winds up. . The first substrate P1 has a strip shape in which the moving direction of the first substrate P1 is the longitudinal direction (long) and the width direction is the short direction (short). The film forming apparatus 10 includes a chamber 16, a vacuum pump 18 that sucks air in the chamber 16 to evacuate the chamber 16, a base material 20 that is a film forming material (thin film material), guide rollers GR <b> 1 to GR <b> 3, A film-forming rotary drum 22 is further provided.

  The supply roll 12 and the collection roll 14 are provided with a motor (not shown). When the motor rotates, the first substrate P1 is unloaded from the supply roll 12 and the first substrate P1 sent out by the collection roll 14 is wound. Taken. Further, the film-forming rotary drum 22 conveys the first substrate P1 while rotating, and supports the part where the film is formed on the circumferential surface. As a result, the first substrate P <b> 1 is transported toward the collection roll 14 along the outer peripheral surface (circumferential surface) of the film-forming rotary drum 22. The guide rollers GR1 to GR3 guide the path of the first substrate P1 being transported. The film-forming rotary drum 22 is provided with a motor (not shown), and the film-forming rotary drum 22 rotates as the motor rotates.

  The film forming apparatus 10 forms a thin film (layer) on the first substrate P1 by vapor deposition or sputtering. When film formation is performed by vapor deposition, the base material 20 is heated by a method such as resistance heating, electron beam, high frequency induction, or laser, and vaporized or sublimated film forming raw materials are attached to the first substrate P1 to form a thin film. Form. When film formation is performed by sputtering, ionized argon gas is collided with the base material 20 to release the molecules of the base material 20, and the free molecules are attached to the first substrate P1 to form a thin film. Therefore, the collection roll 14 winds up the first substrate P1 having a thin film (layer) formed on the surface thereof. The film forming apparatus 10 may form a thin film by CVD (Chemical Vapor Deposition). The film forming apparatus 10 may use a mist deposition method (mist CVD method) as disclosed in, for example, International Publication No. 2013/176222 pamphlet.

  Using such a film forming apparatus 10, a number of thin films can be continuously stacked on the first substrate P1. In other words, by using the collection roll 14 that has wound the first substrate P <b> 1 having the first layer formed on the surface thereof as the supply roll 12 of another film forming apparatus 10, a new film forming apparatus 10 can perform a new operation. A layer (second layer) is laminated on the first layer. In addition, thin films of different materials can be stacked by changing the base material 20 as a film forming raw material when stacking. By laminating this thin film, at least a part of a laminated structure constituting an electronic device including a semiconductor element such as a thin film transistor (TFT) is formed on the first substrate P1 as a supporting substrate. Can do.

For example, when a bottom contact type TFT (thin film transistor) is formed, a metal material (Cu, Al, Mo, etc.) or an ITO thin film (first conductive material) is formed on the surface of the first substrate P1 by the film forming apparatus 10. Layer), a thin film (insulating layer) of an insulating material (SiO ₂ , Al ₂ O ₃ etc.) and a thin film (second conductive layer) of a metal-based material (Cu, Al, Mo etc.) are laminated in this order. Is formed on the first substrate P1. When a top contact type TFT is formed, a thin film (first conductive layer) of a metal material (Cu, Al, Mo, etc.), an oxide semiconductor (IGZO, ZnO, etc.), Silicon (α-Si
), Or a thin film (semiconductor layer) such as an organic semiconductor (pentacene), an insulating material (SiO ₂ , A
l ₂ O ₃ etc.) thin film (insulating layer), metal-based material (Cu, Al, Mo etc.) and ITO thin film (second conductive layer) are laminated in order to form a laminated structure constituting the TFT. It can be formed on the first substrate P1.

  The first substrate P1 thus formed with the laminated structure is processed by a non-vacuum processing apparatus such as photolithography (photo patterning) and etching, which will be described in detail later, and an electrode layer and an insulating layer for a semiconductor element Then, it is processed so as to have a pattern shape such as a wiring layer or a semiconductor layer. The laminated structure of the first substrate P1 processed into such a pattern shape is transferred to a substrate (hereinafter referred to as a second substrate) P2. FIG. 2 is a diagram showing a configuration of a laminator device 30 for transferring the laminated structure formed (supported) on the first substrate P1 to the second substrate P2 (product substrate). The laminator device 30 is, for example, a low-temperature thermal transfer type device that transfers the laminated structure formed on the first substrate P1 to the second substrate P2 at a low temperature of 100 degrees or less. The laminator device 30 includes supply rolls 32 and 34, a pressure heating roller 36, collection rolls 38 and 40, and guide rollers GR5 and GR6.

  The supply roll 32 is a roll of the first substrate P1 having a laminated structure formed on the surface thereof, and carries the first substrate P1 toward the collection roll 38. The supply roll 34 is obtained by winding the second substrate P2 onto which the laminated structure is transferred in a roll shape, and carries the second substrate P2 toward the collection roll 40. Similarly to the first substrate P1, the second substrate P2 is a flexible sheet-like substrate (sheet substrate, transferred substrate), and the moving direction of the second substrate P2 is the longitudinal direction (long), and the width It has a strip shape whose direction is the short direction (short length).

  The pressurizing and heating roller 36 sandwiches the first substrate P1 supplied from the supply roll 32 and the second substrate P2 supplied from the supply roll 34 from both sides so as to be in close contact with each other to perform press-bonding and heating. . Thereby, the laminated structure formed on the first substrate P1 can be transferred to the second substrate P2. That is, the laminated structure formed on the first substrate P1 is softened by heating (for example, a low temperature of 100 degrees or less) by the pressure heating roller 36, and the first substrate P1 softened by pressure bonding by the pressure heating roller 36. The upper laminated structure is transferred to the second substrate P2. An elastic body is used for the surface of the pressure heating roller 36, and it is preferable to arbitrarily set the temperature and pressure (force) of the pressure heating roller 36 according to the transfer material.

  The collection roll 38 collects the first substrate P1 that has passed through the pressure heating roller 36, that is, the first substrate P1 from which the laminated structure has been peeled off. The collection roll 40 winds the second substrate P2 that has passed through the pressure heating roller 36, that is, the second substrate P2 to which the laminated structure is transferred (the second substrate P2 having the laminated structure formed on the surface). to recover. The guide roller GR5 guides the first substrate P1 supplied from the supply roll 32 to the pressure heating roller 36. The guide roller GR6 guides the second substrate P2 supplied from the supply roll 34 to the pressure heating roller 36. It is a guide.

  Here, for the first substrate P1 and the second substrate P2, for example, a foil (foil) made of a metal or an alloy such as a resin film or stainless steel is used. Examples of the resin film material include polyethylene resin, polypropylene resin, polyester resin, ethylene vinyl copolymer resin, polyvinyl chloride resin, cellulose resin, polyamide resin, polyimide resin, polycarbonate resin, polystyrene resin, and vinyl acetate resin. Of these, those including at least one of them may be used. Further, the thickness and rigidity (Young's modulus) of the first substrate P1 and the second substrate P2 are caused by buckling or irreversible wrinkles due to buckling in the first substrate P1 and the second substrate P2 when transported. It may be in a range that does not exist. As a base material of the first substrate P1 and the second substrate P2, films such as PET (polyethylene terephthalate) and PEN (polyethylene naphthalate) having a thickness of about 25 μm to 200 μm are typical of suitable sheet substrates.

  Since the first substrate P1 and the second substrate P2 may receive heat in processing performed on the first substrate P1 and the second substrate P2, a substrate having a material whose thermal expansion coefficient is not significantly large is selected. It is preferable. For example, the thermal expansion coefficient can be suppressed by mixing an inorganic filler with a resin film. The inorganic filler may be, for example, titanium oxide, zinc oxide, alumina, or silicon oxide. Moreover, the 1st board | substrate P1 and the 2nd board | substrate P2 may be a single-layer body of ultra-thin glass with a thickness of about 100 μm manufactured by a float process or the like, and the resin film and foil described above may be applied to this ultra-thin glass. The laminated body which bonded etc. may be sufficient.

  In the film forming apparatus 10 as shown in FIG. 1, since the first substrate P1 may be heated to, for example, about 100 ° C. to 300 ° C. during film formation, the base material of the first substrate P1 is particularly heat resistant. Good polyimide resin, ultra-thin sheet glass, or ultra-thin metal foil sheet (copper foil, stainless steel foil, aluminum foil rolled to a thickness of several tens of μm to several hundred μm) or the like is desirable. Further, the first substrate P1 does not necessarily need to be a long sheet substrate that can be wound up in a roll shape, and the first substrate P1 is a single wafer cut into a size that matches the size of the electronic device (or circuit board) to be manufactured. It may be a sheet substrate, a glass substrate, or a metal plate.

  Next, a manufacturing method of the TFT will be described. The structure of the TFT is roughly classified into a bottom gate type structure and a top gate type structure. In the first embodiment, a manufacturing process of a bottom gate type TFT will be described. Description of the manufacturing process is omitted. In addition, since bottom-gate TFTs are classified into bottom contact type and top contact type, first, a method for manufacturing a bottom contact type TFT will be described, and then a method for manufacturing a top contact type TFT will be described.

(About manufacturing method of bottom contact type TFT)
3 and 4 are flowcharts showing an example of the steps of the method for manufacturing the bottom contact type TFT. FIGS. 5A to 5F and FIGS. 6A to 6D are manufactured by the steps shown in FIGS. It is sectional drawing which shows the manufacture progress state of TFT made. First, in step S1 of FIG. 3, as shown in FIG. 5A, a release layer 50 is formed on the first substrate P1. For example, the release layer 50 may be formed by applying a fluorine-based material or an alkali-dissolving release agent (a material soluble in alkali) to the surface of the first substrate P1, and the photosensitive alkali-dissolving film may be formed. The release layer 50 may be formed by laminating the formed dry film resist (DFR) on the first substrate P1. Examples of the alkali dissolving release agent include a mixture of a binder resin and a carboxyl group. The release layer 50 is for facilitating the peeling of the laminated structure from the first substrate P1.

Then, as shown in FIG. 5B, the laminated structure 52 is formed on the first substrate P1 (first step). This laminated structure 52 is made of a metal-based material (conductive material such as Cu, Al, Mo, Au, etc.) or ITO (conductive) deposited on the first substrate P1 (on the peeling layer 50) with a predetermined thickness. Thin film (first conductive layer) 52a and a thin film of insulating material (insulating material such as SiO ₂ and Al ₂ O ₃ ) deposited on the first conductive layer 52a at a predetermined thickness. (Functional layer) 52b, a metal-based material (conductive material such as Cu, Al, Mo, Au) or ITO (conductive material) deposited on the functional layer 52b with a predetermined thickness (Second conductive layer) 52c. In addition, when the material of the 1st conductive layer 52a and the 2nd conductive layer 52c which comprises the laminated structure 52 is made into copper (Cu), the material of the 1st board | substrate P1 is also made into copper (Cu), and the thermal expansion coefficient is arrange | equalized. It is good.

  Therefore, first, in step S2, the first conductive layer 52a is formed (deposited) on the first substrate P1 (peeling layer 50). In step S3, a functional layer 52b, which is an insulating layer, is formed (deposited) on the first conductive layer 52a. In step S4, a second conductive layer 52c is further formed (deposited). Thereby, the laminated structure 52 is formed on the first substrate P1. The first conductive layer 52a, the functional layer 52b, and the second conductive layer 52c are continuously formed on the first substrate P1 by using the film forming apparatus 10 as shown in FIG. Note that the first conductive layer 52a functions as an electrode layer for the source and drain electrodes and a wiring layer for wiring accompanying the source and drain electrodes. The second conductive layer 52c functions as an electrode layer of the gate electrode and a wiring layer of wiring accompanying the gate electrode. Here, in order to improve the electrical characteristics (mobility, on / off ratio, leakage current, etc.) of the TFT, the interface between the first conductive layer 52a and the functional layer 52b, or the functional layer 52b and the second conductive layer 52c. The interface with is desirably flattened on the order of submicron or less. For this purpose, it is desirable that the surface of the first substrate P1 on the side of the release layer 50 is also planarized on the order of submicron or less.

  Thereafter, the first substrate P1 on which the multilayer structure 52 is formed is subjected to an etching process using a photolithographic method, and as shown in FIG. 5C, the second conductive layer 52c is subjected to a gate electrode and wiring associated therewith. Is formed (first step). In FIG. 5C, only the gate electrode is shown.

  Since the etching process using the photolithography method is a well-known technique, it will be briefly described. In step S5, a photoresist layer is formed on the second conductive layer 52c. Formation of the photoresist layer can be easily performed by using a liquid resist by a roller printing method, a die coating method, a spray method, or by laminating a photoresist layer of a dry film resist (DFR) on the second conductive layer 52c. Can be implemented. In step S6, the formed photoresist layer is exposed to a predetermined pattern (pattern of gate electrodes and wirings associated therewith) using ultraviolet rays, and in step S7, development is performed (in a developer such as TMAH). By immersing the first substrate P <b> 1), the portion of the photoresist layer exposed to the ultraviolet rays is removed. Thereby, a predetermined pattern (resist image) is formed in the photoresist layer. Next, in step S8 after the cleaning and drying of the first substrate P1, a predetermined pattern is formed by immersing the first substrate P1 on which the laminated structure 52 is formed in a corrosive liquid (for example, ferric oxide). Etching is performed using the photoresist layer as a mask to form a gate electrode and wiring associated therewith in the second conductive layer 52c. In step S9, the photoresist layer on the second conductive layer 52c is peeled off, and the first substrate P1 is cleaned. Thereby, the laminated structure 52 as shown in FIG. 5C is obtained. The first substrate P1 may be cleaned using an alkaline cleaning solution such as NaOH.

  Then, in step S10, as shown in FIG. 5D, an adhesive layer 54 is formed by applying an adhesive to the surface side (laminated structure 52 side) of the first substrate P1 on which the laminated structure 52 is formed. . The adhesive layer 54 is for facilitating transfer (adhesion) of the laminated structure 52 formed on the first substrate P1 to the second substrate P2. As this adhesive, for example, an adhesive for dry lamination, a UV (ultraviolet) curable adhesive that changes from a liquid to a solid in response to light energy of ultraviolet light, or a thermosetting adhesive may be used. In the first embodiment, an adhesive for dry lamination is used.

  In the case of the adhesive for dry lamination, the first substrate P1 and the second substrate P2 are temporarily brought into close contact or in close contact so that the second conductive layer 52c is located on the second substrate P2 side. The laminated structure 52 formed on the substrate P1 is transferred to the second substrate P2 (second step). This transfer is transferred by the laminator device 30 as shown in FIG. That is, the laminator device 30 is formed by rolling the first substrate P1 in which the peeling layer 50, the laminated structure 52, and the adhesive layer 54 are laminated in the above order from the surface side of the first substrate P1. By using as the supply roll 32, the laminated structure 52 formed on the first substrate P1 can be transferred to the second substrate P2. At this time, the release layer 50 remains on the first substrate P1 side without being transferred to the second substrate P2 side.

  More specifically, first, as shown in FIG. 5E, the adhesive layer 54 formed on the laminated structure 52 is adhered to the surface of the second substrate P2 (step S11), and as shown in FIG. Thus, the laminated structure 52 is peeled from the first substrate P1 (step S12). Thereby, the laminated structure 52 on the first substrate P1 is transferred to the second substrate P2. By this transfer, the laminated structure 52 is formed on the second substrate P2 in an inverted state. That is, the second conductive layer 52c, the functional layer 52b, and the first conductive layer 52a constituting the stacked structure 52 are stacked on the second substrate P2 in the above order from the surface side of the second substrate P2. Thus, the first conductive layer 52a is exposed. The second substrate P <b> 2 on which the laminated structure 52 is transferred by the laminator device 30 is taken up by the collection roll 40. When the peeling layer 50 is peeled off from the first substrate P1 and transferred to the second substrate P2, the peeling layer 50 is removed and the second substrate P2 is cleaned. The second substrate P2 may be cleaned using an alkaline cleaning solution such as NaOH. Since the release layer 50 is soluble, it is removed from the first conductive layer 52a by a solvent.

  Then, using the collection roll 40 as a supply roller, the second substrate P2 unloaded from the supply roller is subjected to an etching process using a photolithography method, and as shown in FIG. 6A, the first conductive layer 52a. A source electrode and a drain electrode and a wiring associated with the source electrode and the drain electrode are formed (fourth step). FIG. 6A shows only the source electrode and the drain electrode.

  The formation of the source electrode and the like by etching using photolithography will be briefly described. First, in step S13 in FIG. 4, a photoresist layer is formed on the surface side (first conductive layer 52a side) of the second substrate P2. To do. As described in step S5, the photoresist layer is formed by transferring a dry film resist (DFR) or applying a liquid resist. In step S14, the formed photoresist layer is exposed to a predetermined pattern (a pattern of the source electrode and the drain electrode and wiring associated with the source electrode and the drain electrode) using ultraviolet rays, and in step S15, the development is performed. I do. Thereby, a predetermined pattern is formed in the photoresist layer. Next, in step S16, the second substrate P2 on which the laminated structure 52 is formed is immersed in a corrosive solution (for example, ferric oxide), and etching is performed using the photoresist layer on which a predetermined pattern is formed as a mask. Processing is performed to form a source electrode, a drain electrode, and the like in the first conductive layer 52a. In step S17, the photoresist layer on the first conductive layer 52a is peeled off, and the second substrate P2 is cleaned. Thereby, the laminated structure 52 as shown to FIG. 6A is obtained.

  The source electrode and the drain electrode need to be precisely aligned (superposed) with the gate electrode (second conductive layer 52c) further below the functional layer (insulating layer) 52b immediately below. Therefore, the exposure apparatus (drawing apparatus) used in the exposure process in step S14 is formed by the second conductive layer 52c on the first substrate P1 together with the gate electrode in the gate electrode formation process in steps S5 to S9 in FIG. Based on the alignment sensor that optically detects the alignment mark to be formed via the functional layer (insulating layer) 52b or directly, and the detection position of the mark, a predetermined pattern (source electrode, And a function of precisely adjusting the relative positional relationship between the ultraviolet light corresponding to the drain electrode and the associated wiring pattern) and the second substrate P2.

  In step S18, as shown in FIG. 6B, Au substitution plating is performed on the source electrode and the drain electrode of the first conductive layer 52a (fourth step). Au (gold) 56 applied by this substitution plating process is for lowering the resistance at the contact interface between the source and drain electrodes and the semiconductor layer described later (increasing electron mobility).

  After that, in step S19, as shown in FIG. 6C, a thin film (semiconductor layer) 58 of semiconductor (IGZO, ZnO, etc.) is formed on the second substrate P2 (on the first conductive layer 52a) (fourth). Process). Then, an etching process using a photolithography method is performed to process the semiconductor layer 58 as shown in FIG. 6D (fourth step). That is, a photoresist layer is formed on the semiconductor layer 58 in step S20, a predetermined pattern is exposed to the formed photoresist layer using ultraviolet rays in step S21, and development is performed in step S22. Also in this exposure, the alignment mark is detected by the alignment sensor, and the ultraviolet irradiation position is precisely positioned so that the portion of the semiconductor layer 58 to be left crosses between the drain electrode and the source electrode precisely. .

  Thereby, a predetermined pattern is formed in the photoresist layer. Next, in step S23, the second substrate P2 is immersed in a corrosive liquid (for example, hydrogen fluoride), and an etching process is performed using the photoresist layer on which a predetermined pattern is formed as a mask. Is processed. As a result, as shown in FIG. 6D, at least the semiconductor layer 58 between the source electrode and the drain electrode can be left, and other unnecessary semiconductor layers 58 can be removed. Thereafter, in step S24, the photoresist layer on the semiconductor layer 58 is peeled off, and the second substrate P2 is cleaned. Through these steps, a bottom contact type TFT as shown in FIG. 6D is formed on the second substrate P2. The semiconductor layer 58 may be an organic semiconductor or an oxide semiconductor. In this case, after patterning with a resist in advance, a semiconductor liquid material is selectively applied to a region including between the source electrode and the drain electrode (channel portion), and then the lift-off method is used to form the source electrode and the drain electrode. A semiconductor layer 58 may be formed therebetween.

  Among the steps described above, at least the steps S1 to S4 in FIG. 3 (FIGS. 5A and 5B) are performed by the supplier of the first substrate P1, and the steps after the steps performed by the supplier are electronic. It may be performed by a device manufacturer. For example, the supplier may perform steps S1 to S4 in FIG. 3, and the manufacturer may perform steps S5 to S24 in FIG. 3 (FIGS. 5C to 6D). In the present embodiment, the first substrate P1 (the supporting substrate of the laminated structure 52) manufactured through the steps S1 to S4 in FIG. 3 is wound as an intermediate product in a roll shape, or a predetermined state In a state of being cut into a single sheet with a length of 2 mm, it is supplied to the manufacturer of the electronic device.

  Thus, for example, the supplier of the first substrate P1 performs the process of steps S1 to S4 in FIG. 3 (a process that requires a vacuum processing apparatus), and the process of steps S5 to S24 in FIG. By performing the TFT (electronic device) manufacturer (the process that does not require a vacuum processing apparatus), the burden on the electronic device manufacturer can be reduced, and a highly accurate electronic device can be easily manufactured. . In other words, in order to manufacture a highly accurate electronic device, it is necessary to form at least a part of the laminated structure 52 constituting the electronic device in a vacuum space. Since the film does not have to be applied, the burden on the electronic device manufacturer is reduced. Further, the manufacturer of the electronic device only needs to form the electronic device by using the first substrate P1 on which the laminated structure 52 is formed. Therefore, the number and arrangement of the electronic devices are arbitrarily determined and the electronic device is determined. The degree of freedom in designing the arrangement, connection, bus line, etc. of the thin film transistors constituting the electronic device can be improved. In addition, even a manufacturer who does not have a large number of vacuum deposition apparatuses, coating apparatuses, or sputtering apparatuses necessary for forming all the layers constituting the electronic device can easily manufacture high-performance electronic devices. be able to.

(About manufacturing method of top contact type TFT)
7 and 8 are flowcharts showing an example of steps of a method for manufacturing a top contact type TFT. FIGS. 9A to 9D and FIGS. 10A to 10C are manufactured by the steps shown in FIGS. It is sectional drawing which shows the manufacture progress state of TFT made. First, in step S31 of FIG. 7, a release layer 70 is formed on the first substrate P1, as shown in FIG. 9A. This step is the same as step S1 in FIG.

Then, as shown in FIG. 9B, a laminated structure 72 is formed on the first substrate P1 (first step). The laminated structure 72 is made of a metal-based material (conductive material such as Cu, Al, Mo, Au, etc.) or ITO (conductive) deposited on the first substrate P1 (on the release layer 70) with a predetermined thickness. Thin film (first conductive layer) 72a and a semiconductor (material exhibiting semiconductor characteristics such as IGZO, ZnO, silicon, and pentacene) deposited on the first conductive layer 72a at a predetermined thickness. (Semiconductor layer) 72b1, a thin film (insulating layer) 72b2 of an insulating material (insulating material such as SiO ₂ and Al ₂ O ₃ ) deposited on the semiconductor layer 72b1 at a predetermined thickness, and an insulating layer 72b2 And a metal-based material (conductive material such as Cu, Al, Mo, Au, etc.) and a thin film (second conductive layer) 72c of ITO (conductive material) deposited on the substrate at a predetermined thickness. Is done. The semiconductor layer 72b1 and the insulating layer 72b2 constitute a functional layer 72b. Here again, the base material of the first substrate P1 is a heat-resistant polyimide resin, ultra-thin sheet glass, or ultra-thin metal foil sheet (100 to 300 ° C.) in consideration of heating during film formation (100 to 300 ° C.). A copper foil, a stainless steel foil, an aluminum foil) rolled to a thickness of several tens of micrometers to several hundreds of micrometers may be used. The release layer 70 is also made of a fluorine-based material, an alkali-dissolving release agent, a release agent based on an inorganic material, or a silicon release agent, like the release layer 50 described with reference to FIGS. Etc. can be used.

  Therefore, first, in step S32, the first conductive layer 72a is formed (deposited) on the first substrate P1 (peeling layer 70). In step S33, the semiconductor layer 72b1 is formed (deposited) on the first conductive layer 72a, and in step S34, the insulating layer 72b2 is further formed (deposited) to form the functional layer 72b. Thereafter, in step S35, the second conductive layer 72c is formed (deposited) on the functional layer 72b. Thereby, the laminated structure 72 is formed on the first substrate P1. The first conductive layer 72a, the semiconductor layer 72b1, the insulating layer 72b2, and the second conductive layer 72c are continuously formed on the first substrate P1 by using the film forming apparatus 10 described above. The first conductive layer 72a functions as an electrode layer for a source electrode and a drain electrode and a wiring layer for wiring accompanying the source electrode and the drain electrode. The second conductive layer 72c functions as an electrode layer of the gate electrode and a wiring layer of wiring associated with the gate electrode. In the above configuration, when the first substrate P1 and the first conductive layer 72a are made of a metal-based material (for example, Cu), a resin film such as PET is formed when the semiconductor layer 72b1 is formed on the first conductive layer 72a. Since it can be heated to a temperature much higher than the glass transition temperature (for example, 200 ° C. or higher), the orientation (crystallization) of the organic semiconductor material or the oxide semiconductor material is performed well, and the electrical characteristics of the TFT (for example, Mobility) can be dramatically improved. In addition, it is possible to planarize at least the interface between the first conductive layer 72a and the semiconductor layer 72b1 and the interface between the insulating layer 72b2 and the second conductive layer 72c on the order of submicron or less. Contributes to improved electrical characteristics.

  Thereafter, the first substrate P1 on which the multilayer structure 72 is formed is subjected to an etching process using a photolithography method, and as shown in FIG. 9C, the gate electrode and the wiring associated therewith are formed on the second conductive layer 72c. Is formed (first step). In FIG. 9C, only the gate electrode is shown.

  The formation of a gate electrode and the like by etching using photolithography will be briefly described. First, in step S36, a photoresist layer is formed on the second conductive layer 72c. As described in step S5 of FIG. 3, the photoresist layer is formed by transferring a dry film resist, applying a resist solution, or the like. In step S37, the formed photoresist layer is exposed to a predetermined pattern (a pattern such as a gate electrode and wiring associated therewith) using ultraviolet rays, and in step S38, development is performed (in a developer such as TMAH). Immerse the first substrate P1). Thereby, a predetermined pattern is formed in the photoresist layer. Next, in step S39, the first substrate P1 on which the laminated structure 72 is formed is immersed in a corrosive liquid (for example, ferric oxide or the like), and the photoresist layer on which a predetermined pattern is formed is used as a mask. Etching is performed to form a gate electrode or the like in the second conductive layer 72c. In step S40, the photoresist layer on the second conductive layer 72c is peeled off, and the first substrate P1 is cleaned. Thereby, the laminated structure 72 as shown in FIG. 9C is obtained. The first substrate P1 may be cleaned using an alkaline cleaning solution such as NaOH.

  Then, in step S41 of FIG. 8, as shown in FIG. 9D, an adhesive is applied to the front surface side (laminated structure 72 side) of the first substrate P1 on which the laminated structure 72 is formed, whereby the adhesive layer 74 is applied. Form.

  Next, a laminated structure formed on the first substrate P1 by temporarily bringing the first substrate P1 and the second substrate P2 in close proximity or in close contact so that the second conductive layer 72c is positioned on the second substrate P2 side. The body 72 is transferred to the second substrate P2 (second step). This transfer is transferred by the laminator device 30 described above. That is, the first substrate P1 obtained by laminating the peeling layer 70, the laminated structure 72, and the adhesive layer 74 in the order described above from the surface side of the first substrate P1 is wound around the supply roll 32 of the laminator device 30 in a roll shape. It is set in the state where it is set. The laminator device 30 can transfer the laminated structure 72 formed on the first substrate P1 to the second substrate P2. At this time, the release layer 70 for facilitating the peeling of the multilayer structure 72 from the first substrate P1 is not transferred to the second substrate P2 side but remains on the first substrate P1 side.

  First, as shown in FIG. 10A, the adhesive layer 74 formed on the multilayer structure 72 is adhered to the surface of the second substrate P2 (step S42), and the multilayer structure is formed by the release layer 70 as shown in FIG. 10B. 72 is peeled from the first substrate P1 (step S43). Thereby, the laminated structure 72 on the first substrate P1 is transferred to the second substrate P2. By this transfer, the laminated structure 72 is formed on the second substrate P2 in an inverted state. That is, the second conductive layer 72c, the functional layer 72b, and the first conductive layer 72a constituting the stacked structure 72 are stacked on the second substrate P2 in the above order from the surface side of the second substrate P2. Thus, the first conductive layer 72a is exposed. The second substrate P2 to which the laminated structure 72 has been transferred by the laminator device 30 is taken up by the collection roll 40. When the peeling layer 70 is peeled off from the first substrate P1 and transferred to the second substrate P2, the peeling layer 70 is removed and the second substrate P2 is cleaned. Since the release layer 70 is soluble, it is removed from the first conductive layer 72a by a solvent.

  Then, using the collection roll 40 as a supply roller, the second substrate P2 unloaded from the supply roller is subjected to an etching process using a photolithography method, and as shown in FIG. 10C, the first conductive layer 72a. A source electrode and a drain electrode and a wiring associated with the source electrode and the drain electrode are formed (fourth step). In FIG. 10C, only the source electrode and the drain electrode are shown.

  The formation of the source electrode and the like by etching using photolithography will be briefly described. First, in step S44, a photoresist layer is formed on the surface side (first conductive layer 72a side) of the second substrate P2. The photoresist layer is formed by dry film resist, coating, or the like as described in step S5 of FIG. In step S45, the formed photoresist layer is exposed to a predetermined pattern (a pattern of the source electrode and drain electrode and wirings attached to the source electrode and drain electrode) using ultraviolet rays, and developed in step S46. I do. Thereby, a predetermined pattern is formed in the photoresist layer. Next, in step S47, the second substrate P2 on which the laminated structure 72 is formed is immersed in a corrosive liquid (for example, ferric oxide), and etching is performed using the photoresist layer on which a predetermined pattern is formed as a mask. Processing is performed to form a source electrode, a drain electrode, and the like on the first conductive layer 72a. In step S48, the photoresist layer on the first conductive layer 72a is peeled off, and the second substrate P2 is cleaned. Through such a process, a top contact type TFT as shown in FIG. 10C is formed on the second substrate P2. The second substrate P2 may be cleaned using an alkaline cleaning solution such as NaOH.

  Among the steps described above, at least the steps S31 to S35 of FIG. 7 (FIGS. 9A and 9B) are performed by the supplier of the first substrate P1, and the steps after the steps performed by the supplier are electronic. It may be performed by a device manufacturer. For example, the supplier may perform steps S31 to S35 in FIG. 7, and the manufacturer may perform steps S36 to S48 in FIG. 7 (FIGS. 9C to 10C).

  Thus, for example, the supplier of the first substrate P1 performs steps S31 to S35 in FIG. 7, and the TFT (electronic device) manufacturer performs steps S36 to S48 in FIG. By doing so, the burden on the manufacturer of the electronic device can be reduced, and a highly accurate electronic device can be easily manufactured. In other words, in order to manufacture a highly accurate electronic device, it is necessary to form a film of at least a part of the laminated structure 72 constituting the electronic device in a vacuum space. Since the film does not have to be applied, the burden on the electronic device manufacturer is reduced. In addition, the manufacturer of the electronic device only needs to form the electronic device using the first substrate P1 on which the laminated structure 72 is formed. Therefore, the number and arrangement of the electronic devices are arbitrarily determined and the electronic device is determined. The degree of freedom in designing the arrangement, connection, bus line, etc. of the thin film transistors constituting the electronic device can be improved. In addition, even a manufacturer who does not have a large number of vacuum deposition apparatuses, coating apparatuses, or sputtering apparatuses necessary for forming all the layers constituting the electronic device can easily manufacture high-performance electronic devices. be able to. Also in the present embodiment, the first substrate P1 (supporting base material of the laminated structure 72) manufactured through the steps S31 to S35 in FIG. 7 is wound in a roll shape as an intermediate product, or predetermined In a state of being cut into a single sheet with a length of 2 mm, it is supplied to the manufacturer of the electronic device.

[Modification of First Embodiment]
The following modifications are possible for the first embodiment.

  (Modification 1) In Modification 1, a laminated structure is formed while an etching process using a photolithography method is performed for manufacturing a top contact type TFT. FIG. 11 and FIG. 12 are flowcharts showing an example of steps of a method for manufacturing a top contact type TFT according to the first modification. FIGS. 13A to 13F and FIGS. 14A to 14F are FIGS. It is sectional drawing which shows the manufacture progress state of TFT manufactured by the process shown in FIG. First, in step S61 of FIG. 11, as shown in FIG. 13A, a release layer 80 is formed on the first substrate P1. The formation process of this peeling layer 80 is the same as that of step S1 of FIG.

Next, in step S62, as shown in FIG. 13B, a thin film (insulating material) of an insulating material (SiO ₂ , Al ₂ O ₃ or the like) deposited on the first substrate P1 (on the peeling layer 80) with a predetermined thickness. Layer) 82 is formed. The insulating layer 82 is formed on the first substrate P1 by using the film forming apparatus 10 described above. The insulating layer 82 has a function as a passivation and may also function as an etching stopper.

  In step S63, as shown in FIG. 13C, a metal-based material (conductive material such as Cu, Al, Mo or the like) deposited on the first substrate P1 (on the insulating layer 82) with a predetermined thickness. ) Thin film (first conductive layer) 84a is formed (first step). The first conductive layer 84a functions as an electrode layer for a source electrode and a drain electrode and a wiring layer for wiring accompanying the source electrode and the drain electrode. The first conductive layer 84a is formed on the first substrate P1 by using the film forming apparatus 10 described above.

  Thereafter, an etching process using a photolithography method is performed to form a source electrode and a drain electrode and wirings associated with the source electrode and the drain electrode in the first conductive layer 84a as shown in FIG. Process). At this time, etching of the release layer 80 is prevented by the insulating layer 82 that also functions as an etching stopper. In FIG. 13D, only the source electrode and the drain electrode are shown.

  The formation of the source electrode and the like by etching using photolithography will be briefly described. First, in step S64, a photoresist layer is formed on the first conductive layer 84a. The photoresist layer is formed by dry film resist, coating, or the like as described in step S5 of FIG. Then, in step S65, a predetermined pattern (a pattern of the source electrode and drain electrode and wiring associated with the source electrode and drain electrode) is exposed to the formed photoresist layer using ultraviolet rays, and in step S66, development is performed. I do. Thereby, a predetermined pattern is formed in the photoresist layer. Next, in step S67, the first substrate P1 on which the first conductive layer 84a is formed is immersed in a corrosive liquid (for example, ferric oxide), and the photoresist layer on which a predetermined pattern is formed is used as a mask. Etching is performed to form a source electrode, a drain electrode, and the like on the first conductive layer 84a. In step S68, the photoresist layer on the first conductive layer 84a is peeled off, and the first substrate P1 is cleaned.

  In step S69, as shown in FIG. 13E, a thin film (semiconductor layer) of a semiconductor (IGZO, ZnO, etc.) deposited on the first substrate P1 (on the first conductive layer 84a) with a predetermined thickness. ) 84b1 is formed (first step). The semiconductor layer 84b1 is formed on the first substrate P1 by using the film forming apparatus 10 described above. Next, an etching process using a photolithography method is performed to process the semiconductor layer 84b1 as illustrated in FIG. 13F (first step). That is, in step S70, a photoresist layer is formed on the semiconductor layer 84b1. The photoresist layer is formed by dry film resist, coating, or the like as described in step S5 of FIG. In step S71, a predetermined pattern is exposed to the formed photoresist layer using ultraviolet rays, and development is performed in step S72. Thereby, a predetermined pattern is formed in the photoresist layer. Next, in step S73, the first substrate P1 is immersed in a corrosive liquid (for example, hydrogen fluoride), and an etching process is performed using the photoresist layer on which a predetermined pattern is formed as a mask, and the semiconductor layer 84b1. Is processed. Accordingly, as shown in FIG. 13F, at least the semiconductor layer 84b1 between the source electrode and the drain electrode can be left, and the other unnecessary semiconductor layer 84b1 can be removed. In step S74, the photoresist layer is peeled off and the first substrate P1 is cleaned.

Thereafter, in step S75 of FIG. 12, as shown in FIG. 14A, an insulating material (SiO ₂ , Al ₂ O _3, etc.) deposited on the surface side (semiconductor layer 84b1 side) of the first substrate P1 with a predetermined thickness. ) Thin film (insulating layer) 84b2 is formed (first step). The insulating layer 84b2 is formed on the first substrate P1 by using the film forming apparatus 10 described above. The semiconductor layer 84b1 and the insulating layer 84b2 constitute a functional layer 84b.

  Then, in step S76, as shown in FIG. 14B, a metallic material (Cu, Al, Mo, etc., deposited on the first substrate P1 (on the insulating layer 84b2) with a predetermined thickness is deposited. Film) (second conductive layer) 84c. The second conductive layer 84c is formed on the first substrate P1 by using the film forming apparatus 10 described above. The second conductive layer 84c functions as an electrode layer of the gate electrode and a wiring layer of wiring accompanying the gate electrode. The first conductive layer 84a, the functional layer 84b, and the second conductive layer 84c constitute a laminated structure 84.

  Next, an etching process using a photolithography method is performed to form a gate electrode and a wiring associated therewith in the second conductive layer 84c as shown in FIG. 14C (first step). In FIG. 14C, only the gate electrode is shown. In the step shown in FIG. 14C, the first substrate P1 on which the second conductive layer 84c is formed is subjected to an etching process using a photolithography method for forming a gate electrode and a wiring associated therewith. Thereby, a TFT is formed on the first substrate P1.

  The formation of a gate electrode and the like by etching using photolithography will be briefly described. First, in step S77, a photoresist layer is formed on the second conductive layer 84c. The photoresist layer is formed by dry film resist, coating, or the like as described in step S5 of FIG. In step S78, the formed photoresist layer is exposed to a predetermined pattern (a pattern of a gate electrode and wiring associated therewith) using ultraviolet light, and development is performed in step S79. Thereby, a predetermined pattern is formed in the photoresist layer. Next, in step S80, the first substrate P1 is immersed in a corrosive liquid (for example, ferric oxide), and an etching process using the photoresist layer on which a predetermined pattern is formed as a mask is performed. A gate electrode and a wiring associated therewith are formed on the two conductive layer 84c. In step S81, the photoresist layer on the second conductive layer 84c is peeled off, and the first substrate P1 is cleaned. The laminated structure 84 is formed on the first substrate P1 through the processes of Step S63 of FIG. 11 to Step S81 of FIG.

  In step S82, as shown in FIG. 14D, an adhesive layer 86 is formed by applying an adhesive on the first substrate P1 on which the laminated structure 84 is formed, that is, on the second conductive layer 84c. . The adhesive layer 86 is for facilitating the transfer (adhesion) of the laminated structure 84 formed on the first substrate P1 to the second substrate P2. As this adhesive, for example, a UV curable resin may be used. In this case, after the adhesive layer 86 is formed, the adhesive layer 86 is irradiated with ultraviolet rays.

  Next, in step S83, the first substrate P1 and the second substrate P2 are temporarily brought into close contact or in close contact so that the second conductive layer 84c is located on the second substrate P2 side, as shown in FIG. 14E. The laminated structure 84 formed on the first substrate P1 is transferred to the second substrate P2 (second step). This transfer is transferred by the laminator device 30 described above. That is, the first substrate P1 in which the peeling layer 80, the insulating layer 82, the laminated structure 84, and the adhesive layer 86 are laminated in the above order from the surface side of the first substrate P1 is rolled. The laminated structure 84 formed on the first substrate P1 can be transferred to the second substrate P2 by being used as the supply roll 32 of the laminator device 30. Thereby, the laminated structure 84 is formed on the second substrate P2 in an inverted state. That is, the second conductive layer 84c, the functional layer 84b, and the first conductive layer 84a constituting the stacked structure 84 are stacked on the second substrate P2 in this order from the surface side of the second substrate P2. . At this time, the peeling layer 80 remains on the first substrate P1 side without being transferred to the second substrate P2 side. The second substrate P <b> 2 on which the laminated structure 84 is transferred by the laminator device 30 is taken up by the collection roll 40. Through such a process, a top contact type TFT as shown in FIG. 14E is formed on the second substrate P2.

  Note that the insulating layer 82 may be processed as shown in FIG. 14F by performing an etching process using a photolithography method after the laminated structure 84, that is, the TFT is transferred onto the second substrate P2. (Fourth step). By the step shown in FIG. 14F, at least the insulating layer 82 between the source electrode and the drain electrode remains, and the other unnecessary insulating layer 82 is removed.

  Among the steps described above, at least the steps shown in step S61 in FIG. 11 to step S81 in FIG. 12 (FIGS. 13A to 14C) are performed by the supplier of the first substrate P1, and the steps performed by the supplier are performed. The later steps may be performed by the electronic device manufacturer. For example, the supplier may perform step S61 in FIG. 11 to step S82 in FIG. 12, and the manufacturer may perform step S83 in FIG. 12 (FIG. 14E).

  Thus, for example, the supplier of the first substrate P1 performs the process from step S61 in FIG. 11 to step S82 in FIG. 12, and the electronic device manufacturer performs at least the process in step S83 in FIG. The burden on the device manufacturer can be reduced, and a highly accurate electronic device can be manufactured.

  (Modification 2) In the modification 1, the insulating layer 82 is formed between the release layer 80 and the first conductive layer 84a. However, in the modification 2, the insulating layer 82 is not formed. That is, in the second modification, step S62 in FIG. 11 is not performed. Therefore, after step S61 in FIG. 11, step S63 is performed. For example, the passivation layer may not be provided, and the insulating layer 82 may not be provided between the release layer 80 and the first conductive layer 84a when the release layer 80 is not likely to be etched. In this case, since the insulating layer 82 is not originally formed, there is no need to process the insulating layer 82 by performing an etching process using a photolithography method as shown in FIG. 14F.

  (Modification 3) The supplier of the first substrate P1 may provide the manufacturer with the first substrate P1 on which the alignment mark Ks is formed. The alignment mark Ks is a reference mark for relatively aligning (aligning) a predetermined pattern exposed in the exposure region W on the substrate and the substrate. The alignment mark Ks is optically detected by an imaging device with a microscope, so that the position of the substrate (position in the longitudinal direction of the substrate, position in the lateral direction, tilted state) or the state of distortion in the plane of the substrate can be detected. Can be detected. For example, the alignment marks Ks are formed at regular intervals along the longitudinal direction (longitudinal direction) of the substrate on both ends in the width direction of the substrate.

  For example, when the supplier of the first substrate P1 forms the laminated structure 52 (72) on the first substrate P1 as shown in FIG. 5B or FIG. 9B, the photolithography method is used as shown in FIG. The alignment mark Ks may be formed on the second conductive layer 52c (72c) by performing the etching process (third step). And you may make it perform the process after FIG. 5C (FIG. 9C) using the 1st board | substrate P1 in which the alignment mark Ks was formed. In this case, the first conductive layer 52a (72a) becomes the surface side of the second substrate P2 and the second conductive layer 52c (72c) becomes the deep side of the second substrate P2 by the transfer, so that the formed alignment mark Ks is It is hidden by the first conductive layer 52a (72a). Therefore, after the transfer (for example, when forming the source electrode and the drain electrode), the first conductive layer 52a (in the region facing the alignment mark Ks as shown in FIG. 16) is etched by photolithography. The window 90 may be provided by removing 72a). The window 90 may be provided by not forming the first conductive layer 52a (72a) in the region facing the alignment mark Ks. This saves the trouble of removing the first conductive layer 52a (72a) in the region facing the alignment mark Ks. Since the functional layer 52b (72b) is made of a transmissive material, the alignment mark Ks can be imaged with an optical alignment system such as a microscope, but the functional layer 52b (72b) In the case of being made of a non-permeable material, the functional layer 52b (72b) may be provided with the window 90. Note that the window 90 is an opening formed for imaging the alignment mark Ks. Alternatively, the alignment mark Ks may be formed on the first conductive layer 52a (72a), and the window 90 may be formed on the second conductive layer 52c (72c).

  In addition, when the first conductive layer 52a (72a) is formed, the alignment mark Ks or the window 90 is formed in the first conductive layer 52a (72a) by using an etching process utilizing a photolithography method, and the second conductive layer 52a (72a) is formed. When the conductive layer 52c (72c) is formed, the window 90 or the alignment mark Ks may be formed in the second conductive layer 52c (72c) by using an etching process using a photolithography method. In particular, in the first and second modified examples, the laminated structure 84 is formed while performing the etching process using the photolithography method. Therefore, the alignment mark Ks and the window 90 are also formed during the formation of the laminated structure 84. You may form in.

  In addition, the supplier of the first substrate P1 has a wiring pattern in the device region on the circuit board for electronic devices (for example, artwork such as the shape, arrangement, and dimensions of large patterns such as the ground bus line and the power bus line). In advance, the alignment mark Ks and the window 90 are formed in the first conductive layer 52a (72a) or the second conductive layer 52c (72c) by an etching process using a photolithography method. These wiring patterns may be formed. Furthermore, when the supplier of the first substrate P1 knows in advance the region where the semiconductor element (TFT) is formed along with the wiring pattern (or the region where no TFT is formed), the function is applied to the region where the TFT is formed. A semiconductor layer as the layer 52b (72b) may be selectively deposited, and an insulating layer as the functional layer 52b (72b) may be selectively deposited in a region where no TFT is formed. In this case, in order to make the entire thickness of the functional layer 52b (72b) as uniform as possible, the semiconductor layer and the insulating layer may be adjusted to have substantially the same thickness.

  (Modification 4) FIG. 17 is a diagram showing a configuration of a laminator apparatus 30a in Modification 4. In FIG. In the fourth modification, the same reference numerals are given to the same configurations as those in the first embodiment, and the description thereof is omitted. In the modified example 4, a guide roller GR6a having a larger radius than the guide roller GR6 is provided instead of the guide roller GR6. The laminator device 30a is provided with a die coater head DCH for applying a thermosetting adhesive that is cured by heat to the second substrate P2 wound around the guide roller GR6a. That is, in the modified example 4, the adhesive layer 54 (74) is formed by applying an adhesive to the second substrate P2 side instead of the first substrate P1 side. Therefore, the adhesive layer 54 (74) is not provided on the first substrate P1. The region on the second substrate P2 to which the thermosetting adhesive is applied by the die coater head DCH is supported by the circumferential surface of the guide roller GR6a. The die coater head DCH applies a thermosetting adhesive widely and uniformly to the second substrate P2. Thereby, the laminated structure 52 (72) formed on the first substrate P1 can be transferred to the second substrate P2 by the pressure heating roller 36.

  Specifically, the pressure heating roller 36 is configured so that the laminated structure 52 (72) is located on the second substrate P2 side and is in contact with the thermosetting adhesive applied on the second substrate P2. P1 and the second substrate P2 are in close contact with both sides and heated. Since the thermosetting adhesive is cured by this heating, the adhesive layer 54 (or 74) is formed, and the laminated structure 52 (72) and the second substrate P2 are firmly bonded to form the first substrate P1. The laminated structure 52 (72) thus transferred is transferred to the second substrate P2. The first substrate P1 and the second substrate P2 that have passed through the pressure heating roller 36 are separated from each other.

  (Modification 5) FIG. 18 is a diagram showing a configuration of a laminator apparatus 30b in Modification 5. In FIG. Note that in the fifth modification, the same reference numerals are given to the same configurations as those in the first embodiment, and description thereof is omitted. In the modified example 5, a pressure roller 36b that performs only pressure bonding without heating is provided instead of the pressure roller heating roller 36, and a guide roller GR6b having a larger radius than the guide roller GR6 is provided instead of the guide roller GR6. Yes. The pressure roller 36b includes a roller R and a drum DRS having a larger radius than the roller R. Therefore, the first substrate P1 and the second substrate P2 sandwiched and adhered between the roller R and the drum DRS are transported along the circumferential surface of the drum DRS while being overlapped with each other, and thereafter, the guide rollers GR7, Separated from each other by GR8. The first substrate P1 is guided to the collection roll 38 by the guide roller GR7, and the second substrate P2 is guided to the collection roll 40 by the guide roller GR8.

  The laminator device 30b is provided with a die coater head DCH1 that applies a UV curing adhesive that is cured by UV light to the second substrate P2 wound around the guide roller GR6b. That is, in the modified example 5, the adhesive layer 54 (74) is formed by applying an adhesive on the second substrate P2 side instead of the first substrate P1 side. Therefore, the adhesive layer 54 (74) is not provided on the first substrate P1. The region on the second substrate P2 to which the UV curable adhesive is applied by the die coater head DCH1 is supported by the circumferential surface of the guide roller GR6b. The die coater head DCH1 applies a UV curing adhesive widely and uniformly to the second substrate P2. Further, the laminator device 30b has an ultraviolet irradiation source 94 for irradiating the UV curable adhesive with UV (ultraviolet) light before the first substrate P1 and the second substrate P2 bonded by the pressure roller 36b are separated from each other. Is provided with a plurality of irradiation devices UVS. Thereby, the laminated structure 52 (72) formed on the first substrate P1 can be transferred to the second substrate P2 by the pressure roller 36b.

  Specifically, the roller R and the drum DRS of the pressure roller 36b are positioned so that the laminated structure 52 (72) is located on the second substrate P2 side and is in contact with the UV curable adhesive applied on the second substrate P2. In this manner, the first substrate P1 and the second substrate P2 are adhered to each other with both sides interposed therebetween. Thereafter, the irradiation device UVS irradiates the first substrate P1 and the second substrate P2 which are wound around the drum DRS and are transported while being superimposed on each other with UV light. Since the UV curable adhesive between the first substrate P1 and the second substrate P2 is cured by the irradiation of the UV light, an adhesive layer 54 (74) is formed, and the laminated structure 52 (72) and the second substrate are formed. P2 is firmly bonded. After the UV irradiation, the first substrate P1 and the second substrate P2 are separated from each other by the guide rollers GR7 and GR8. Thereby, the laminated structure 52 (72) formed on the first substrate P1 is transferred to the second substrate P2.

[Second Embodiment]
In the second embodiment, a specific method for manufacturing a pixel circuit of an organic EL display will be described. FIG. 19 is a diagram illustrating an example of a pixel circuit of one light emitting pixel of an active matrix organic EL display, and FIG. 20 is a diagram illustrating a specific structure of the pixel circuit illustrated in FIG. The pixel circuit includes a TFT, a capacitor C, and an organic light emitting diode (OLED). The source electrode S and drain electrode D of the TFT, the wiring L1 associated therewith, one electrode C1 of the capacitor C, and the pixel electrode E connected to the cathode of the OLED are formed in the first conductive layer 102 of the multilayer structure 100. Has been. The gate electrode G of the TFT, the wiring L2 associated therewith, and the other electrode C2 of the capacitor C are formed in the second conductive layer 104 of the multilayer structure 100. The electrode C2 of the capacitor C is connected to the ground GND (earth line). In addition, an electroless plating contactor M is provided at a location where it is necessary to connect the wiring L1 formed in the first conductive layer 102 and the wiring L2 formed in the second conductive layer 104. In FIG. 20, the first conductive layer 102 is indicated by hatching for convenience in order to distinguish the first conductive layer 102 and the second conductive layer 104.

  In the second embodiment, a method for manufacturing a pixel circuit having a top contact type TFT will be described. FIG. 21 and FIG. 22 are flowcharts showing an example of the steps of the pixel circuit manufacturing method.

First, after the steps S101 to S105, as shown in FIG. 23, the peeling layer 106, the first conductive layer 102, the semiconductor layer 108, the insulating layer 110, and the first layer P1 are sequentially formed from the surface side of the first substrate P1. Two conductive layers 104 are formed on the first substrate P1. Steps S101 to S105 are the same as steps S31 to S35 in FIG. Needless to say, the semiconductor layer 108 and the insulating layer 110 constitute a functional layer 112, and the first conductive layer 102, the functional layer 112 (the semiconductor layer 108 and the insulating layer 110), and the second conductive layer 104 are stacked. The structure 100 is configured. In the second embodiment, the first conductive layer 102 and the second conductive layer 104 are formed of Cu (copper), the semiconductor layer 108 is formed of ZnO which is a kind of oxide semiconductor, and the insulating layer 110 is formed. Is made of SiO ₂ .

  Then, as shown in FIGS. 24 and 25, a predetermined pattern (the pattern of the gate electrode G, the wiring L2, and the electrode C2 of the capacitor C described above) is formed on the second conductive layer 104 by etching using photolithography. ). In FIG. 24, only the gate electrode G and the wiring L2 are shown in the second conductive layer 104. In FIG. 25, the first conductive layer 102 is indicated by hatching in order to distinguish the first conductive layer 102 and the second conductive layer 104.

  The formation of a gate electrode and the like by etching using a photolithography method will be briefly described. First, a photoresist layer is formed on the second conductive layer 104 in step S106. In step S107, a predetermined pattern (pattern of the gate electrode G, the wiring L1, and the electrode C2) is exposed to the coated photoresist layer using ultraviolet rays, and development is performed in step S108. Thereby, a predetermined pattern is formed in the photoresist layer. Next, in step S109, the first substrate P1 is immersed in a ferric oxide corrosive solution, whereby an etching process is performed using the photoresist layer on which a predetermined pattern is formed as a mask. A gate electrode G and the like are formed on the substrate. In step S110, the photoresist layer is peeled off and the first substrate P1 is cleaned. Steps S106 to S110 are the same as steps S36 to S40 in FIG. The functional layer 112 is exposed in the region where the second conductive layer 104 is removed by this etching process.

  Thereafter, in step S111, the functional layer 112 is also etched (processed) as shown in FIG. 24 by immersing the first substrate P1 in a hydrogen fluoride corrosive solution. Since the functional layer 112 is exposed in the region where the second conductive layer 104 is removed by the etching process in step S109, the functional layer 112 in the region where the second conductive layer 104 is removed is subjected to the etching process in step S111. Removed by.

  Thereafter, in step S112, an adhesive layer 114 is formed by applying an adhesive to the surface side (second conductive layer 104 side) of the first substrate P1 on which the multilayer structure 100 is formed. Then, in step S113, the first substrate P1 and the second substrate P2 are temporarily brought into close contact or in close contact so that the second conductive layer 104 is located on the second substrate P2 side, as shown in FIG. The laminated structure 100 formed on the first substrate P1 is transferred to the second substrate P2. This transfer is transferred by the laminator device 30. Steps S112 and S113 are the same as steps S41 to S43 in FIG.

  Then, by etching using photolithography, as shown in FIGS. 27 and 28, the first conductive layer 102 has a predetermined pattern (the source electrode S and drain electrode D, the wiring L1, and the electrode C1 of the capacitor C described above). , And the pattern of the pixel electrode E). In FIG. 27, only the source electrode S, the drain electrode D, and the wiring L1 are illustrated in the first conductive layer 102. In FIG. 28, the first conductive layer 102 is indicated by hatching in order to distinguish the first conductive layer 102 and the second conductive layer 104.

  Briefly describing the formation of the source electrode and the like by etching using a photolithography method, a photoresist layer is formed on the surface side (first conductive layer 102 side) of the second substrate P2 in step S114 of FIG. In step S115, a predetermined pattern (a pattern of the source electrode S, the drain electrode D, the wiring L1, the electrode C1, and the pixel electrode E) is exposed to the formed photoresist layer using ultraviolet rays, and in step S116. Develop. Thereby, a predetermined pattern is formed in the photoresist layer. Next, in step S117, the second substrate P2 is immersed in a ferric oxide corrosive solution, and an etching process is performed using the photoresist layer on which a predetermined pattern is formed as a mask. A source electrode S, a drain electrode D, and the like are formed. At this time, an opening portion of the contact hole H for forming the electroless plating contactor M is also formed in the first conductive layer 102. In step S118, the photoresist layer on the first conductive layer 102 is peeled off, and the second substrate P2 is cleaned. Steps S114 to S118 are the same as steps S44 to S48 in FIG. 8 except that the contact hole H is formed.

  Then, as shown in FIG. 29, the functional layer 112 (semiconductor layer 108 and insulating layer 110) in the contact hole H portion is etched by an etching process using a photolithography method. That is, in step S119, a photoresist layer is formed on the surface side (first conductive layer 102 side) of the second substrate P2. In step S120, a predetermined pattern is exposed to the formed photoresist layer using ultraviolet rays, and development is performed in step S121. Thereby, a predetermined pattern is formed in the photoresist layer. Next, in step S122, the second substrate P2 is immersed in an etching solution of hydrogen fluoride, and an etching process is performed using the photoresist layer on which a predetermined pattern is formed as a mask. 112 is also etched. Thereby, the contact hole H is completed.

  Thereafter, in step S123, an electroless plating process is performed on the contact hole H, and as shown in FIG. 30, an electroless plating contactor M made of, for example, Cu, Cr, NiP or the like is formed, and the first conductive The layer 102 (wiring L1) and the second conductive layer 104 (wiring L2) are electrically connected. In step S124, the photoresist layer on the second substrate P2 is peeled off, and the second substrate P2 is cleaned. Through the steps as described above, a pixel circuit as shown in FIG. 20 can be manufactured.

  In the first embodiment (including modifications) and the second embodiment, the thin film is processed using an etching process using a photolithography method, but an optical patterning method is used. Any processing can be used. As the processing using the optical patterning method, in addition to the etching processing using the photolithography method, for example, in the state where the first substrate P1 on which the laminated structure 52 is formed is immersed in a special liquid, ultraviolet rays are used. A method of etching the resist layer coated on the second conductive layer 52c by irradiating the pattern light, and a second conductive material by irradiating the ultraviolet pattern light with a laser beam spot condensed at a high NA. There is an ablation method for directly removing (etching) the layer 52c.

  In the first embodiment (including modifications) and the second embodiment, the bottom gate type TFT is described as an example. However, a top gate type TFT may be used. In addition, the laminated structures 52 and 72 formed on the first substrate P1 (supporting substrate) are not limited to thin film transistors (TFTs), and are also useful for manufacturing electronic devices including thin film diodes (TFDs). Furthermore, in the configuration of the laminated structures 52, 72, etc., the functional layer 52b (72b) sandwiched between the upper and lower first conductive layers and the second conductive layer may be a thin film having two or more layers. For example, when the functional layer 52b (72b) is configured by stacking a first functional film and a second functional film, the first functional film corresponds to the entire device region on the first substrate P1. The second functional film may be formed uniformly in a region, and the second functional film may be selectively formed in a partial region on the first functional film.

By the way, in the said 1st Embodiment (a modification is also included), the said 2nd Embodiment, etc., among the surfaces of the 1st board | substrate P1 (supporting base materials, such as metal foil), the insulating layer of a laminated structure Alternatively, when the roughness of the surface on which the semiconductor layer is laminated is expressed by an arithmetic average roughness Ra value (nm) defined by JIS standards, the roughness Ra value is the value of the insulating layer (or semiconductor layer) to be laminated. It is determined in a range not exceeding the thickness. However, in order to ensure long-term stable operation as a TFT, the surface roughness Ra value of the first substrate P1 is preferably 200 nm or less (submicron or less), and more preferably in the range of 1 nm to several tens of nm. As the roughness Ra value is decreased, the characteristics of the TFT, such as electron mobility, on / off ratio, and leakage current, are improved. Although the roughness Ra value can be less than 1 nm, a practical roughness Ra value may be about several nm. Such roughness Ra value can be easily obtained by the current surface treatment (polishing) technique. Further, when the first conductive layer (52a, 72a, 84a, 102) of the laminated structure is formed on the surface of the first substrate P1, instead of flattening the surface of the first substrate P1 by a polishing process or the like. In addition, after a planarization film is formed on the surface of the first substrate P1, a peeling layer (50, 70, 80, 106) and a first conductive layer (52a, 72a, 84a, 102) are formed on the planarization film. You may form into a film in order. The flattening film is a material that fills the recesses on the surface of the first substrate P1 to alleviate the recesses and protrusions and has strong etching resistance, and does not denature even during heat treatment during transfer (laminate) or post-annealing, for example It is made of a silicon oxide (SiO ₂ ) -based wet material. As a material for such a flattened film, Sumise Fine (registered trademark) manufactured by Sumitomo Osaka Cement Co., Ltd., Vistrater (registered trademark) manufactured by Nippon Soda Co., Ltd., Colcoat (registered trademark) manufactured by Colcoat Co., Ltd. In addition, a flattening material SOG (Spin On Glass) sold by Honeywell or Hitachi Chemical Co., Ltd. can be used.

[Modifications of the above embodiments]
Each of the above embodiments (including each modification) can be further modified as follows.

[Modification 1]
FIG. 31 shows a schematic configuration of a film forming apparatus 10A for continuously forming a multilayer structure for an electronic device on the first substrate P1, similarly to the film forming apparatus 10 of FIG. A film forming apparatus 10A shown in FIG. 31 is disposed around the chamber 16, the vacuum pump 18, the film forming rotary drum 22, and the film forming rotary drum 22, and continuously deposits a plurality of film forming materials (thin film materials). A plurality of base materials 20A, 20B, 20C and guide rollers GR1 to GR3. As described in the previous embodiments and modifications, on the first substrate P1, a two-layer structure of a conductive layer (metal film, ITO film, etc.) and an insulating layer (dielectric film), or its A three-layer structure in which a semiconductor layer is formed on the two-layer structure is formed. Therefore, the base material 20A disposed around the film-forming rotary drum 22 is formed by forming a conductive layer by vapor deposition, sputtering, CVD, or the like, and the base material 20B is conductive by vapor deposition, sputtering, CVD, or the like. It is assumed that an insulating layer is formed on the layer, and the base material 20C is a semiconductor layer formed on the insulating layer by vapor deposition, sputtering, CVD, or the like. Note that when a two-layer structure of a conductive layer and an insulating layer is formed on the first substrate P1, film formation using the base material 20C may be avoided. Furthermore, depending on the structure of the TFT to be formed, the arrangement of the base material 20B and the base material 20C may be changed, and the conductive layer, the semiconductor layer, and the insulating layer may be formed in this order.

  As described above, the surface of the first substrate P1 wound up by the collection roll 14 is formed by sequentially arranging the respective film-forming portions of the plurality of thin-film material base materials 20A, 20B, and 20C around the film-forming rotary drum 22. Since a desired laminated structure is formed at once, it is not necessary to replace the collection roll 14 with another film forming apparatus, and productivity is improved. In this case, it is desirable to set the same temperature in the film forming unit using the base material 20A, the film forming unit using the base material 20B, and the film forming unit using the base material 20C. Further, the film forming apparatus 10A may incorporate a mist deposition method (mist CVD method) as disclosed in, for example, International Publication No. 2013/176222 pamphlet. In that case, the base material of the film forming material is contained in an ionic state or a nanoparticle state in the mist sprayed on the surface of the first substrate P1. Furthermore, when non-equilibrium atmospheric pressure plasma is generated in the space between the mist spray nozzle and the surface of the first substrate P1 using a high-pressure pulse power source, the temperature of the first substrate P1 is about 200 ° C. Therefore, good film formation by the mist CVD method is possible, and the film formation rate is improved.

[Modification 2]
FIG. 32 is a schematic diagram showing a modification of the transfer method according to FIGS. 9 and 10 described above, and the same members (layers, films, materials, etc.) as those in FIGS. 9 and 10 are denoted by the same reference numerals. It is. In the previous example of FIG. 9, after the peeling layer 70, the first conductive layer 72a, the semiconductor layer 72b1, the insulating layer 72b2, and the second conductive layer 72c are sequentially stacked on the first substrate P1, as shown in FIG. 9B. As shown in FIG. 9C, the second conductive layer 72c was etched to form a gate electrode. Similarly, a peeling layer 70, a first conductive layer 72a, a semiconductor layer 72b1, an insulating layer 72b2, and a second conductive layer 72c are stacked on the first substrate P1 shown in FIG. 72b1 is not formed uniformly on the first conductive layer 72a, but the semiconductor layer 72b1 is selectively formed in a local region corresponding to the channel portion (gap portion between the source electrode and the drain electrode) of the TFT. In this case, a photoresist layer is formed on the first conductive layer 72a, a resist layer opening is formed in a region where the semiconductor layer 72b1 is to be formed by photolithography, and vapor deposition, sputtering, CVD, or the like is performed in the opening. Thus, a semiconductor material may be deposited.

  Thereafter, in the modification of FIG. 32, an insulating layer 72b2 is formed so as to uniformly cover the first conductive layer 72a and the selectively formed semiconductor layer 72b1, and the second conductive layer is further formed on the insulating layer 72b2. A layer 72c is formed, and the second conductive layer 72c is processed so as to become a gate electrode (and a wiring connected thereto) by an etching process using a photolithography method, as in FIG. 9C. In this modification, the semiconductor layer 72b1 can be selectively formed by limiting to the TFT formation region, so that the amount of semiconductor material used can be suppressed. When the multilayer structure 72 formed on the first substrate P1 is transferred to the second substrate P2, the adhesive layer 74 is applied to the surface of the multilayer structure 72 of the first substrate P1 in FIG. 9D. In this modification, an adhesive layer 74 is formed on the second substrate P2 side as shown in FIG. The second substrate P2 in this modification has a structure in which a buffer layer P2b made of polyethylene (PE) or the like is laminated on the surface of a sheet substrate P2a such as PET or PEN, and a sealant layer (Silicon Sealant or the like) P2c on the surface of the buffer layer P2b. Then, an adhesive layer 74 is formed.

  As shown in FIG. 32, when the stacked structure 72 on the first substrate P1 side is formed of a selective semiconductor layer 72b1 or a gate electrode, the surface of the stacked structure 72 facing the second substrate P2 has irregularities. As a result, the adhesion with the second substrate P2 may be non-uniform during transfer. Therefore, a buffer layer P2b is provided to absorb such irregularities. The buffer layer P2b is preferably one having stability and plasticity, and a thermoplastic material such as polyethylene (PE) is preferable when thermocompression bonding is performed during transfer. Furthermore, in this modification, the adhesive layer 74 formed on the buffer layer P2b is a synthetic resin emulsion type adhesive EVA (Ethylene Vinyl Acetate) mainly composed of vinyl acetate resin and ethylene vinyl acetate copolymer resin. With such a configuration, the uneven structure 72 on the first substrate P1 side having unevenness is precisely transferred to the second substrate P2 side without being damaged such as cracks.

[Modification 3]
As shown in FIG. 32, when the adhesive layer 74 (EVA) is used, good transfer is possible. However, if the unevenness of the laminated structure 72 on the first substrate P1 side is relatively large, the adhesive layer 74 is used. Due to internal stress generated during the curing of (EVA), fine cracks may be generated in the adhesive layer 74 (EVA) after curing, particularly in the upper part or in the vicinity of the second conductive layer 72c of the laminated structure 72. Therefore, after forming the laminated structure 72 (first conductive layer 72a, semiconductor layer 72b1, insulating layer 72b2, second conductive layer 72c) on the first substrate P1 as shown in FIG. 32, as shown in FIG. A planarization film FP is formed so as to cover the entire stacked structure 72. The planarizing film FP fills the concave portion of the multilayer structure 72 to relieve the irregularity, has a strong etching resistance, and is a material that does not denature even during heat treatment during transfer (laminate) or post-annealing, for example, It is made of a silicon oxide (SiO ₂ ) -based wet material. As materials for such a flattening film FP, Sumise Fine (registered trademark) manufactured by Sumitomo Osaka Cement Co., Ltd., Vistraiter (registered trademark) manufactured by Nippon Soda Co., Ltd., Colcoat (registered trademark) manufactured by Colcoat Co., Ltd. ), Flattening material SOG (Spin On Glass) sold by Honeywell or Hitachi Chemical Co., Ltd. can be used. Then, after the material of the flattening film FP is completely dried or in the middle of drying, the laminated structure 72 with the flattening film FP is pressure-transferred to the adhesive layer 74 (EVA) on the second substrate P2.

  The planarizing film FP is an inorganic insulating film (or organic insulating film), and cracks due to internal stress at the time of curing of the adhesive layer 74 (EVA) by directly bonding to the adhesive layer 74 (EVA) to be laminated. Has the effect of reducing the occurrence. In FIG. 33, after the laminated structure 72 is formed on the first substrate P1, the wet material of the planarization film FP is applied thereon, but as shown in FIG. 32, the second substrate P2 is used. After the adhesive layer 74 (EVA) is formed thereon, the planarizing film FP is formed on the adhesive layer 74 (EVA), and before the planarizing film FP is dried, the laminated structure on the first substrate P1 The body 72 may be transferred to the planarizing film FP while being heated. 32 and 33, the laminated structure 72 formed on the first substrate P1 has the first conductive layer 72a on the first substrate P1 side as a source electrode / drain electrode of the TFT and a wiring connected thereto. Thus, the second conductive layer 72c on the second substrate P2 side has been described as the gate electrode of the TFT and the wiring connected thereto, but the reverse is also possible. That is, the first conductive layer 72a may be a TFT gate electrode and a wiring connected thereto, and the second conductive layer 72c may be a TFT source / drain electrode and a wiring connected thereto.

[Third Embodiment]
FIGS. 34 to 36 are views showing a manufacturing process of an electronic device (TFT) in which a part of the manufacturing method according to the embodiment of FIGS. 23 to 30 is improved. Accordingly, the members (materials) shown in FIGS. 34 to 36 that are the same as the members (materials) in FIGS. 23 to 30 are denoted by the same reference numerals as those in FIGS. 23 to 30. In the present embodiment, as shown in FIG. 34A, the first substrate P1 is a copper (Cu) sheet foil plate having a thickness of about several tens of μm to several hundreds of μm, and copper ( A Cu) first conductive layer 102 is laminated on the entire surface. The first conductive layer 102 is formed by laminating a copper foil rolled to a thickness of several tens of μm or less on the release layer 106. The first conductive layer 102 after the lamination is lapped so that the arithmetic mean roughness Ra value of the surface is about several nm to several tens nm while reducing the thickness.

Next, as shown in FIG. 34B, an insulating layer 110 that functions as a gate insulating film of the TFT is formed on the first conductive layer 102 of the first substrate P1. The insulating layer 110 is a typical silicon oxide film (SiO ₂ ), and is formed on the entire surface of the first conductive layer 102, and then a method of removing the silicon oxide film other than the TFT formation region by etching or the like, or selection By a typical film formation, a silicon oxide film is deposited only on the TFT formation region from the beginning. Since both the first substrate P1 and the first conductive layer 102 are made of copper (Cu) having high heat resistance, they can be formed at a high temperature in a vacuum, and the flatness (roughness Ra) of the silicon oxide film is improved. be able to.

Next, as shown in FIG. 34C, the semiconductor layer 108 is formed on the insulating layer 110 (SiO ₂ ). Here, the semiconductor layer 108 is an IGZO (oxide semiconductor) composed of indium, gallium, zinc, and oxygen. The semiconductor layer 108 made of IGZO has indium, gallium, zinc and oxygen as constituent elements, and has a predetermined atomic ratio of indium to the total amount of indium and gallium and a specific atomic ratio of zinc to the total amount of indium, gallium and zinc. The film is formed by a sputtering apparatus using an oxide sintered body having a ratio of 1 to 5 as a sputtering target. Prior to the sputtering process, a window corresponding to the formation region of the semiconductor layer 108 is opened in the resist layer formed on the entire surface of the first substrate P1 by a photolithography process (pattern exposure and resist development). After the IGZO semiconductor is sputtered by the sputtering apparatus, a step of peeling the resist layer is also performed. As a result, an IGZO semiconductor layer 108 is selectively formed on the insulating layer 110 as shown in FIG. 34C.

  Next, as shown in FIG. 34D, the source electrode 104 (S) and the drain electrode 104 (D) as the second conductive layer 104 are formed with a certain gap so as to form a channel portion on the semiconductor layer 108. It is formed so as to face each other. Again, a photolithography step is used to form a resist layer window in a region where the source electrode 104 (S) and the drain electrode 104 (D) are formed, and the metallic source electrode 104 (S) is formed in the window. And the drain electrode 104 (D) are deposited by vapor deposition or the like. The source electrode 104 (S) and the drain electrode 104 (D) are preferably made of gold (Au) having a high work function in order to be bonded to the semiconductor layer 108, but other metal materials (aluminum, copper) or silver A conductive ink material containing nanoparticles or metallic carbon nanotubes may be used. Here, the source electrode 104 (S) and the drain electrode 104 (D) are formed so as to extend from the channel portion to the first conductive layer 102 outside the region of the insulating layer 110 as shown in FIG. 34D. 104 (S) and the drain electrode 104 (D) are in electrical conduction with the first conductive layer 102 (ohmic coupling). Through the above steps, the laminated structure 100 (the first conductive layer 102, the insulating layer 110, the semiconductor layer 108, and the second conductive layer 104) is formed on the first substrate P1.

  FIG. 35 is a diagram showing a planar arrangement configuration of the laminated structure 100 formed on the first substrate P1. As electrical characteristics of TFT, it is desired that both electron mobility and on / off ratio are high and leakage current is sufficiently small. In the present embodiment, the surface of the first conductive layer 102 serving as the base of the TFT is a smooth surface having a sufficiently small arithmetic average roughness Ra value. Therefore, the insulating layer 110 and the semiconductor layer 108 formed thereon are also formed as a flat film having a uniform thickness, and the flatness of the contact interface between the semiconductor layer 108 and the second conductive layer 104 (source electrode and drain electrode). Well maintained. As a result, good characteristics can be obtained in terms of electron mobility, on / off ratio, and leakage current. In addition, since the gap between the source electrode 104 (S) and the drain electrode 104 (D) in the channel portion can be reduced to about several μm, a high-performance TFT utilizing the characteristics of the IGZO semiconductor can be obtained. As shown in FIG. 35, when the insulating layer 110, the semiconductor layer 108, and the second conductive layer 104 (source electrode and drain electrode) are stacked, relative stacking on the order of microns is required. Therefore, in the photolithography process, an alignment mark formed at a specific position on the first substrate P1 (particularly the first conductive layer 102) is detected by the alignment sensor in the exposure apparatus, and the alignment for adjusting the pattern exposure position. Action is required.

  FIG. 36 is a diagram illustrating a state in which the laminated structure 100 illustrated in FIGS. 34 and 35 is transferred to the second substrate P2 and further processed. FIG. 36A shows a state immediately after the laminated structure 100 on the first substrate P1 is transferred to the second substrate P2 by the transfer (laminating) step. Also in the present embodiment, before the transfer, as described with reference to FIG. 33, the planarization film FP that covers the entire surface of the stacked structure 100 of the first substrate P1 is formed on the first substrate P1, As described above with reference to FIG. 32, a second substrate P2 is prepared in which a buffer layer P2b made of polyethylene resin is formed with a predetermined thickness on the surface of a sheet substrate P2a made of PET. The adhesive layer (EVA) 114 is formed with a predetermined thickness. At the time of transfer, the adhesive layer (EVA) 114 is cured by heating while the flattening film FP on the first substrate P1 and the adhesive layer (EVA) 114 on the second substrate P2 are pressure-bonded with a predetermined pressure. The laminated structure 100 is peeled from one substrate P1. As a result, as shown in FIG. 36A, the laminated structure 100 is bonded onto the second substrate P2 with the first conductive layer (Cu) 102 exposed on the top surface.

  In the state immediately after the transfer shown in FIG. 36A, a residue of the release layer 106 may be attached to the surface of the first conductive layer 102. In that case, the surface of the first conductive layer 102 may be cleaned or polished. In particular, when the thickness of the first conductive layer 102 is about several tens of μm, the subsequent processing (particularly etching) of the first conductive layer 102 may take time. The thickness of one conductive layer 102 is preferably about several μm. In this embodiment, since the buffer layer P2b, the adhesive layer 114 made of EVA, and the planarization film FP are provided, the internal TFT may be damaged (cracked or disconnected) by the external force during polishing of the surface of the first conductive layer 102. ) Is suppressed. In addition, among the alignment marks used in the photolithography process when manufacturing the TFT laminated structure 100 on the first substrate P1, the alignment marks formed at each of the plurality of positions of the first conductive layer 102 are fine through-holes. In the case of a 20 μm diameter circle or a 20 μm square rectangle, for example, the first conductive layer 102 is the uppermost surface as shown in FIG. 36A, so that the alignment mark can be easily detected by the alignment sensor of the exposure apparatus. . Therefore, when the first conductive layer 102 is processed in the photolithography process, the positions of the TFTs below the first conductive layer 102, particularly the positions of the source electrode 104 (S) and the drain electrode 104 (D) Can be accurately identified with reference to the position of.

  Therefore, a resist layer is applied to the surface of the first conductive layer 102 in FIG. 36A, and pattern light corresponding to the shape of the TFT gate electrode, source electrode, drain electrode, and wiring connected to these electrodes is resist-resisted by an exposure apparatus. Expose the layer. At this time, the projection position of the pattern light is precisely set by detecting the alignment mark formed on the first conductive layer 102 by the alignment sensor of the exposure apparatus. As shown in FIG. 36B, the resist layer after the exposure process and the first conductive layer 102 (Cu) are etched to form the gate electrode 102G, the source electrode 102S, the drain electrode 102D (and the electrodes) by the first conductive layer 102, as shown in FIG. Is formed). At that time, the etched source electrode 102S is bonded to the source electrode 104 (S) directly bonded to the semiconductor layer 108, and the drain electrode 102D is bonded to the drain electrode 104 (D) directly bonded to the semiconductor layer 108. Alignment and patterning are performed so as to achieve the above state. Further, the etched gate electrode 102G is patterned so as to cover the channel portion (cap portion of the source electrode 104 (S) and the drain electrode 104 (D)) shown in FIG.

  FIG. 37 is a diagram showing an example of a planar arrangement configuration of the TFT of FIG. 36B, and a cross section taken along arrow 36B-36B ′ in FIG. 37 is FIG. 36B. The unnecessary portion of the first conductive layer 102 is removed by the etching process, but the insulating planarizing film FP is exposed in the removed portion. When further functional elements (resistors, capacitors, light emitting elements, light receiving elements, ICs, etc.) are formed on the second substrate P2 for the manufacture of electronic devices, wiring portions formed by the first conductive layer 102, etc. In addition, these functional elements can be soldered. When the first conductive layer 102 is copper (Cu), an insulating and heat resistant film that prevents corrosion due to oxidation may be selectively or entirely formed.

  As described above, in the present embodiment, the arithmetic mean roughness Ra value of the first conductive layer 102 of the multilayer structure 100 formed on the first substrate P1 is sufficiently reduced, and a vacuum process or a high temperature process can be used. Since the first substrate P1 is a metal foil (copper foil), a high-performance TFT can be formed. Therefore, the performance of the electronic device (display panel, touch panel, sheet sensor, etc.) finally manufactured on the flexible second substrate P2 is greatly improved. In the present embodiment, the second conductive layer 104 of the stacked structure 100 formed on the first substrate P1 is processed so as to be a source electrode and a drain electrode of the TFT. Processing may be performed so that the layer 104 serves as a gate electrode. In that case, in the manufacturing process of the TFT (laminated structure 100) shown in FIG. 34, the order of the insulating layer 110 and the semiconductor layer 108 stacked on the first conductive layer 102 may be reversed. That is, first, the semiconductor layer 108 is formed in a predetermined region on the first conductive layer 102, and the insulating layer 110 is formed on the insulating layer 110 so as to completely cover the semiconductor layer 108. The gate electrode formed by the second conductive layer 104 may be formed so as to be partially coupled to the first conductive layer 102.

  In the above-described embodiment, the first substrate P1 is a copper (Cu) sheet foil plate, and the first conductive layer 102 of the multilayer structure 100 is formed on the surface of the first substrate P1 with the release layer 106 interposed therebetween. However, the copper (Cu) sheet foil plate itself of the first substrate P <b> 1 can be used as the first conductive layer 102 of the laminated structure 100. In that case, the 1st board | substrate P1 is good to make the metal foil (copper foil) by rolling that the arithmetic mean roughness Ra value of the surface becomes small enough, and also wraps the surface as needed.

  When the first conductive layer 102 is used as the first substrate P1, the first substrate P1 itself becomes the first conductive layer 102 (electrode, wiring) and is transferred to the second substrate P2 side. It is desirable to perform a polishing process to reduce the thickness of the first substrate P1 (first conductive layer 102) immediately after the process. As described above, when the first substrate P1 itself is used as the first conductive layer 102, the entire stacked structure (conductive layer, insulating layer, semiconductor layer) including the first substrate P1 is used as the second substrate. As a result, the first substrate P1 is also transferred to the second substrate P2.

  Further, in the above embodiment mode, a structure in which two layers of the insulating layer 110 and the semiconductor layer 108 are sandwiched between the first conductive layer 102 (or the first substrate P1 itself) and the second conductive layer 104 is a laminated structure. However, as shown in FIG. 5, a structure in which only the insulating layer (or only the semiconductor layer) is sandwiched between the first conductive layer 102 (or the first substrate P1 itself) and the second conductive layer 104 is used. It is good also as a laminated structure.

  As described above, when the first substrate P1 itself is configured as a part of the multilayer structure, the first substrate on which at least a part of the multilayer structure constituting the electronic device is formed is transferred to the second substrate. In the device manufacturing method, a first substrate is prepared as a first conductive layer made of a conductive material, a functional layer made of at least one of an insulating material and a semiconductor is formed on the first conductive layer, and the functional layer By forming a second conductive layer on the conductive material on the first step, a first step of forming a laminated structure, and the first substrate and the second substrate so that the second conductive layer is located on the second substrate side. A second step of transferring the laminated structure including the first substrate to the second substrate by temporarily bringing the substrate close to or in close contact with the substrate is performed.

  Further, when the first substrate P1 itself is configured as a part of the laminated structure, the transfer substrate for transferring at least a part of the laminated structure constituting the electronic device to the transfer target substrate is made of a conductive material. A conductive foil functioning as one conductive layer (for example, a metal foil), a functional layer formed on the first conductive layer by at least one of insulating and semiconductor materials, and formed on the functional layer by a conductive material The second conductive layer is provided. In this case, the entire transfer substrate is transferred (bonded) to the transfer substrate.

  Furthermore, in the embodiment of FIG. 34 described above, a copper foil is laminated as the first conductive layer 102 on the first substrate P1 via the peeling layer 106. In addition, aluminum (Al), zinc (Zn), molybdenum (Mo), nickel (Ni), tantalum (Ta), tin (Sn), stainless steel (SUS), etc., or a foil made of an alloy thereof, or a foil obtained by plating gold (Au) or the like on the foil. The first conductive layer 102 may be laminated. These metal foils are produced as rolled foils and electrolytic foils (electroplated foils). In order to increase the adhesion during lamination, the back surface facing the first substrate P1 has a certain degree of roughness (for example, arithmetic). Average roughness Ra value of about 200 nm) is required. On the other hand, the surface on which the functional layer (insulating layer, semiconductor layer, etc.) of the metal foil is formed needs to be a smooth surface having a roughness Ra value of about several nanometers to several tens of nanometers. Therefore, when the first conductive layer 102 is a metal foil, the roughness Ra value is intentionally different between the front surface and the back surface of the metal foil, and the surface having the large roughness Ra value is the first substrate P1 side. A surface with a small Ra value may be a surface on which a laminated structure is formed.

Claims (7)

A device manufacturing method of transferring at least a part of a laminated structure of a thin film transistor constituting an electronic device on a first substrate and then transferring the laminated structure onto a second substrate,
A first conductive layer made of a conductive material is uniformly formed on the first substrate, and a functional layer made of at least one of an insulating material and a semiconductor is formed on the first conductive layer, and then an optical patterning method is used. Through the processing using the first conductive layer, any one of the source electrode, the drain electrode, and the gate electrode of the thin film transistor is formed in the second conductive layer made of a conductive material formed on the functional layer. A first step of forming the stacked structure by a layer, the functional layer, and the second conductive layer;
The first substrate and the second substrate are temporarily brought close to or in close contact with each other so that the second conductive layer is located on the second substrate side, and the stacked structure is transferred to the second substrate. Two steps;
The source electrode, the drain electrode, and the gate electrode of the thin film transistor are processed by using a photo-patterning method on the first conductive layer that is the surface of the stacked structure transferred to the second substrate. And an additional processing step to form any other of
A device manufacturing method. The device manufacturing method according to claim 1,
Between the first step and the second step, or after the second step, the second conductive layer or the first conductive layer is processed using a photopatterning method. A device manufacturing method further comprising a third step of forming an alignment mark for detecting the position of the second substrate. The device manufacturing method according to claim 1,
The device manufacturing method, wherein the functional layer includes a single insulating layer or a stacked layer of a semiconductor layer and an insulating layer. The device manufacturing method according to claim 1,
The thin film transistor is a bottom contact type,
In the first step, the functional layer is an insulating layer made of the insulating material, the second conductive layer is the gate electrode of the thin film transistor,
In the additional processing step, after the first conductive layer is processed as the source electrode and the drain electrode of the thin film transistor, a step of forming a semiconductor layer made of the semiconductor material between the source electrode and the drain electrode. A device manufacturing method. The device manufacturing method according to claim 1,
The thin film transistor is a top contact type,
In the first step, the functional layer includes a semiconductor layer deposited on the first conductive layer by the semiconductor material and an insulating layer deposited on the semiconductor layer by an insulating material. A device manufacturing method comprising lamination. A device manufacturing method according to any one of claims 1 to 5 ,
In the first step, the first conductive layer and the second conductive layer are metal materials,
A device manufacturing method, wherein any or all of the first conductive layer, the functional layer, and the second conductive layer are formed by any one of vapor deposition, sputtering, and CVD. It is a device manufacturing method of any one of Claims 1-6 , Comprising:
The first step includes a step of forming a release layer made of a material soluble in a solvent on the surface of the first substrate,
The device manufacturing method, wherein the first conductive layer is formed on the release layer.

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