CN111128707B - Method for manufacturing element and transfer substrate - Google Patents

Method for manufacturing element and transfer substrate Download PDF

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Publication number
CN111128707B
CN111128707B CN201911389514.XA CN201911389514A CN111128707B CN 111128707 B CN111128707 B CN 111128707B CN 201911389514 A CN201911389514 A CN 201911389514A CN 111128707 B CN111128707 B CN 111128707B
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substrate
layer
conductive layer
conductive
laminated structure
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CN111128707A (en
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奈良圭
中积诚
西康孝
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Nikon Corp
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Nikon Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0275—Photolithographic processes using lasers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/10—Apparatus or processes specially adapted to the manufacture of electroluminescent light sources
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)
  • Electroluminescent Light Sources (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Liquid Crystal (AREA)
  • Preparation Of Compounds By Using Micro-Organisms (AREA)

Abstract

The burden of the electronic device manufacturer can be reduced, and high-precision electronic devices can be manufactured. A device manufacturing method for forming at least a part of a laminated structure constituting an electronic device on a 1 st substrate which is a transfer substrate, and transferring the laminated structure (52) onto a 2 nd substrate (P2), the device manufacturing method comprising: step 1, forming a laminated structure (52) by forming a 1 st conductive layer (52 a) on a 1 st substrate (P1), forming a functional layer (52 b) on the 1 st conductive layer (52 a), and forming a 2 nd conductive layer (52 c) on the functional layer (52 b); and a step 2 in which the 1 st substrate (P1) and the 2 nd substrate (P2) are temporarily brought into close contact with each other so that the 2 nd conductive layer (52 c) is located on the 2 nd substrate (P2) side, and the laminate structure (52) is transferred to the 2 nd substrate (P2).

Description

Method for manufacturing element and transfer substrate
The present application is a divisional application of patent application having application date 2015, 8, 24, application number 2015180045821. X and entitled "device manufacturing method and transfer substrate".
Technical Field
The present invention relates to a transfer substrate on which a laminate structure constituting at least a part of an electronic device is formed, and a device manufacturing method for manufacturing an electronic device by transferring the laminate structure formed on the transfer substrate to a substrate to be transferred.
Background
Japanese patent application laid-open No. 2006-302814 discloses a method for forming an organic EL layer. Briefly described, first, a hole transport layer is formed on the 1 st endless belt by a coating method (a spraying method or the like), a light-emitting layer is formed on the 2 nd endless belt by a coating method (a spraying method or the like), and an electron transport layer is formed on the 3 rd endless belt by a coating method (a spraying method or the like). Then, after the hole transport layer formed on the 1 st endless belt is transferred on the sheet-like substrate supplied from the supply roll, the light emitting layer formed on the 2 nd endless belt is transferred onto the hole transport layer, and then the electron transport layer formed on the 3 rd endless belt is transferred onto the light emitting layer, thereby forming the organic EL layer.
Disclosure of Invention
However, for example, in the case of manufacturing an electronic device including a semiconductor device such as a thin film transistor, it is preferable to form a film in a vacuum space where the film thickness is easily controlled in order to improve the performance and yield of the semiconductor device or to stabilize the characteristics, and it is difficult to manufacture a high-precision electronic device by a transfer method using a technique described in japanese patent application laid-open No. 2006-302814.
On the other hand, although a method of manufacturing an electronic device on a glass substrate and transferring the completed electronic device from the glass substrate to another final substrate (for example, a flexible resin film or a plastic plate) is generally performed, in this case, a manufacturer of the electronic device forms a layer constituting the electronic device on the glass substrate by forming a film in a vacuum space, or repeatedly performs a developing process, an etching process, a CVD process, a sputtering process, or the like using photolithography depending on a laminated structure of the electronic device to form the electronic device, and then transfers the completed electronic device to the final substrate. Therefore, manufacturers of electronic components have to expend not only the manufacturing cost of manufacturing finished electronic components on a glass substrate using equipment for performing a plurality of film formation manufacturing processes for forming a layer structure of electronic components on a glass substrate, but also the manufacturing cost (equipment) of transferring (transferring) electronic components on a glass substrate to a final substrate. However, it is difficult to reduce the product price of the final electronic device (such as LCD display panel or organic EL display panel) and the touch panel, and the burden on the manufacturer of the electronic device is high.
In accordance with aspect 1 of the present invention, there is provided a method for manufacturing an element, including forming at least a part of a laminated structure constituting an electronic element on a 1 st substrate, transferring the laminated structure onto a 2 nd substrate, comprising: step 1, forming a functional layer formed of at least one material of an insulating property and a semiconductor on the 1 st conductive layer by forming the 1 st conductive layer formed of a conductive material on the 1 st substrate, and forming a 2 nd conductive layer formed of a conductive material on the functional layer to form the laminated structure; and a step 2 of temporarily bringing the 1 st substrate into close proximity with or close contact with the 2 nd substrate so that the 2 nd conductive layer is located on the 2 nd substrate side, thereby transferring the laminate structure to the 2 nd substrate.
In the 2 nd aspect of the present invention, a transfer substrate is a laminate structure for transferring at least a part of a constituent electronic element onto a transfer substrate: the laminated structure is formed on the surface of the transfer substrate, and is composed of a 1 st conductive layer formed on the transfer substrate using a conductive material, a functional layer formed on the 1 st conductive layer using at least one of an insulating material and a semiconductor material, and a 2 nd conductive layer formed on the functional layer using a conductive material.
In a 3 rd aspect of the present invention, a transfer substrate is a transfer substrate for transferring at least a part of a laminate structure constituting an electronic device including a semiconductor device onto a product substrate on which the electronic device is formed, the laminate structure being supported: the laminated structure is a sequential lamination of a 1 st conductive layer formed from the front surface side of the transfer substrate in the same or selective manner using a conductive material, a functional layer formed in the same or selective manner using an insulating material or a material exhibiting semiconductor characteristics, and a 2 nd conductive layer formed in the same or selective manner using a conductive material.
In accordance with a 4 th aspect of the present invention, there is provided a device manufacturing method for transferring a 1 st substrate on which at least a part of a laminate structure constituting an electronic device is formed, to a 2 nd substrate, the method comprising: step 1, preparing the 1 st substrate as a 1 st conductive layer formed of a conductive material, forming a functional layer formed of at least one of an insulating material and a semiconductor material on the 1 st conductive layer, and forming a 2 nd conductive layer formed of a conductive material on the functional layer to form the laminated structure; and a step 2 of temporarily bringing the 1 st substrate into close proximity with or close contact with the 2 nd substrate so that the 2 nd conductive layer is located on the 2 nd substrate side, thereby transferring the laminated structure including the 1 st substrate to the 2 nd substrate.
In accordance with a 5 th aspect of the present invention, there is provided a transfer substrate for transferring at least a part of a laminate structure constituting an electronic device on a transferred substrate, the transfer substrate comprising: a conductive foil that uses a conductive material to function as the 1 st conductive layer; a functional layer formed on the 1 st conductive layer using at least one material of insulation and semiconductor; and a 2 nd conductive layer formed on the functional layer using a conductive material.
Drawings
FIG. 1 is a view showing the structure of a thin film forming apparatus for forming a thin film on a substrate according to embodiment 1.
Fig. 2 is a diagram showing the structure of the lamination device according to embodiment 1 for transferring the laminate structure formed on the 1 st substrate to the 2 nd substrate.
Fig. 3 is a flowchart showing an example of steps of a bottom contact TFT manufacturing method.
Fig. 4 is a flowchart showing an example of steps of a bottom contact TFT manufacturing method.
Fig. 5A to 5F are cross-sectional views showing a TFT manufacturing-passing state manufactured by the steps shown in fig. 3 and 4.
Fig. 6A to 6D are cross-sectional views showing a TFT manufacturing-passing state manufactured by the steps shown in fig. 3 and 4.
Fig. 7 is a flowchart showing an example of steps of the method for manufacturing the top contact TFT.
Fig. 8 is a flowchart showing an example of steps of the method for manufacturing the top contact TFT.
Fig. 9A to 9D are cross-sectional views showing a TFT manufacturing-passing state manufactured by the steps shown in fig. 7 and 8.
Fig. 10A to 10C are cross-sectional views showing a TFT manufacturing-passing state manufactured by the steps shown in fig. 7 and 8.
Fig. 11 is a flowchart showing an example of the steps of the method for manufacturing a top contact TFT according to modification 1 of embodiment 1.
Fig. 12 is a flowchart showing an example of the steps of the method for manufacturing a top contact TFT according to modification 1 of embodiment 1.
Fig. 13A to 13F are cross-sectional views showing a TFT manufacturing-passing state manufactured by the steps shown in fig. 11 and 12.
Fig. 14A to 14F are cross-sectional views showing a TFT manufacturing-passing state manufactured by the steps shown in fig. 11 and 12.
Fig. 15 is a cross-sectional view showing modification 3 of embodiment 1 when an alignment mark is formed on the 2 nd conductive layer.
Fig. 16 is a cross-sectional view showing modification 3 of embodiment 1 when a window is formed in the 1 st conductive layer.
Fig. 17 is a diagram showing the structure of a lamination device in modification 4 of embodiment 1.
Fig. 18 is a diagram showing the structure of a lamination device in modification 5 of embodiment 1.
Fig. 19 is a diagram showing an example of a pixel circuit of the organic EL display according to embodiment 2.
Fig. 20 is a diagram showing a specific configuration of the pixel circuit shown in fig. 19.
Fig. 21 is a flowchart showing an example of steps of the method for manufacturing the pixel circuit shown in fig. 20.
Fig. 22 is a flowchart showing an example of steps of the method for manufacturing the pixel circuit shown in fig. 20.
Fig. 23 is a cross-sectional view of the laminated structure formed on the 1 st substrate at the steps S101 to S105 in fig. 21.
Fig. 24 is a cross-sectional view of the laminated structure in which the 2 nd conductive layer is processed in the steps S106 to S111 in fig. 21.
Fig. 25 is a plan view of the laminated structure shown in fig. 24.
Fig. 26 is a cross-sectional view of the laminated structure formed on the 1 st substrate in step S113 of fig. 21 transferred to the 2 nd substrate.
Fig. 27 is a cross-sectional view of the laminated structure in which the 1 st conductive layer is processed in the steps S114 to S118 in fig. 22.
Fig. 28 is a plan view of the laminated structure shown in fig. 27.
Fig. 29 is a cross-sectional view of the functional layer of the contact hole portion shown in fig. 27 etched in the steps S119 to S122 of fig. 22.
Fig. 30 is a cross-sectional view of the contact hole portion shown in fig. 29, in which an electroless contact is formed in step S123 of fig. 22.
Fig. 31 is a diagram showing a modification of the film forming apparatus shown in fig. 1.
Fig. 32 is a diagram showing another configuration example of a laminated structure of a top contact TFT and a transfer example of the laminated structure.
Fig. 33 is a diagram showing a state in which a planarization film is used at the time of transfer shown in fig. 32.
Fig. 34A to 34D are views showing a process for manufacturing a laminated structure when the laminated structure of the electronic device shown in fig. 23 to 30 is modified.
Fig. 35 is a view showing a top view arrangement configuration of the laminated structure shown in fig. 34D formed on the 1 st substrate.
Fig. 36A is a diagram showing a pattern immediately after the laminated structure shown in fig. 34D formed on the 1 st substrate is transferred to the 2 nd substrate in a transfer step, and fig. 36B is a diagram showing a pattern in which a gate electrode, a drain electrode, and the like are formed in the 1 st conductive layer shown in fig. 36A.
Fig. 37 is a diagram showing an example of a planar arrangement structure of the TFT of fig. 36B.
Symbol description:
10. film forming apparatus
12. Supply reel
14. Recovery reel
16. Treatment chamber
18. Vacuum pump
20. Substrate material
22. Rotary cylinder for film formation
30. Lamination device
32. 34 supply spool
36 crimping heating roller
38. 40 recovery reel
GR1, GR2, GR3, GR5, GR6 guide roller
50. Stripping layer
52. Laminated structure
52a 1 st conductive layer
52b functional layer
52c No. 2 conductive layer
54. Adhesive layer
56. Gold alloy
58. Semiconductor layer
P1 st substrate
P2 nd substrate
Detailed Description
In the device manufacturing method and the transfer substrate according to the aspects of the present invention, preferred embodiments are disclosed, and the detailed description is given below with reference to the accompanying drawings. The aspects of the present invention are not limited to these embodiments, and various modifications and improvements are also included.
[ embodiment 1 ]
Fig. 1 is a diagram showing a configuration of a film forming apparatus 10 for forming a thin film on a substrate (hereinafter referred to as a 1 st substrate) P1. The 1 st substrate P1 is a Flexible (Flexible) sheet-like substrate (sheet-like substrate), and the film forming apparatus 10 has a structure in which the 1 st substrate P1 supplied from a supply roll 12 for winding the 1 st substrate (transfer substrate, support substrate) P1 into a roll form is fed, the fed 1 st substrate P1 is subjected to a film forming process, and then wound up by a recovery roll 14, that is, a so-called roll-to-roll system. The 1 st substrate P1 has a strip shape in which the movement direction of the 1 st substrate P1 is the long side direction (long strip) and the width direction is the short side direction (short side). The film forming apparatus 10 further includes: the film forming apparatus includes a processing chamber 16, a vacuum pump 18 that sucks air in the processing chamber 16 and vacuums the processing chamber 16, a substrate 20 as a film forming material (film raw material), guide rolls GR1 to GR3, and a film forming rotary cylinder 22.
Motors, not shown, are provided on the supply reel 12 and the recovery reel 14, and the 1 st substrate P1 is carried out from the supply reel 12 by the rotation of the motors, and the 1 st substrate P1 carried out is wound up by the recovery reel 14. The film forming rotary cylinder 22 is a portion that conveys the 1 st substrate P1 while rotating and performs film formation while being supported on the circumferential surface. Thus, the 1 st substrate P1 is conveyed toward the recovery roll 14 along the outer peripheral surface (circumferential surface) of the film formation rotary cylinder 22. The guide rollers GR1 to GR3 guide the path of the 1 st substrate P1 to be conveyed. A motor, not shown, is provided to the film formation rotary cylinder 22, and the film formation rotary cylinder 22 is rotated by the motor.
The film forming apparatus 10 forms a thin film (layer) on the 1 st substrate P1 by vapor deposition or sputtering. In the case of forming a film by vapor deposition, the substrate 20 is heated by resistance heating, electron beam, high frequency induction, laser, or the like, and the vaporized or sublimated film forming material is adhered to the 1 st substrate P1 to form a thin film. In the case of forming a film by sputtering, the ionized argon gas is made to collide with the substrate 20 to dissociate molecules of the substrate 20, and the dissociated molecules are attached to the 1 st substrate P1 to form a thin film. Thus, the 1 st substrate P1 having the film (layer) formed on the surface thereof is wound around the recovery reel 14. The film forming apparatus 10 may form a thin film by CVD (Chemical Vapor Deposition). Further, as the film forming apparatus 10, for example, an apparatus using an aerosol deposition method (aerosol CVD method) disclosed in the specification of international publication No. 2013/17682 may be used.
The film forming apparatus 10 can be used to continuously laminate a plurality of thin films on the 1 st substrate P1. That is, the recovery roll 14 wound around the 1 st substrate P1 having the 1 st layer formed on the surface thereof is used as the supply roll 12 of the other film forming apparatus 10, and a new layer (2 nd layer) is stacked on the 1 st layer by the other film forming apparatus 10. In addition, at the time of lamination, films of different materials can be laminated by changing the base material 20 as a film-forming raw material. By laminating the thin film, at least a part of a laminated structure of an electronic device such as a thin film transistor (TFT; thin Film Transistor) constituting a semiconductor device can be formed on the 1 st substrate P1 as a supporting base material.
For example, in the case of forming a bottom contact type TFT (thin film transistor), the film forming apparatus 10 is used on the 1 st substrate P1A metal material (Cu, al, mo, etc.) or a thin film of ITO (1 st conductive layer), an insulating material (SiO) 2 、Al 2 O 3 Etc.), a thin film (insulating layer) of a metal material (Cu, al, mo, etc.), a thin film (2 nd conductive layer), and at least a part of the laminated structure constituting the TFT are formed on the 1 st substrate P1. In the case of forming the top contact TFT, a thin film (1 st conductive layer) of a metal material (Cu, al, mo, etc.), a thin film (semiconductor layer) of an oxide semiconductor (IGZO, znO, etc.), silicon (α -Si), an organic semiconductor (pentacene), etc., and an insulating material (SiO) are sequentially laminated by the film forming apparatus 10 2 、Al 2 O 3 Etc.), a metal material (Cu, al, mo, etc.), or a thin film of ITO (2 nd conductive layer), thereby enabling to form a laminated structure constituting the TFT on the 1 st substrate P1.
The 1 st substrate P1 having the laminated structure formed in the above manner is processed into a pattern shape having an electrode layer, an insulating layer, a wiring layer, a semiconductor layer, or the like for a semiconductor device by a non-vacuum processing apparatus such as photolithography (photo patterning) and etching, which will be described later. The laminated structure of the 1 st substrate P1 processed into such a pattern shape is transferred to a substrate (hereinafter referred to as a 2 nd substrate) P2. Fig. 2 is a diagram showing a configuration of a lamination device 30 for transferring a lamination structure formed (carried) on the 1 st substrate P1 to the 2 nd substrate P2 (product substrate). The lamination device 30 is, for example, a low-temperature thermal transfer type device that transfers a lamination structure formed on the 1 st substrate P1 to the 2 nd substrate P2 at a low temperature of 100 degrees or less. The laminating apparatus 30 includes supply rolls 32 and 34, pressure-bonding heating rolls 36, recovery rolls 38 and 40, and guide rolls GR5 and GR6.
The supply roll 32 is a roll for winding the 1 st substrate P1 having the laminated structure formed on the surface thereof, and carries the 1 st substrate P1 out of the recovery roll 38. The supply roll 34 is a roll that rolls the 2 nd substrate P2 of the transfer laminate structure, and the 2 nd substrate P2 is carried out to the recovery roll 40. The 2 nd substrate P2 is also a flexible sheet-like substrate (sheet-like substrate, transfer substrate) similar to the 1 st substrate P1, and has a belt-like shape in which the movement direction of the 2 nd substrate P2 is the long side direction (long strip) and the width direction is the short side direction (short strip).
The pressure-bonding heating roller 36 temporarily holds the 1 st substrate P1 supplied from the supply roll 32 and the 2 nd substrate P2 supplied from the supply roll 34 from both sides, and temporarily applies pressure-bonding to both substrates and simultaneously heats them. This enables the laminated structure formed on the 1 st substrate P1 to be transferred to the 2 nd substrate P2. That is, the laminated structure formed on the 1 st substrate P1 is softened by heating (for example, a low temperature of 100 degrees or less) by the press-bonding heating roller 36, and the softened laminated structure on the 1 st substrate P1 is transferred to the 2 nd substrate P2 by press-bonding by the press-bonding heating roller 36. The surface of the pressure-contact heat roller 36 is preferably made of an elastomer, and the temperature and pressure (pressing force) of the pressure-contact heat roller 36 are arbitrarily set depending on the transfer material.
The recovery reel 38 is used to recover the 1 st substrate P1, i.e., the 1 st substrate P1 from which the laminate structure has been peeled off, by winding up the 1 st substrate P1 by the pressure-bonding heating roller 36. The recovery reel 40 is configured to collect the 2 nd substrate P2 (the 2 nd substrate P2 having the laminated structure formed on the surface) transferred by the pressure-bonding heating roller 36 by winding up the 2 nd substrate P2, that is, the 2 nd substrate P2 having the laminated structure transferred thereto. The guide roller GR5 is used for guiding the 1 st substrate P1 supplied from the supply reel 32 to the press-bonding heating roller 36, and the guide roller GR6 is used for guiding the 2 nd substrate P2 supplied from the supply reel 34 to the press-bonding heating roller 36.
Here, for example, a foil (foil) made of a metal or an alloy such as a resin film or stainless steel may be used for the 1 st substrate P1 and the 2 nd substrate P2. As a material of the resin film, for example, a material including at least one of a polyethylene resin, a polypropylene resin, a polyester resin, an ethylene-vinyl acetate copolymer resin, a polyvinyl chloride resin, a cellulose resin, a polyamide resin, a polyimide resin, a polycarbonate resin, a polystyrene resin, and a vinyl acetate resin can be used. The thickness or rigidity (young's modulus) of the 1 st substrate P1 and the 2 nd substrate P2 may be in a range where no crease or irreversible wrinkle occurs in the 1 st substrate P1 and the 2 nd substrate P2 due to bending during conveyance. Films such as PET (polyethylene terephthalate) and PEN (polynaphthalate) having a thickness of 25 μm to 200 μm are typical of preferred sheet-like substrates as the base materials of the 1 st substrate P1 and the 2 nd substrate P2.
Since the 1 st substrate P1 and the 2 nd substrate P2 may be heated during the process applied to the 1 st substrate P1 and the 2 nd substrate P2, it is preferable to select a substrate having a material having a not significantly large thermal expansion coefficient. For example, the thermal expansion coefficient can be suppressed by mixing an inorganic filler to the resin film. The inorganic filler may be, for example, titanium oxide, zinc oxide, aluminum oxide, silicon oxide, or the like. The 1 st substrate P1 and the 2 nd substrate P2 may be a single layer of an extremely thin glass having a thickness of about 100 μm manufactured by a float method or the like, or may be a laminate in which the resin film, foil or the like is bonded to the extremely thin glass.
Further, as in the film forming apparatus 10 of fig. 1, since the 1 st substrate P1 is heated to, for example, 100 to 300 ℃ during film formation, the 1 st substrate P1 is preferably a polyimide resin, an extremely thin sheet glass, an extremely thin metal foil (copper foil rolled to a thickness of several tens to several hundreds of μm, stainless steel foil, aluminum foil) or the like, which is excellent in heat resistance. The 1 st substrate P1 is not necessarily a long sheet-like substrate that can be wound into a roll, but may be a single sheet-like substrate, a glass substrate, or a metal plate cut into a size corresponding to the size of the electronic component (or a circuit board thereof) to be manufactured.
Next, a method for manufacturing a TFT will be described. The TFT structure can be largely classified into a bottom gate structure and a top gate structure, but in embodiment 1, the steps of manufacturing the TFT of the bottom gate structure will be described, and the description of the steps of manufacturing the TFT of the top gate structure will be omitted. Since TFTs of bottom gate structure are classified into bottom contact type and top contact type, a method of manufacturing a bottom contact type TFT will be described first, and then a method of manufacturing a top contact type TFT will be described.
(method for manufacturing bottom contact type TFT)
Fig. 3 and 4 are flowcharts showing an example of steps of a method for manufacturing a bottom-contact TFT, and fig. 5A to 5F and 6A to 6D are cross-sectional views showing a state of passing through the manufacturing process of the TFT manufactured by the steps shown in fig. 3 and 4. First, in step S1 of fig. 3, as shown in fig. 5A, a peeling layer 50 is formed on a 1 st substrate P1. For example, the release layer 50 may be formed by applying a fluorine-based material or an alkali-soluble release agent (an alkali-soluble material) to the surface of the 1 st substrate P1, or by laminating a Dry Film Resist (DFR) having a photosensitive alkali-soluble film formed thereon on the 1 st substrate P1. Examples of the alkali-soluble mold release agent include a mixture of a binder resin and a carboxyl group. The release layer 50 is a layer for easily peeling the laminated structure from the 1 st substrate P1.
Next, as shown in fig. 5B, a laminated structure 52 is formed on the 1 st substrate P1 (1 st step). The laminated structure 52 is formed by a metal material (conductive material such as Cu, al, mo, au) or a thin film (1 st conductive layer) 52a of ITO (conductive material) deposited on the 1 st substrate P1 (on the release layer 50) with a predetermined thickness, and an insulating material (SiO) deposited on the 1 st conductive layer 52a with a predetermined thickness 2 、Al 2 O 3 And the like), a thin film (functional layer) 52b of a metal material (conductive material such as Cu, al, mo, au) or a thin film (2 nd conductive layer) 52c of ITO (conductive material) deposited on the functional layer 52b with a predetermined thickness. In addition, when copper (Cu) is used as the material of the 1 st conductive layer 52a and the 2 nd conductive layer 52c constituting the laminated structure 52, copper (Cu) is also used as the material of the 1 st substrate P1 so that the thermal expansion coefficient is uniform.
In step S2, the 1 st conductive layer 52a is formed (deposited) on the 1 st substrate P1 (the release layer 50). Next, in step S3, a functional layer 52b, which is an insulating layer, is formed (deposited) on the 1 st conductive layer 52a, and in step S4, a 2 nd conductive layer 52c is formed (deposited). Thereby, the laminated structure 52 is formed on the 1 st substrate P1. The 1 st conductive layer 52a, the functional layer 52b, and the 2 nd conductive layer 52c are continuously formed on the 1 st substrate P1 by using the film forming apparatus 10 of fig. 1. The 1 st conductive layer 52a functions as an electrode layer of the source electrode and the drain electrode and a wiring layer of a wiring attached to the source electrode and the drain electrode. The 2 nd conductive layer 52c functions as an electrode layer of the gate electrode and a wiring layer of a wiring attached to the gate electrode. Here, in order to improve the electrical characteristics (mobility, ON/OFF ratio, leakage current, etc.) of the TFT, the interface between the 1 st conductive layer 52a and the functional layer 52b or the interface between the functional layer 52b and the 2 nd conductive layer 52c is preferably planarized to a level of submicron or less. Therefore, the surface of the 1 st substrate P1 on the release layer 50 side is preferably planarized at a level of submicron or less.
Thereafter, the 1 st substrate P1 on which the laminated structure 52 is formed is subjected to an etching process by photolithography, and as shown in fig. 5C, a gate electrode and wiring attached thereto are formed on the 2 nd conductive layer 52C (step 1). In addition, only the gate electrode is shown in fig. 5C.
Since the etching process using this photolithography method is a well-known technique, it is briefly described that a photoresist layer is formed on the 2 nd conductive layer 52c in step S5. The formation of the resist layer can be simply performed by roll printing, spin coating, blowing, or the like of a liquid resist, or by laminating a resist layer of a Dry Film Resist (DFR) on the 2 nd conductive layer 52 c. Next, in step S6, a predetermined pattern (pattern of the gate electrode and wiring or the like attached thereto) is exposed to ultraviolet rays on the formed photoresist layer, and in step S7, development is performed (the 1 st substrate P1 is immersed in a developer such as TMAH) to remove the photoresist layer at the portion exposed to ultraviolet rays. Thereby, a predetermined pattern (resist image) is formed on the photoresist layer. Next, in step S8 after cleaning and drying of the 1 st substrate P1, the 1 st substrate P1 on which the laminated structure 52 is formed is immersed in an etchant (for example, ferric oxide), and an etching process is performed using the photoresist layer formed with a predetermined pattern as a mask, whereby a gate electrode, wiring and the like attached to the gate electrode are formed on the 2 nd conductive layer 52 c. Next, in step S9, the resist layer on the 2 nd conductive layer 52c is peeled off, and the 1 st substrate P1 is cleaned. Thus, a laminated structure 52 shown in fig. 5C is produced. The 1 st substrate P1 may be cleaned by an alkaline cleaning solution such as NaOH.
Next, in step S10, as shown in fig. 5D, the adhesive agent is applied to the surface side (laminate structure 52 side) of the 1 st substrate P1 on which the laminate structure 52 is formed, thereby forming the adhesive layer 54. The adhesive layer 54 is used to facilitate transfer (adhesion) of the laminated structure 52 formed on the 1 st substrate P1 to the 2 nd substrate P2. As the adhesive, for example, an adhesive for dry lamination, a UV (ultraviolet) curing adhesive which is convertible from a liquid to a solid in response to light energy of ultraviolet rays, or a thermosetting adhesive can be used. In embodiment 1, an adhesive for dry lamination is used.
Next, in the case of drying the adhesive for lamination, the 1 st substrate P1 and the 2 nd substrate P2 are temporarily brought close to or brought into close contact with each other so that the 2 nd conductive layer 52c is located on the 2 nd substrate P2 side, and the laminated structure 52 formed on the 1 st substrate P1 is transferred to the 2 nd substrate P2 (step 2). This transfer is performed by the lamination device 30 shown in fig. 2. That is, the release layer 50, the laminated structure 52, and the adhesive layer 54 are used as the supply roll 32 of the laminating apparatus 30 by winding the 1 st substrate P1 laminated in the order described above from the surface side of the 1 st substrate P1, so that the laminated structure 52 formed on the 1 st substrate P1 can be transferred to the 2 nd substrate P2. At this time, the peeling layer 50 is not transferred to the 2 nd substrate P2 side but remains on the 1 st substrate P1 side.
Specifically, first, as shown in fig. 5E, the adhesive layer 54 formed on the laminated structure 52 is adhered to the surface of the 2 nd substrate P2 (step S11), and as shown in fig. 5F, the laminated structure 52 is peeled from the 1 st substrate P1 by the peeling layer 50 (step S12). Thereby, the laminated structure 52 on the 1 st substrate P1 is transferred to the 2 nd substrate P2. By this transfer, the laminated structure 52 is formed on the 2 nd substrate P2 in an inverted state. That is, the 2 nd conductive layer 52c, the functional layer 52b, and the 1 st conductive layer 52a constituting the laminated structure 52 are laminated on the 2 nd substrate P2 in the order described above from the surface side of the 2 nd substrate P2, and the 1 st conductive layer 52a is exposed. The 2 nd substrate P2 to which the laminated structure 52 is transferred by the laminating apparatus 30 is wound up by the recovery reel 40. When the release layer 50 has been peeled off from the 1 st substrate P1 and transferred to the 2 nd substrate P2 side, the release layer 50 is removed and the 2 nd substrate P2 is cleaned. The 2 nd substrate P2 may be cleaned by using an alkaline cleaning solution such as NaOH. The peeling layer 50 is soluble and thus can be removed from the 1 st conductive layer 52a by a solvent.
Next, the recovery reel 40 is used as a supply roller, and the 2 nd substrate P2 carried out from the supply roller is subjected to etching treatment by photolithography, whereby source and drain electrodes and wiring attached to the source and drain electrodes are formed on the 1 st conductive layer 52a as shown in fig. 6A (step 4). Fig. 6A shows only the source electrode and the drain electrode.
To briefly explain the formation of a source electrode or the like by an etching process using photolithography, first, in step S13 of fig. 4, a photoresist layer is formed on the surface side (1 st conductive layer 52a side) of the 2 nd substrate P2. The resist layer is formed by transfer of a Dry Film Resist (DFR), coating of a liquid resist, or the like, as described in step S5. Next, in step S14, a predetermined pattern (pattern of source and drain electrodes, wiring attached to the source and drain electrodes, and the like) is exposed to the formed photoresist layer using ultraviolet light, and development is performed in step S15. Thereby forming a predetermined pattern on the photoresist layer. Next, in step S16, the 2 nd substrate P2 on which the laminated structure 52 is formed is immersed in an etchant (for example, ferric oxide or the like), and the photoresist layer on which a predetermined pattern is formed is subjected to etching treatment as a mask, so that a source electrode, a drain electrode, and the like are formed on the 1 st conductive layer 52 a. Next, in step S17, the resist layer on the 1 st conductive layer 52a is peeled off, and the 2 nd substrate P2 is cleaned. Thus, a laminated structure 52 as shown in FIG. 6A is obtained.
The source electrode and the drain electrode must be precisely aligned (stacked) with respect to the gate electrode (the 2 nd conductive layer 52 c) below the functional layer (insulating layer) 52b in the vicinity thereof. The exposure apparatus (drawing apparatus) used in the exposure step of step S14 has a function of precisely adjusting the relative positional relationship between the ultraviolet rays and the 2 nd substrate P2 corresponding to the predetermined pattern (pattern of the source electrode, the drain electrode, and the wiring or the like) to be exposed in step S14, based on the detection position of the alignment mark formed by the 2 nd conductive layer 52c on the 1 st substrate P1, and the functional layer (insulating layer) 52b or the alignment sensor directly optically detecting the alignment mark in the step of forming the gate electrode or the like of steps S5 to S9 in fig. 3.
Next, in step S18, as shown in fig. 6B, au replacement plating is performed on the source electrode and the drain electrode of the 1 st conductive layer 52a (step 4). Au (gold) 56 applied by the substitution plating process serves to reduce the resistance of the contact interface between the source electrode and the drain electrode and the semiconductor layer (to be described later) (to improve electron mobility).
Thereafter, in step S19, as shown in fig. 6C, a thin film (semiconductor layer) 58 of a semiconductor (IGZO, znO, etc.) is formed on the 2 nd substrate P2 (on the 1 st conductive layer 52 a) (step 4). Next, an etching process using photolithography is performed to process the semiconductor layer 5 as shown in fig. 6D (step 4). That is, a resist layer is formed on the semiconductor layer 58 in step S20, a predetermined pattern is formed on the formed resist layer using ultraviolet rays in step S21, and development is performed in step S22. At the time of this exposure, the alignment mark is detected by the alignment sensor, so that the portion to be left in the semiconductor layer 58 is precisely positioned across between the drain electrode and the source electrode.
Thereby forming a predetermined pattern on the photoresist layer. Next, in step S23, the 2 nd substrate P2 is immersed in an etchant (for example, hydrogen fluoride) to etch the photoresist layer having the predetermined pattern formed thereon as a mask, thereby processing the semiconductor layer 58. As a result, as shown in fig. 6D, the semiconductor layer 58 at least between the source electrode and the drain electrode remains, and the unnecessary semiconductor layer 58 other than this can be removed. Thereafter, in step S24, the resist layer on the semiconductor layer 58 is stripped, and the 2 nd substrate P2 is cleaned. By this step, a bottom contact TFT as shown in fig. 6D is formed on the 2 nd substrate P2. In addition, the semiconductor layer 58 may be an organic semiconductor or an oxide semiconductor. In this case, the semiconductor layer 58 may be formed between the source electrode and the drain electrode by a lift-off method after the liquid material of the semiconductor is selectively applied to the region including the space between the source electrode and the drain electrode (channel portion) by patterning with a resist in advance.
In the above-described steps, at least the steps S1 to S4 (fig. 5A and 5B) of fig. 3 may be performed by the supplier of the 1 st substrate P1, and the steps subsequent to the steps performed by the supplier may be performed by the manufacturer of the electronic device. For example, the steps of step S1 to step S4 of fig. 3 may be performed by the supplier, and the steps of step S5 of fig. 3 to step S24 of fig. 4 (fig. 5C to 6D) may be performed by the manufacturer. In the present embodiment, the 1 st substrate P1 (the supporting substrate for the laminate structure 52) manufactured through the steps S1 to S4 in fig. 3 is supplied to the manufacturer of the electronic component in a state of being wound into a roll as an intermediate product or in a state of being cut into pieces of a predetermined length.
As described above, for example, the step S1 to step S4 of fig. 3 (the step of using a vacuum processing apparatus is necessary) is performed by the supplier of the 1 st substrate P1, and the step S5 to step S24 of fig. 3 (the step of not using a vacuum processing apparatus) is performed by the manufacturer of the TFT (electronic component), whereby the burden of the manufacturer of the electronic component can be reduced, and the high-precision electronic component can be manufactured easily. That is, in order to manufacture an electronic component with high precision, at least a part of the laminated structure 52 constituting the electronic component must be formed in a vacuum space, but since a manufacturer of the electronic component does not need to form a film in the vacuum space, the burden on the manufacturer of the electronic component can be reduced. Further, since the manufacturer of the electronic component only needs to form the electronic component using the 1 st substrate P1 on which the laminated structure 52 is formed, the number and arrangement of the electronic components can be arbitrarily determined to manufacture the electronic component, and the degree of freedom in the arrangement of the thin film transistors and the like constituting the electronic component, the wiring, the bus line, and the like can be improved. In addition, even if a manufacturer does not have a large number of vacuum vapor deposition apparatuses, coating apparatuses, sputtering apparatuses, or the like, which are necessary for forming all layers constituting an electronic component, it is possible to easily manufacture a high-performance electronic component.
(method for manufacturing top contact type TFT)
Fig. 7 and 8 are flowcharts showing an example of steps of a method for manufacturing a top-contact TFT, and fig. 9A to 9D and 10A to 10C are cross-sectional views showing a state of passing through the manufacturing process of the TFT manufactured by the steps shown in fig. 7 and 8. First, in step S31 in fig. 7, as shown in fig. 9A, a peeling layer 70 is formed on a 1 st substrate P1. This step is the same as step S1 of fig. 3.
Next, as shown in fig. 9B, a laminated structure 72 is formed on the 1 st substrate P1 (step 1). The laminated structure 72 is formed by stacking a plurality of layers with a predetermined thicknessA thin film (1 st conductive layer) 72a of a metal material (conductive material such as Cu, al, mo, au) or ITO (conductive material) deposited on the 1 st substrate P1 (on the release layer 70), a thin film (semiconductor layer) 72b1 of a semiconductor (material exhibiting semiconductor characteristics such as IGZO, znO, silicon, pentacene, etc.) deposited on the 1 st conductive layer 72a at a predetermined thickness, and an insulating material (SiO) deposited on the semiconductor layer 72b1 at a predetermined thickness 2 、Al 2 O 3 Etc.), a thin film (insulating layer) 72b2 of an insulating material, a metal-based material (conductive material such as Cu, al, mo, au) deposited on the insulating layer 72b2 at a predetermined thickness, or a thin film (2 nd conductive layer) 72c of an ITO (conductive material). The semiconductor layer 72b1 and the insulating layer 72b2 constitute a functional layer 72b. In the same manner as above, the base material of the 1 st substrate P1 is preferably polyimide resin, extremely thin glass, or extremely thin metal foil (copper foil, stainless steel foil, aluminum foil rolled to a thickness of several tens μm to several hundreds μm) having excellent heat resistance in consideration of heating (100 to 300 ℃) at the time of film formation. As the release layer 70, a fluorine-based material, an alkali-soluble release agent, an inorganic-based release agent, a silicon release agent, or the like can be used as in the release layer 50 described above with reference to fig. 3 to 5F.
In step S32, the 1 st conductive layer 72a is formed (deposited) on the 1 st substrate P1 (the release layer 70). Next, in step S33, a semiconductor layer 72b1 is formed (deposited) on the 1 st conductive layer 72a, and in step S34, an insulating layer 72b2 is formed (deposited) again, thereby forming a functional layer 72b. Thereafter, in step S35, the 2 nd conductive layer 72c is formed (deposited) on the functional layer 72b. Thereby, the laminated structure 72 is formed on the 1 st substrate P1. The 1 st conductive layer 72a, the semiconductor layer 72b1, the insulating layer 72b2, and the 2 nd conductive layer 72c are continuously formed on the 1 st substrate P1 by using the film forming apparatus 10 described above. The 1 st conductive layer 72a functions as an electrode layer of the source electrode and the drain electrode and a wiring layer of a wiring attached to the source electrode and the drain electrode. The 2 nd conductive layer 72c functions as an electrode layer of the gate electrode and a wiring layer of a wiring attached to the gate electrode. In the above configuration, when the 1 st substrate P1 or the 1 st conductive layer 72a is made of a metal material (e.g., cu), the semiconductor layer 72b1 is formed on the 1 st conductive layer 72a, and can be heated to a temperature (e.g., 200 ℃ or higher) far higher than the glass transition temperature of the resin film such as PET, so that the orientation (crystallization) of the organic semiconductor material, the oxide semiconductor material, or the like can be performed well, and the electrical characteristics (e.g., mobility) of the TFT can be improved in a jump-like manner. Further, at least the interface between the 1 st conductive layer 72a and the semiconductor layer 72b1 and the interface between the insulating layer 72b2 and the 2 nd conductive layer 72c are planarized at a level of submicron or less, respectively, which contributes to improvement of the electrical characteristics of the TFT.
Thereafter, the 1 st substrate P1 on which the laminated structure 72 is formed is subjected to an etching process by photolithography, and as shown in fig. 9C, a gate electrode and wiring attached thereto are formed on the 2 nd conductive layer 72C (step 1). In addition, only the gate electrode is shown in fig. 9C.
Briefly describing the etching process using this photolithography method, first, in step S36, a photoresist layer is formed on the 2 nd conductive layer 72 c. The resist layer is formed by transfer of a dry film resist, coating of a resist solution, or the like, as described in step S5 of fig. 3. Next, in step S37, the formed photoresist layer is exposed to ultraviolet light in a predetermined pattern (pattern of the gate electrode and wiring and the like attached thereto), and in step S38, development is performed (the 1 st substrate P1 is immersed in a developer such as TMAH). Thereby forming a predetermined pattern on the photoresist layer. Next, in step S39, the 1 st substrate P1 on which the laminated structure 72 is formed is immersed in an etchant (for example, ferric oxide), and an etching process is performed using the photoresist layer formed with a predetermined pattern as a mask, whereby a gate electrode or the like is formed on the 2 nd conductive layer 72 c. Next, in step S40, the resist layer on the 2 nd conductive layer 72c is peeled off, and the 1 st substrate P1 is cleaned. Thus, a laminated structure 72 shown in fig. 9C is produced. The 1 st substrate P1 may be cleaned by an alkaline cleaning solution such as NaOH.
Next, in step S41 of fig. 8, the adhesive agent is applied to the surface side (the laminated structure 72 side) of the 1 st substrate P1 on which the laminated structure 72 is formed, thereby forming the adhesive layer 54.
Next, the 1 st substrate P1 and the 2 nd substrate P2 are temporarily brought close to or brought into close contact with each other so that the 2 nd conductive layer 72c is located on the 2 nd substrate P2 side, and the laminated structure 72 formed on the 1 st substrate P1 is transferred to the 2 nd substrate P2 (step 2). The transfer is performed by the lamination device 30 described above. That is, the 1 st substrate P1 laminated in the order of the release layer 70, the laminated structure 72, and the adhesive layer 74 from the surface side of the 1 st substrate P1 is set in a roll-like state on the supply roll 32 of the laminating apparatus 30. The build-up structure 72 formed on the 1 st substrate P1 can be transferred to the 2 nd substrate P2 by the build-up device 30. At this time, the peeling layer 70 for easily peeling the laminated structure 72 from the 1 st substrate P1 is not transferred to the 2 nd substrate P2 side but remains on the 1 st substrate P1 side.
First, as shown in fig. 10A, the adhesive layer 74 formed on the laminated structure 72 is adhered to the surface of the 2 nd substrate P2 (step S42), and as shown in fig. 10B, the laminated structure 72 is peeled from the 1 st substrate P1 by the peeling layer 70 (step S43). Thereby, the laminated structure 72 on the 1 st substrate P1 is transferred to the 2 nd substrate P2. By this transfer, the laminated structure 72 is formed on the 2 nd substrate P2 in an inverted state. That is, the 2 nd conductive layer 72c, the functional layer 72b, and the 1 st conductive layer 72a constituting the laminated structure 72 are laminated on the 2 nd substrate P2 in the order described above from the surface side of the 2 nd substrate P2, and the 1 st conductive layer 72a is exposed. The 2 nd substrate P2 to which the laminated structure 72 is transferred by the laminating apparatus 30 is wound up by the recovery reel 40. When the release layer 70 has been peeled off from the 1 st substrate P1 and transferred to the 2 nd substrate P2 side, the release layer 70 is removed and the 2 nd substrate P2 is cleaned. The peeling layer 70 is soluble and thus can be removed from the 1 st conductive layer 72a by a solvent.
Next, the recovery reel 40 is used as a supply roller, and the 2 nd substrate P2 carried out from the supply roller is subjected to etching treatment by photolithography, whereby source and drain electrodes and wiring attached to the source and drain electrodes are formed on the 1 st conductive layer 72a as shown in fig. 10C (step 4). Fig. 10C shows only the source electrode and the drain electrode.
To briefly explain the formation of a source electrode or the like by an etching process using photolithography, first, in step S44, a photoresist layer is formed on the surface side (1 st conductive layer 72a side) of the 2 nd substrate P2. The photoresist layer is formed by drying a film resist, coating, or the like as described in step S5 of fig. 3. Next, in step S45, the formed photoresist layer is exposed to a predetermined pattern (pattern of source and drain electrodes, wiring attached to the source and drain electrodes, and the like) using ultraviolet rays, and development is performed in step S46. Thereby forming a predetermined pattern on the photoresist layer. Next, in step S47, the 2 nd substrate P2 on which the laminated structure 72 is formed is immersed in an etchant (for example, ferric oxide or the like), and the photoresist layer on which a predetermined pattern is formed is subjected to etching treatment as a mask, so that a source electrode, a drain electrode, and the like are formed on the 1 st conductive layer 72 a. Next, in step S48, the resist layer on the 1 st conductive layer 72a is peeled off, and the 2 nd substrate P2 is cleaned. By this step, a top contact TFT as shown in fig. 10C is formed on the 2 nd substrate P2. The 2 nd substrate P2 may be cleaned by using an alkaline cleaning solution such as NaOH.
In the above-described steps, at least the steps S31 to S35 (fig. 9A and 9B) of fig. 7 may be performed by the supplier of the 1 st substrate P1, and the steps subsequent to the steps performed by the supplier may be performed by the manufacturer of the electronic device. For example, the steps of step S31 to step S35 of fig. 7 may be performed by the supplier, and the steps of step S36 of fig. 7 to step S48 of fig. 8 (fig. 9C to 10C) may be performed by the manufacturer.
As described above, for example, the step S31 to the step S35 in fig. 7 are performed by the supplier of the 1 st substrate P1, and the step S36 to the step S48 in fig. 7 to the step S48 in fig. 8 are performed by the manufacturer of the TFT (electronic component), whereby the burden of the manufacturer of the electronic component can be reduced, and the high-precision electronic component can be manufactured easily. That is, in order to manufacture an electronic component with high precision, at least a part of the laminated structure 72 constituting the electronic component must be formed in a vacuum space, but since a manufacturer of the electronic component does not need to form a film in the vacuum space, the burden on the manufacturer of the electronic component can be reduced. Further, since the manufacturer of the electronic component only needs to form the electronic component using the 1 st substrate P1 on which the laminated structure 72 is formed, the number and arrangement of the electronic components can be arbitrarily determined to manufacture the electronic component, and the degree of freedom in the arrangement of the thin film transistors and the like constituting the electronic component, the wiring, the bus line, and the like can be improved. In addition, even if a manufacturer does not have a large number of vacuum vapor deposition apparatuses, coating apparatuses, sputtering apparatuses, or the like, which are necessary for forming all layers constituting an electronic component, it is possible to easily manufacture a high-performance electronic component. In the same manner as in the present embodiment, the 1 st substrate P1 (the support substrate for the laminate structure 72) produced through the steps S31 to S35 in fig. 7 is supplied to the manufacturer of the electronic component in a state of being wound into a roll as an intermediate product or in a state of being cut into pieces of a predetermined length.
Modification of embodiment 1
The following modifications are also possible in embodiment 1.
Modification 1
In modification 1, a stacked structure is formed while etching treatment by photolithography is performed in the manufacture of a top-contact TFT. Fig. 11 and 12 are flowcharts showing an example of steps of the method for manufacturing a top-contact TFT according to modification 1, and fig. 13A to 13F and fig. 14A to 14F are cross-sectional views showing the state of passing by the manufacturing process of the TFT manufactured by the steps shown in fig. 11 and 12. First, in step S61 in fig. 11, as shown in fig. 13A, a peeling layer 80 is formed on a 1 st substrate P1. The step of forming the peeling layer 80 is the same as step S1 of fig. 3.
Next, in step S62, as shown in fig. 13B, an insulating material (SiO 2 、Al 2 O 3 Etc.) film (insulating layer) 82. The insulating layer 82 is formed on the 1 st substrate P1 by using the film forming apparatus 10 described above. The insulating layer 82 functions as passivation (passivation) and may also function as an etch stop.
Next, in step S63, as shown in fig. 13C, a thin film (1 st conductive layer) 84a of a metal material (conductive material such as Cu, al, mo, or the like) deposited in a predetermined thickness is formed on the 1 st substrate P1 (on the insulating layer 82) (1 st step). The 1 st conductive layer 84a functions as an electrode layer of the source electrode and the drain electrode and a wiring layer of a wiring attached to the source electrode and the drain electrode. The 1 st conductive layer 84a is formed on the 1 st substrate P1 by using the film forming apparatus 10 described above.
Thereafter, as shown in fig. 13D, a source electrode and a drain electrode and wirings attached to the source electrode and the drain electrode are formed on the 1 st conductive layer 84a by etching using photolithography (step 1). At this time, etching of the peeling layer 80 is prevented by the insulating layer 82 which also functions as an etching stopper. Fig. 13D shows only the source electrode and the drain electrode.
Briefly describing the formation of a source electrode or the like by an etching process using photolithography, first, in step S64, a photoresist layer is formed on the 1 st conductive layer 84 a. The photoresist layer is formed by drying a film resist, coating, or the like as described in step S5 of fig. 3. Next, in step S65, the formed photoresist layer is exposed to a predetermined pattern (pattern of source and drain electrodes, wiring attached to the source and drain electrodes, and the like) using ultraviolet rays, and development is performed in step S66. Thereby forming a predetermined pattern on the photoresist layer. Next, in step S67, the 1 st substrate P1 on which the 1 st conductive layer 84a is formed is immersed in an etchant (for example, ferric oxide or the like), and the photoresist layer on which a predetermined pattern is formed is subjected to etching treatment as a mask, so that a source electrode, a drain electrode, and the like are formed on the 1 st conductive layer 84 a. Next, in step S68, the resist layer on the 1 st conductive layer 84a is peeled off, and the 1 st substrate P1 is cleaned.
Next, in step S69, as shown in fig. 13E, a thin film (semiconductor layer) 84b1 of a semiconductor (IGZO, znO, or the like) deposited in a predetermined thickness is formed on the 1 st substrate P1 (on the 1 st conductive layer 84 a) (1 st step). The semiconductor layer 84b1 is formed on the 1 st substrate P1 by using the film forming apparatus 10 described above. Next, an etching process using photolithography is performed to process the semiconductor layer 84b1 as shown in fig. 13F (step 1). That is, in step S70, a photoresist layer is formed on the semiconductor layer 84b1. The photoresist layer is formed by drying a film resist, coating, or the like as described in step S5 of fig. 3. Next, in step S71, a predetermined pattern is exposed to the formed photoresist layer using ultraviolet rays, and development is performed in step S72. Thereby forming a predetermined pattern on the photoresist layer. Next, in step S73, the 1 st substrate P1 is immersed in an etchant (for example, hydrogen fluoride or the like), and the photoresist layer having the predetermined pattern formed thereon is subjected to etching treatment as a mask, thereby processing the semiconductor layer 84b1. As a result, as shown in fig. 13F, the semiconductor layer 84b1 located at least between the source electrode and the drain electrode remains, and the unnecessary semiconductor layer 84b1 other than this can be removed. Next, in step S74, the resist layer is peeled off, and the 1 st substrate P1 is cleaned.
Thereafter, in step S75 of fig. 12, as shown in fig. 14A, an insulating material (SiO 2 、Al 2 O 3 Etc.) film (insulating layer) 84b2 (step 1). The insulating layer 84b2 is formed on the 1 st substrate P1 by using the film forming apparatus 10 described above. The semiconductor layer 84b1 and the insulating layer 84b2 constitute a functional layer 84b.
Next, in step S76, as shown in fig. 14B, a thin film (2 nd conductive layer) 84c of a metal material (conductive material such as Cu, al, mo, etc.) deposited in a predetermined thickness is formed on the 1 st substrate P1 (on the insulating layer 84B 2). The 2 nd conductive layer 84c is formed on the 1 st substrate P1 by using the film forming apparatus 10 described above. The 2 nd conductive layer 84c functions as an electrode layer of the gate electrode and a wiring layer of a wiring attached to the gate electrode. The 1 st conductive layer 84a, the functional layer 84b, and the 2 nd conductive layer 84c constitute a laminated structure 84.
Next, an etching process using photolithography is performed, and as shown in fig. 14C, a gate electrode and a wiring attached to the gate electrode are formed on the 2 nd conductive layer 84C (step 1). In fig. 14C, only the gate electrode is shown. In the step shown in fig. 14C, the 1 st substrate P1 on which the 2 nd conductive layer 84C is formed is subjected to etching treatment by photolithography to form a gate electrode and wiring attached to the gate electrode. Thereby, a TFT is formed on the 1 st substrate P1.
Briefly describing the formation of a gate electrode or the like by an etching process using photolithography, first, in step S77, a photoresist layer is formed on the 2 nd conductive layer 84 c. The photoresist layer is formed by drying a film resist, coating, or the like as described in step S5 of fig. 3. Next, in step S78, a predetermined pattern (pattern of the gate electrode and wiring or the like attached thereto) is exposed to the formed photoresist layer using ultraviolet light, and development is performed in step S79. Thereby forming a predetermined pattern on the photoresist layer. Next, in step S80, the 1 st substrate P1 is immersed in an etchant (for example, ferric oxide or the like), and an etching process is performed using the photoresist layer formed with a predetermined pattern as a mask, so that a gate electrode, wiring attached thereto, and the like are formed on the 2 nd conductive layer 84 c. Next, in step S81, the resist layer on the 2 nd conductive layer 84c is peeled off, and the 1 st substrate P1 is cleaned. The laminated structure 84 is formed on the 1 st substrate P1 by the steps from step S63 in fig. 11 to step S81 in fig. 12.
Next, in step S82, as shown in fig. 14D, an adhesive agent is applied to the 1 st substrate P1, that is, the 2 nd conductive layer 84c, on which the laminated structure 84 is formed, to form an adhesive layer 86. The adhesive layer 86 is used to easily transfer (adhere) the laminated structure 84 formed on the 1 st substrate P1 to the 2 nd substrate P2. As this adhesive, for example, UV curable resin can be used. In this case, ultraviolet rays are irradiated to the adhesive layer 86 after the adhesive layer 86 is formed.
Next, in step S83, the 1 st substrate P1 and the 2 nd substrate P2 are temporarily brought close to or brought into close contact with each other so that the 2 nd conductive layer 84c is located on the 2 nd substrate P2 side, and the laminated structure 84 formed on the 1 st substrate P1 is transferred to the 2 nd substrate P2 as shown in fig. 14E (step 2). The transfer is performed by the lamination device 30. That is, the 1 st substrate P1, which is laminated in the order of the release layer 80, the insulating layer 82, the laminated structure 84, and the adhesive layer 86 from the surface side of the 1 st substrate P1, is wound into a roll and used as the supply roll 32 of the laminating apparatus 30, whereby the laminated structure 84 formed on the 1 st substrate P1 can be transferred to the 2 nd substrate P2. Thus, the laminated structure 84 is formed on the 2 nd substrate P2 in an inverted state. That is, the 2 nd conductive layer 84c, the functional layer 84b, and the 1 st conductive layer 84a constituting the laminated structure 84 are laminated on the 2 nd substrate P2 in the order described above from the surface side of the 2 nd substrate P2. At this time, the release layer 80 is not transferred to the 2 nd substrate P2 side but remains on the 1 st substrate P1 side. The 2 nd substrate P2 to which the laminated structure 84 is transferred by the laminating apparatus 30 is wound up by the recovery reel 40. By this step, a top contact TFT as shown in fig. 14E is formed on the 2 nd substrate P2.
Further, after the laminated structure 84, that is, the TFT is transferred onto the 2 nd substrate P2, the insulating layer 82 may be processed as shown in fig. 14F by performing an etching process using a photolithography method (step 4). By the steps shown in fig. 14F, the insulating layer 82 at least between the source electrode and the drain electrode remains, and the insulating layer 82 is not required except for this.
In the above-described steps, at least the steps S61 of fig. 11 to S81 of fig. 12 (fig. 13A to 14C) may be performed by the supplier of the 1 st substrate P1, and the steps subsequent to the steps performed by the supplier may be performed by the manufacturer of the electronic device. For example, the supplier may perform the steps from step S61 in fig. 11 to step S82 in fig. 12, and the manufacturer may perform the step S83 in fig. 12 (fig. 14E).
As described above, for example, the step S61 of fig. 11 to the step S82 of fig. 12 are performed by the supplier of the 1 st substrate P1, and at least the step S83 of fig. 12 is performed by the manufacturer of the electronic component, whereby the burden of the manufacturer of the electronic component can be reduced, and the electronic component with high accuracy can be manufactured.
Modification 2
In modification 1, the insulating layer 82 is formed between the release layer 80 and the 1 st conductive layer 84a, but in modification 2, the insulating layer 82 is not formed. That is, in modification 2, the step of step S62 in fig. 11 is not performed. Step S63 is performed after the step of step S61 in fig. 11. For example, a passivation layer may not be provided, and if the peeling layer 80 is not likely to be etched, the insulating layer 82 may not be provided between the peeling layer 80 and the 1 st conductive layer 84 a. In this case, since the insulating layer 82 is not formed, it is not necessary to process the insulating layer 82 by performing an etching process using a photolithography method on the insulating layer 82 as shown in fig. 14F.
Modification 3
The supplier of the 1 st substrate P1 may also provide the 1 st substrate P1 with the alignment mark Ks formed thereon to the manufacturer. The alignment mark Ks is a reference mark for relatively aligning (aligning) a predetermined pattern of the exposure region W exposed on the substrate with the substrate. By optically detecting the alignment mark Ks by an imaging device with a microscope, the position of the substrate (the position in the long side direction, the position in the short side direction, the inclined state of the substrate) or the distortion state in the plane of the substrate can be detected. The alignment marks Ks are formed at regular intervals along the longitudinal direction (longitudinal direction) of the substrate, for example, on the both end sides in the width direction of the substrate.
For example, the supplier of the 1 st substrate P1 may form the alignment mark Ks on the 2 nd conductive layer 52c (72 c) by performing an etching process using a photolithography method as shown in fig. 15 after forming the laminated structure 52 (72) on the 1 st substrate P1 as shown in fig. 5B or 9B (step 3). Next, the 1 st substrate P1 on which the alignment mark Ks is formed may be used to perform the steps after fig. 5C (fig. 9C). In this case, since the 1 st conductive layer 52a (72 a) is the surface side of the 2 nd substrate P2 by transfer, the 2 nd conductive layer 52c (72 c) is the deep side of the 2 nd substrate P2, and thus the formed alignment mark Ks is hidden by the 1 st conductive layer 52a (72 a). Accordingly, after transfer (for example, when forming a source electrode and a drain electrode), the window portion 90 may be formed by removing the 1 st conductive layer 52a (72 a) in the region opposite to the alignment mark Ks as shown in fig. 16 by etching using photolithography. The window 90 may be formed by forming the 1 st conductive layer 52a (72 a) not to face the alignment mark Ks. Thus, the step of removing the 1 st conductive layer 52a (72 a) in the region opposite to the alignment mark Ks can be omitted. Further, since the functional layer 52b (72 b) is made of a material having transmissivity, the imaging alignment mark Ks can be aligned optically by a microscope or the like, but when the functional layer 52b (72 b) is made of a material having no transmissivity, the window portion 90 is preferably provided also in the functional layer 52b (72 b). The window 90 is an opening formed for capturing the alignment mark Ks. The alignment mark Ks may be formed in the 1 st conductive layer 52a (72 a), and the window 90 may be formed in the 2 nd conductive layer 52c (72 c).
When the 1 st conductive layer 52a (72 a) is formed, the alignment mark Ks or the window 90 is formed in the 1 st conductive layer 52a (72 a) by using an etching process using a photolithography method, and when the 2 nd conductive layer 52c (72 c) is formed, the window 90 or the alignment mark Ks is formed in the 2 nd conductive layer 52c (72 c) by using an etching process using a photolithography method. In particular, in the modifications 1 and 2, the laminated structure 84 is gradually formed while etching is performed by photolithography, so that the alignment mark Ks and the window 90 may be formed together during the formation of the laminated structure 84.
In addition, when the supplier of the 1 st substrate P1 has grasped beforehand the wiring pattern (for example, the shape, arrangement, size, etc. of a large pattern such as a ground bus line, a power bus line, etc.) in the element region on the circuit board for electronic elements, the wiring patterns may be formed by etching using photolithography while forming the alignment mark Ks or the window portion 90 on the 1 st conductive layer 52a (72 a) or the 2 nd conductive layer 52c (72 c). Further, in the case where the supplier of the 1 st substrate P1 has grasped beforehand the region where the wiring pattern and the semiconductor element (TFT) are formed (or the region where the TFT is not formed at all), the semiconductor layer as the functional layer 52b (72 b) may be selectively deposited in the region where the TFT is formed, and the insulating layer as the functional layer 52b (72 b) may be selectively deposited in the region where the TFT is not formed at all. In this case, the thickness of the semiconductor layer and the insulating layer may be adjusted to be substantially the same as each other so that the thickness of the functional layer 52b (72 b) is as uniform as possible.
Modification 4
Fig. 17 is a diagram showing the structure of the lamination device 30a in modification 4. In modification 4, the same components as those in embodiment 1 are denoted by the same reference numerals, and description thereof is omitted. In modification 4, instead of the guide roller GR6, a guide roller GR6a having a larger radius than the guide roller GR6 is provided. The lamination device 30a is provided with a die coating head (die coating head) DCH for coating the 2 nd substrate P2 wound around the guide roller GR6a with a thermally curable adhesive that cures thermally. That is, in modification 4, the adhesive agent is applied not to the 1 st substrate P1 side but to the 2 nd substrate P2 side, thereby forming the adhesive layer 54 (74). Accordingly, the adhesive layer 54 is not provided on the 1 st substrate P1 (74). The region on the 2 nd substrate P2 coated with the thermosetting adhesive by the die coating head DCH is supported by the circumferential surface of the guide roller GR6a. The die coating head DCH applies the thermosetting adhesive to the 2 nd substrate P2 in a wide range and in the same manner. Thus, the laminated structure 52 (72) formed on the 1 st substrate P1 can be transferred to the 2 nd substrate P2 by the pressure-bonding heating roller 36.
Specifically, the pressure-bonding heating roller 36 is configured to heat the 1 st substrate P1 and the 2 nd substrate P2 while sandwiching them from both sides so that the laminated structure 52 (72) is located on the 2 nd substrate P2 side and is in contact with the thermosetting adhesive applied to the 2 nd substrate P2. Since the adhesive agent is cured by heat curing, the adhesive layer 54 (or 74) is formed, the laminated structure 52 (72) and the 2 nd substrate P2 are firmly adhered, and the laminated structure 52 (72) formed on the 1 st substrate P1 is transferred to the 2 nd substrate P2. Further, the 1 st substrate P1 and the 2 nd substrate P2 are separated from each other by the press-bonding heat roller 36.
Modification 5
Fig. 18 is a diagram showing the structure of the lamination device 30b in modification 5. In modification 5, the same components as those in embodiment 1 are denoted by the same reference numerals, and the description thereof is omitted. In modification 5, instead of the pressure-contact heating roller 36, a pressure-contact roller 36b that performs pressure-contact only without heating is provided, and instead of the guide roller GR6, a guide roller GR6b having a larger radius than the guide roller GR6 is provided. The press roller 36b has a roller R and a cylinder DRS having a larger radius than the roller R. The 1 st substrate P1 and the 2 nd substrate P2, which are held between the roller R and the cylinder DRS and are closely adhered, are conveyed along the circumferential surface of the cylinder DRS in a state of being superimposed on each other, and thereafter are separated from each other by the guide rollers GR7 and GR 8. The 1 st substrate P1 is guided by the recovery reel 38 through the guide roller GR7, and the 2 nd substrate P2 is guided by the recovery reel 40 through the guide roller GR 8.
The laminating apparatus 30b is provided with a die coating head DCH1 for coating the 2 nd substrate P2 wound around the guide roller GR6b with a UV curable adhesive agent that is cured by UV light. That is, in modification 5, the adhesive agent is applied not to the 1 st substrate P1 side but to the 2 nd substrate P2 side, thereby forming the adhesive layer 54 (74). Accordingly, the adhesive layer 54 is not provided on the 1 st substrate P1 (74). The area on the 2 nd substrate P2 coated with the UV curable adhesive by the die coating head DCH1 is supported by the circumferential surface of the guide roller GR6b. The die coating head DCH1 applies a UV curable adhesive to the 2 nd substrate P2 in a wide range and in the same manner. The laminating apparatus 30b is provided with an irradiation device UVS having a plurality of ultraviolet irradiation sources 94 for irradiating UV (ultraviolet) light to the UV curing adhesive before the 1 st substrate P1 and the 2 nd substrate P2 pressed by the pressing roller 36b are separated. Thus, the laminated structure 52 (72) formed on the 1 st substrate P1 can be transferred to the 2 nd substrate P2 by the pressure roller 36 b.
Specifically, the roller R and the cylinder DRS of the press roller 36b sandwich the 1 st substrate P1 and the 2 nd substrate P2 from both sides so that the laminated structure 52 (72) is located on the 2 nd substrate P2 side and is in contact with the UV curable adhesive applied on the 2 nd substrate P2. Thereafter, the irradiation device UVS irradiates UV light to the 1 st substrate P1 and the 2 nd substrate P2 which are conveyed while being wound around the cylinder DRS in a state of being superimposed on each other. By the irradiation of the UV light, the UV curable adhesive agent located between the 1 st substrate P1 and the 2 nd substrate P2 is cured, and thus the adhesive layer 54 (or 74) is formed, and the laminated structure 52 (72) and the 2 nd substrate P2 are firmly adhered. After the UV irradiation, the 1 st substrate P1 and the 2 nd substrate P2 are separated from each other by the guide rollers GR7, GR 8. Thereby, the laminated structure 52 (72) formed on the 1 st substrate P1 is transferred to the 2 nd substrate P2.
[ embodiment 2 ]
In embodiment 2, a specific method for manufacturing a pixel circuit of an organic EL display will be described. Fig. 19 is a diagram showing an example of a pixel circuit of one light emitting pixel of the active matrix organic EL display, and fig. 20 is a diagram showing a specific structure of the pixel circuit shown in fig. 19. The pixel circuit has a TFT, a capacitor C, and an organic light emitting diode (OLED: organic Light Emitting Diode). The source electrode S and the drain electrode D of the TFT, the wiring L1 attached thereto, the electrode C1 of one of the capacitors C, and the pixel electrode E connected to the cathode of the OLED are formed on the 1 st conductive layer 102 of the multilayer structure 100. The gate electrode G of the TFT, the wiring L2 attached thereto, and the other electrode C2 of the capacitor C are formed on the 2 nd conductive layer 104 of the multilayer structure 100. The electrode C2 of this capacitor C is connected to ground GND (ground). The electroless plating contact M is provided at a position where the wiring L1 formed in the 1 st conductive layer 102 and the wiring L2 formed in the 2 nd conductive layer 104 must be connected. In fig. 20, the 1 st conductive layer 102 is shown with diagonal lines for convenience of description in order to distinguish the 1 st conductive layer 102 from the 2 nd conductive layer 104.
In embodiment 2, a method for manufacturing a pixel circuit including a top-contact TFT will be described. Fig. 21 and 22 are flowcharts showing an example of steps of a method for manufacturing a pixel circuit.
First, after the steps S101 to S105, as shown in fig. 23, a peeling layer 106, a 1 st conductive layer 102, a semiconductor layer 108, an insulating layer 110, and a 2 nd conductive layer 104 are formed on the 1 st substrate P1 in this order from the surface side of the 1 st substrate P1. The steps from step S101 to step S105 are the same as those from step S31 to step S35 in fig. 7. The semiconductor layer 108 and the insulating layer 110 constitute a functional layer 112, and the 1 st conductive layer 102, the functional layer 112 (the semiconductor layer 108 and the insulating layer 110), and the 2 nd conductive layer 104 constitute the multilayer structure 100. In embodiment 2, the 1 st conductive layer 102 and the 2 nd conductive layer 104 are formed of Cu (copper), the semiconductor layer 108 is formed of ZnO, which is one type of oxide semiconductor, and the insulating layer 110 is formed of SiO 2 And (5) forming.
Next, by etching using photolithography, a predetermined pattern (the pattern of the gate electrode G, the wiring L2, and the electrode C2 of the capacitor C) is formed on the 2 nd conductive layer 104 as shown in fig. 24 and 25. In fig. 24, only the gate electrode G and the wiring L2 are shown in the 2 nd conductive layer 104. In fig. 25, the 1 st conductive layer 102 is shown with diagonal lines to distinguish the 1 st conductive layer 102 from the 2 nd conductive layer 104.
Briefly describing the formation of a gate electrode or the like by an etching process using photolithography, first, in step S106, a photoresist layer is formed on the 2 nd conductive layer 104. Next, in step S107, the applied photoresist layer is exposed to a predetermined pattern (pattern of the gate electrode G, the wiring L1, and the electrode C2) using ultraviolet rays, and development is performed in step S108. Thereby forming a predetermined pattern on the photoresist layer. Next, in step S109, the 1 st substrate P1 is immersed in an etchant of ferric oxide, and an etching process is performed using the photoresist layer having a predetermined pattern as a mask, thereby forming a gate electrode G or the like on the 2 nd conductive layer 104. Next, in step S110, the resist layer is stripped, and the 1 st substrate P1 is cleaned. The steps S106 to S110 are the same as the steps S36 to S40 in fig. 7. In the region after the 2 nd conductive layer 104 is removed by the etching treatment, the functional layer 112 is exposed.
Thereafter, in step S111, the 1 st substrate P1 is immersed in an etchant of hydrogen fluoride, whereby the functional layer 112 is also etched (processed) as shown in fig. 24. Since the functional layer 112 is exposed in the region from which the 2 nd conductive layer 104 is removed by the etching process of step S109, the functional layer 112 in the region from which the 2 nd conductive layer 104 is removed by the etching process of step S111.
Thereafter, in step S112, the adhesive agent is applied to the front surface side (the 2 nd conductive layer 104 side) of the 1 st substrate P1 on which the laminated structure 100 is formed, thereby forming the adhesive layer 114. Next, in step S113, the 1 st substrate P1 and the 2 nd substrate P2 are temporarily brought close to or brought into close contact with each other so that the 2 nd conductive layer 104 is located on the 2 nd substrate P2 side, and as shown in fig. 26, the laminated structure 100 formed on the 1 st substrate P1 is transferred to the 2 nd substrate P2. The transfer is performed by the lamination device 30. The steps of step S112 and step S113 are the same as the steps S41 to S43 in fig. 8.
Next, a predetermined pattern (the pattern of the source electrode S and the drain electrode D, the wiring L1, the electrode C1 of the capacitor C, and the pixel electrode E described above) is formed on the 1 st conductive layer 102 by etching using photolithography, as shown in fig. 27 and 28. In fig. 27, only the source electrode S, the drain electrode D, and the wiring L1 are illustrated in the 1 st conductive layer 102. In fig. 28, the 1 st conductive layer 102 is shown with diagonal lines to distinguish the 1 st conductive layer 102 from the 2 nd conductive layer 104.
Briefly described, a photoresist layer is formed on the surface side (1 st conductive layer 102 side) of the 2 nd substrate P2 in step S114 of fig. 22 by forming a source electrode or the like by etching processing using photolithography. Next, in step S115, a predetermined pattern (pattern of the source electrode S, drain electrode D, wiring L1, electrode C1, and pixel electrode E) is exposed to the photoresist layer formed using ultraviolet light, and development is performed in step S116. Thereby forming a predetermined pattern on the photoresist layer. Next, in step S117, the 2 nd substrate P2 is immersed in an etchant of ferric oxide, and the photoresist layer having the predetermined pattern is etched using the photoresist layer as a mask, so that the source electrode S, the drain electrode D, and the like are formed on the 1 st conductive layer 102. At this time, an opening portion of the contact hole H for forming the electroless contact M is also formed in the 1 st conductive layer 102. Next, in step S118, the photoresist layer on the 1 st conductive layer 102 is stripped, and the 2 nd substrate P2 is cleaned. The steps of steps S114 to S118 are the same as those of steps S44 to S48 of fig. 8, except that the contact hole H is formed.
Next, by etching using photolithography, as shown in fig. 29, the functional layer 112 (the semiconductor layer 108 and the insulating layer 110) in the contact hole H is etched. That is, in step S119, a photoresist layer is formed on the surface side (1 st conductive layer 102 side) of the 2 nd substrate P2. Next, in step S120, the predetermined pattern is exposed to the formed photoresist layer using ultraviolet rays, and development is performed in step S121. Thereby forming a predetermined pattern on the photoresist layer. Next, in step S122, the functional layer 112 in the contact hole H is etched by immersing the 2 nd substrate P2 in an etchant of hydrogen fluoride and etching the photoresist layer having the predetermined pattern as a mask. Thereby, the contact hole H is completed.
Thereafter, in step S123, electroless plating is performed on the contact hole H, and as shown in fig. 30, an electroless plated contact M composed of, for example, cu, cr, niP is formed, and the 1 st conductive layer 102 (wiring L1) and the 2 nd conductive layer 104 (wiring L2) are electrically connected. Next, in step S124, the photoresist layer on the 2 nd substrate P2 is stripped, and the 2 nd substrate P2 is cleaned. Through the above steps, a pixel circuit as shown in fig. 20 can be manufactured.
In addition, although the thin film is processed by etching using photolithography in embodiment 1 (including modifications) and embodiment 2, any method may be used as long as the thin film is processed by a photo-patterning method. As a processing process using the photo patterning method, there are, for example, a method of etching a resist layer coated on the 2 nd conductive layer 52c by irradiating ultraviolet pattern light in a state where the 1 st substrate P1 on which the laminated structure 52 is formed is immersed in a special liquid, a method of directly removing (etching) the 2 nd conductive layer 52c by irradiating ultraviolet pattern light with a spot of a laser beam having a high NA concentration, and the like, in addition to an etching process using a photolithography method.
In embodiment 1 (including modifications) and embodiment 2, a TFT of a bottom gate structure is described as an example, but a TFT of a top gate structure may be used. The layered structures 52 and 72 formed on the 1 st substrate P1 (supporting substrate) are not limited to Thin Film Transistors (TFTs), and are also useful for manufacturing electronic devices including Thin Film Diodes (TFDs). In the structure of the laminated structure 52, 72, etc., the functional layer 52b (72 b) sandwiched between the 1 st conductive layer and the 2 nd conductive layer may be a thin film of 2 or more layers. For example, when the functional layer 52b (72 b) is formed by laminating the 1 st functional film and the 2 nd functional film, the 1 st functional film may be formed on the 1 st substrate P1 in the same manner as in the region corresponding to the entire device region, and the 2 nd functional film may be selectively formed on a part of the region on the 1 st functional film.
In embodiment 1 (including modifications) and embodiment 2, the thickness Ra value of the surface of the insulating layer or the semiconductor layer of the laminated structure is set to be not more than the range of the thickness of the insulating layer (or the semiconductor layer) to be laminated, when the thickness of the surface of the 1 st substrate P1 (supporting substrate such as a metal foil) is expressed by the arithmetic average thickness Ra value (nm) defined by the JIS standard. However, in order to ensure a long-term stable operation as a TFT, the roughness Ra value of the surface of the 1 st substrate P1 is preferably set to 200nm or less (ultra-micron or less), more preferably, to a range of 1nm to tens of nm. The smaller the roughness Ra value is, the more the electronic mobility, ON/OFF ratio, and leakage current characteristics as the electrical characteristics of the TFT are improved. The roughness Ra value may be less than 1nm, but may be about several nm as a practical roughness Ra value. Such coarseness is of Ra values can be readily prepared by current surface treatment (grinding) techniques. In addition, when the 1 st conductive layer (52 a, 72a, 84a, 102) of the laminated structure is formed on the surface of the 1 st substrate P1, instead of planarizing the surface of the 1 st substrate P1 by polishing or the like, a planarizing film may be formed on the surface of the 1 st substrate P1, and then the release layer (50, 70, 80, 106) and the 1 st conductive layer (52 a, 72a, 84a, 102) may be formed on the planarizing film in this order. The planarization film is made of a material such as silicon oxide (SiO) which fills the concave portion and the uneven portion of the surface of the 1 st substrate P1 and has strong etching resistance and is not denatured by heat treatment during transfer (lamination) or post annealing (post annealing) 2 ) Is a wet material. As a material of such a planarizing film, a planarizing material SOG (Spin On Glass) sold by sumisefine (registered trademark) manufactured by sumiko osaka cement corporation, BISUTOREITA (registered trademark) manufactured by soyama corporation, japan, colsat (registered trademark) manufactured by colsat corporation, hanwei union corporation, hitachi chemical corporation, etc. can be used.
Variations of the above embodiments
The above-described embodiments (including modifications) may be modified as follows.
Modification 1
Fig. 31 is a schematic configuration of a film forming apparatus 10A for continuously forming a build-up structure for electronic components on a 1 st substrate P1, as in the film forming apparatus 10 of fig. 1. The film forming apparatus 10A of fig. 31 includes a processing chamber 16, a vacuum pump 18, a film forming rotary cylinder 22, a plurality of substrates 20A,20b,20c disposed around the film forming rotary cylinder 22 for continuously depositing a plurality of film forming materials (film raw materials), and guide rollers GR1 to GR3. As described in the previous embodiments and modifications, a 2-layer structure including a conductive layer (a metal film, an ITO film, or the like) and an insulating layer (a dielectric film) or a 3-layer structure including a semiconductor layer formed on the 2-layer structure is formed on the 1 st substrate P1. Therefore, the substrate 20A disposed around the film-forming rotary cylinder 22 forms a conductive layer by vapor deposition, sputtering, CVD, or the like, the substrate 20B forms an insulating layer on the conductive layer by vapor deposition, sputtering, CVD, or the like, and the substrate 20C forms a semiconductor layer on the insulating layer by vapor deposition, sputtering, CVD, or the like. In the case of forming a 2-layer structure of the conductive layer and the insulating layer on the 1 st substrate P1, the substrate 20C may not be formed. Further, depending on the structure of the TFT to be formed, the arrangement of the substrate 20B and the substrate 20C may be replaced, and the film formation may be performed in the order of the conductive layer, the semiconductor layer, and the insulating layer.
As described above, by disposing the film forming portions of the plurality of thin film material substrates 20a,20b,20c sequentially around the film forming rotary cylinder 22, a desired laminated structure is formed at a time on the surface of the 1 st substrate P1 wound up by the recovery roll 14, and therefore, it is not necessary to provide the recovery roll 14 in a separate film forming apparatus, and productivity is improved. In this case, it is preferable that the temperature be set to be the same in the film forming portion of the substrate 20A, the film forming portion of the substrate 20B, and the film forming portion of the substrate 20C. Further, as the film forming apparatus 10A, an apparatus using an atomization deposition method (atomization CVD method) disclosed in, for example, international publication No. 2013/17682 can be used. In this case, the base material of the film-forming material is contained in an ionic state or a nanoparticle state in mist sprayed on the surface of the 1 st substrate P1. Further, when the non-equilibrium atmospheric pressure plasma is generated in the space between the mist spray nozzle and the surface of the 1 st substrate P1 by using the high-voltage pulse electrode, even if the temperature of the 1 st substrate P1 is about 200 ℃, the favorable film formation by the mist CVD method can be performed, and the film formation rate is improved.
Modification 2
Fig. 32 is a schematic diagram showing a modification of the transfer method of fig. 9A to 9D and 10A to 10C, and members (layers, films, materials, etc.) having the same symbols as those of fig. 9A to 9D and 10A to 10C are given the same symbols. In the example of fig. 9A to 9D, as shown in fig. 9B, the peeling layer 70, the 1 st conductive layer 72a, the semiconductor layer 72B1, the insulating layer 72B2, and the 2 nd conductive layer 72C are sequentially stacked on the 1 st substrate P1, and then the 2 nd conductive layer 72C is etched to form a gate electrode as shown in fig. 9C. In the same manner as in the 1 st substrate P1 shown in fig. 32, the peeling layer 70, the 1 st conductive layer 72a, the semiconductor layer 72b1, the insulating layer 72b2, and the 2 nd conductive layer 72c are laminated, but in this modification, the semiconductor layer 72b1 is selectively formed in a partial region of the TFT corresponding to the channel portion (gap portion between the source electrode and the drain electrode) instead of the semiconductor layer 72b1 being formed on the 1 st conductive layer 72 a. In this case, a resist layer is formed over the 1 st conductive layer 72a, an opening of the resist layer is formed in a region where the semiconductor layer 72b1 is to be formed by photolithography, and a semiconductor material is deposited in the opening by vapor deposition, sputtering, CVD, or the like.
Thereafter, in the modification example of fig. 32, the insulating layer 72b2 is formed so as to cover the 1 st conductive layer 72a as well as the selectively formed semiconductor layer 72b1, and the 2 nd conductive layer 72C is further formed on the insulating layer 72b2, and the 2 nd conductive layer 72C is processed into a gate electrode (and wiring connected thereto) by etching treatment using a photolithography method as in the case of fig. 9C. In this modification, the semiconductor layer 72b1 can be selectively formed in a film formation region of the TFT, and therefore the amount of the semiconductor material used can be suppressed. As described above, when the laminated structure 72 formed on the 1 st substrate P1 is transferred to the 2 nd substrate P2, the adhesive layer 74 is applied to the surface of the laminated structure 72 of the 1 st substrate P1 in the previous fig. 9D, but in this modification, the adhesive layer 74 is formed on the 2 nd substrate P2 side as shown in fig. 32. The 2 nd substrate P2 in the present modification is constituted by a buffer layer P2b made of Polyethylene (PE) or the like on the surface area of a sheet-like substrate P2a made of PET, PEN or the like, and an adhesive layer 74 is formed on the surface of the buffer layer P2b by a sealing layer (Silicon sealer or the like) P2 c.
As shown in fig. 32, when the laminated structure 72 on the 1 st substrate P1 side is formed with the selective semiconductor layer 72b1 or the gate electrode, irregularities may be generated on the surface of the laminated structure 72 facing the 2 nd substrate P2, and thus adhesion to the 2 nd substrate P2 may not be uniform during transfer. Therefore, the buffer layer P2b is provided to absorb such irregularities. The buffer layer P2b is preferably a material having stability and plasticity, and is preferably a material having thermal plasticity such as Polyethylene (PE) when thermally crimping is performed during transfer. In the present modification, the adhesive layer 74 formed on the buffer layer P2b is a synthetic resin emulsion adhesive EVA (Ethylene Vinyl Acetate) mainly composed of a vinyl acetate resin or an ethylene-vinyl acetate copolymer resin. By adopting such a configuration, the laminated structure 72 on the 1 st substrate P1 side having irregularities can be precisely transferred to the 2 nd substrate P2 side without being damaged by cracks or the like.
Modification 3
As shown in fig. 32, although the transfer can be performed well when the adhesive layer 74 (EVA) is used, if the roughness of the laminated structure 72 on the 1 st substrate P1 side is large, there is a possibility that fine cracks may occur in the adhesive layer 74 (EVA) after curing, particularly in the upper part or the vicinity of the 2 nd conductive layer 72c of the laminated structure 72, due to internal stress generated when the adhesive layer 74 (EVA) is cured. Accordingly, after the laminated structure 72 (the 1 st conductive layer 72a, the semiconductor layer 72b1, the insulating layer 72b2, and the 2 nd conductive layer 72 c) is formed on the 1 st substrate P1 as shown in fig. 32, the planarizing film FP is formed so as to cover the entire laminated structure 72 as shown in fig. 33. The planarization film FP is made of a material which fills the recesses and irregularities of the laminated structure 72, has high etching resistance, and is not denatured by heat treatment during transfer (lamination) or post-annealing, such as silicon oxide (SiO) 2 ) Is a wet material. As a material of the planarization film FP, a planarization material SOG (Spin On Glass) sold by sumisefine (registered trademark) manufactured by sumiko osaka cement corporation, BISUTOREITA (registered trademark) manufactured by soyama corporation, japan, colcat (registered trademark) manufactured by colcat corporation, hanwei corporation, hitachi chemical corporation, etc. can be used. Then, after the material of the planarizing film FP is completely dried or during the drying, the laminated structure 72 having the planarizing film FP is pressure-bonded and transferred to the adhesive layer 74 (EVA) on the 2 nd substrate P2.
The planarizing film FP is an inorganic insulating film (or an organic insulating film) and has an effect of reducing cracks caused by internal stress when the adhesive layer 74 (EVA) is cured by direct bonding with the laminated adhesive layer 74 (EVA). In fig. 33, although the laminated structure 72 is formed on the 1 st substrate P1 and then the wet material of the planarization film FP is applied thereon, as shown in fig. 32, the adhesive layer 74 (EVA) may be formed on the 2 nd substrate P2 and then the planarization film FP may be formed on the adhesive layer 74 (EVA), and before the planarization film FP is dried, the laminated structure 72 on the 1 st substrate P1 may be transferred to the planarization film FP while being heated. In fig. 32 and 33, the 1 st conductive layer 72a on the 1 st substrate P1 side of the laminated structure 72 is described as the source electrode/drain electrode of the TFT and the wiring connected thereto, and the 2 nd conductive layer 72c on the 2 nd substrate P2 side is described as the gate electrode of the TFT and the wiring connected thereto, but the opposite may be adopted. That is, the 1 st conductive layer 72a may be used as a gate electrode of a TFT and a wiring connected thereto, and the 2 nd conductive layer 72c may be used as a source electrode/drain electrode of a TFT and a wiring connected thereto.
[ embodiment 3 ]
Fig. 34A to 34D to 36A to 36B are views showing steps of manufacturing an electronic device (TFT) in which a part of the manufacturing method of the embodiment of fig. 23 to 30 is modified. The same reference numerals as those in fig. 23 to 30 are given to the same members (materials) as those in fig. 23 to 30 among the members (materials) shown in fig. 34A to 36B. In this embodiment, as shown in fig. 34A, the 1 st substrate P1 is a copper (Cu) sheet-like foil plate having a thickness of several tens μm to several hundreds μm, and the 1 st conductive layer 102 of copper (Cu) is provided on the entire surface thereof via the release layer 106. The 1 st conductive layer 102 is formed by laminating a copper foil rolled to a thickness of several tens μm or less on the release layer 106. The 1 st conductive layer 102 after lamination is polished so that the arithmetic average roughness Ra value of the surface becomes about several nm to ten nm while reducing the thickness thereof.
Next, as shown in fig. 34B, an insulating layer 110 functioning as a gate insulating film of the TFT is formed on the 1 st conductive layer 102 of the 1 st substrate P1. The insulating layer 110 is typically a silicon oxide film (SiO 2 ) The silicon oxide film may be formed by a method of removing a silicon oxide film other than a formation region of the TFT by etching or the like after the entire surface of the 1 st conductive layer 102 is formed, a method of depositing a silicon oxide film selectively from the first, i.e., only the formation region of the TFT, or the like. Since the 1 st substrate P1 and the 1 st conductive layer 102 are both copper (Cu) having high heat resistance, a film can be formed at a high temperature in a vacuum, and the flatness (roughness Ra of the silicon oxide film can be improved ) Good.
Next, as shown in fig. 34C, a silicon oxide layer is formed on the insulating layer 110 (SiO 2 ) And a semiconductor layer 108 is formed thereon. Here, the semiconductor layer 108 is an IGZO (Oxide semiconductor) composed of Indium (Indium), gallium (Gallium), zinc (Zinc), and oxygen (Oxide). The IGZO semiconductor layer 108 is formed by a sputtering apparatus using an oxide sintered body in which an atomic ratio of indium relative to a total amount of indium and gallium and an atomic ratio of zinc relative to a total amount of indium and gallium and zinc are set to a predetermined ratio as a sputtering target, with indium, gallium, zinc, and oxygen as constituent elements. Before the sputtering step, a process of forming a window corresponding to the formation region of the semiconductor layer 108 by a photolithography step (exposure of a pattern and development of a resist) is performed on the entire resist layer formed on the 1 st substrate P1, and after the IGZO semiconductor is sputtered by a sputtering apparatus, a step of peeling off the resist layer is also performed. Thereby, as shown in fig. 34C, the semiconductor layer 108 of IGZO is selectively formed on the insulating layer 110.
Next, as shown in fig. 34D, the source electrode 104 (S) and the drain electrode 104 (D) as the 2 nd conductive layer 104 are arranged to face each other with a certain gap therebetween so as to form a Channel portion (Channel) on the semiconductor layer 108. In the same manner, a window of a resist layer is formed in a region where the source electrode 104 (S) and the drain electrode 104 (D) are formed by a photolithography step, and metallic source electrode 104 (S) and drain electrode 104 (D) are deposited by vapor deposition or the like in the window. The source electrode 104 (S) and the drain electrode 104 (D) are preferably gold (Au) having a large work factor because they are bonded to the semiconductor layer 108, but may be other metal materials (aluminum, copper) or conductive ink materials including silver nanoparticles or metallic carbon nanotubes. Here, the source electrode 104 (S) and the drain electrode 104 (D) are formed as the 1 st conductive layer 102 extending from the channel portion to the outside of the region of the insulating layer 110 as shown in fig. 34D, and the source electrode 104 (S) and the drain electrode 104 (D) are in an electrically conductive state (ohmic contact) with the 1 st conductive layer 102. Through the above steps, the multilayer structure 100 (the 1 st conductive layer 102, the insulating layer 110, the semiconductor layer 108, and the 2 nd conductive layer 104) is formed on the 1 st substrate P1.
Fig. 35 is a view showing a planar arrangement configuration of the multilayer structure 100 formed on the 1 st substrate P1. As the electrical characteristics of the TFT, it is desirable that both the electron mobility and the ON/OFF ratio are high and the leakage current is sufficiently small. In this embodiment, the surface of the 1 st conductive layer 102 as a base of the TFT is made smooth, and the arithmetic average roughness Ra value is sufficiently small. Therefore, the insulating layer 110 and the semiconductor layer 108 formed thereon are also formed as a flat film of uniform thickness, and the flatness of the contact interface between the semiconductor layer 108 and the 2 nd conductive layer 104 (source electrode and drain electrode) is also well maintained. Thus, the electron mobility, ON/OFF ratio, and leakage current are all excellent. Further, since the gap between the source electrode 104 (S) and the drain electrode 104 (D) in the channel portion can be made small, which is about several μm, a high-performance TFT exhibiting IGZO semiconductor characteristics can be obtained. As shown in fig. 35, the insulating layer 110, the semiconductor layer 108, and the 2 nd conductive layer 104 (source electrode and drain electrode) must be stacked relatively on the order of micrometers. Therefore, in the photolithography step, an alignment operation is required, that is, an alignment sensor in the exposure apparatus detects the position of an alignment mark formed at a specific position on the 1 st substrate P1 (particularly, the 1 st conductive layer 102) to adjust the pattern exposure position.
Fig. 36A to 36B are diagrams showing the case where the laminated structure 100 shown in fig. 34A to 34D and 35 is transferred to the 2 nd substrate P2 and further subjected to processing. Fig. 36A shows a state immediately after the laminated structure 100 on the 1 st substrate P1 is transferred to the 2 nd substrate P2 by the transfer (lamination) step. In the present embodiment, as described above with reference to fig. 33, a planarization film FP covering the entire laminated structure 100 of the 1 st substrate P1 is formed on the 1 st substrate P1 before transfer, and as described above with reference to fig. 32, a buffer layer P2b of polyethylene resin is formed on the surface of a PET sheet-like substrate P2a to a predetermined thickness of the 2 nd substrate P2, and an adhesive layer (EVA) 114 of vinyl acetate resin is formed on the 2 nd substrate P2 to a predetermined thickness. At the time of transfer, the laminated structure 100 is peeled from the 1 st substrate P1 by curing the adhesive layer (EVA) 114 by heating while pressing the planarization film FP on the 1 st substrate P1 and the adhesive layer (EVA) 114 on the 2 nd substrate P2 at a predetermined pressure. As a result, as shown in fig. 36A, the laminated structure 100 is bonded to the 2 nd substrate P2 with the 1 st conductive layer (Cu) 102 exposed at the uppermost surface.
In the state immediately after transfer shown in fig. 36A, residue of the peeling layer 106 may adhere to the surface of the 1 st conductive layer 102. In this case, the surface of the 1 st conductive layer 102 may be cleaned or polished. In particular, when the thickness of the 1 st conductive layer 102 is about several tens μm, since it may take time to perform the subsequent processing (particularly etching) of the 1 st conductive layer 102, the polishing step may be performed first, and the thickness of the 1 st conductive layer 102 may be about several μm. In this embodiment, since the buffer layer P2b, the adhesion layer 114 of EVA, and the planarizing film FP are provided, internal TFT breakage (cracks and breaks) can be suppressed by external force during polishing of the 1 st conductive layer 102 surface. In addition, when the alignment mark formed at each of the plurality of positions of the 1 st conductive layer 102 is a fine through hole (for example, a circle having a diameter of 20 μm, a rectangle having an angle of 20 μm, or the like) among the alignment marks used in the photolithography step in manufacturing the multilayer structure 100 of the TFT on the 1 st substrate P1, the 1 st conductive layer 102 is the uppermost surface as shown in fig. 36A, and therefore, the alignment mark can be easily detected by the alignment sensor of the exposure apparatus. In the photolithography step, the position of the TFT under the 1 st conductive layer 102, particularly, the positions of the source electrode 104 (S) and the drain electrode 104 (D) can be accurately specified with reference to the position of the alignment mark when the 1 st conductive layer 102 is processed.
A resist layer is applied to the surface of the 1 st conductive layer 102 in fig. 36A, and pattern light corresponding to the shapes of the gate electrode, the source electrode, the drain electrode, and the wiring connected to the electrodes of the TFT is exposed to the resist layer by an exposure device. At this time, the projection position of the pattern light is precisely set by detecting the alignment mark formed on the 1 st conductive layer 102 by the alignment sensor of the exposure device. By the development process of the resist layer after exposure and the etching process of the 1 st conductive layer 102 (Cu), the gate electrode 102G, the source electrode 102S, and the drain electrode 102D (and wirings connected to these electrodes) of the 1 st conductive layer 102 are formed as shown in fig. 36B. At this time, alignment and patterning are performed so that the etched source electrode 102S is bonded to the source electrode 104 (S) directly bonded to the semiconductor layer 108, and the drain electrode 102D is bonded to the drain electrode 104 (D) directly bonded to the semiconductor layer 108. Further, the etched gate electrode 102G is patterned so as to cover the channel portion (gap portion between the source electrode 104 (S) and the drain electrode 104 (D)) shown in fig. 35.
Fig. 37 is a view showing an example of a planar arrangement configuration of the TFT of fig. 36B, and an arrow section of 36B to 36B' in fig. 37 is fig. 36B. The unnecessary portion of the 1 st conductive layer 102 is removed by etching, but the insulating planarizing film FP is exposed at the removed portion. In order to manufacture an electronic device, when more functional devices (a resistor, a capacitor, a light emitting device, a light receiving device, an IC, and the like) are formed on the 2 nd substrate P2, the functional devices can be soldered to a wiring portion or the like formed with the 1 st conductive layer 102. In the case where the 1 st conductive layer 102 is copper (Cu), an insulating and heat-resistant film that prevents corrosion due to oxidation may be selectively or entirely formed.
As described above, in the present embodiment, in order to sufficiently reduce the arithmetic average roughness Ra value of the 1 st conductive layer 102 of the multilayer structure 100 formed on the 1 st substrate P1 and to enable the use of the vacuum manufacturing process or the high temperature manufacturing process, a metal foil (copper foil) is used as the 1 st substrate P1, whereby a TFT with high performance can be formed. Therefore, the performance of the electronic device (display panel, touch panel, sheet sensor, etc.) fabricated on the flexible 2 nd substrate P2 can be improved in a jump manner. In the present embodiment, the 2 nd conductive layer 104 in the multilayer structure 100 formed on the 1 st substrate P1 is processed into the source electrode and the drain electrode of the TFT, but the 2 nd conductive layer 104 may be processed into the gate electrode. In this case, in the steps of manufacturing the TFT (the stacked structure 100) shown in fig. 34A to 34D, the order (vertical relationship) of the insulating layer 110 and the semiconductor layer 108 stacked on the 1 st conductive layer 102 may be reversed. That is, the semiconductor layer 108 is formed in a predetermined region on the 1 st conductive layer 102, the insulating layer 110 is formed thereon in a size that completely covers the semiconductor layer 108, and the gate electrode of the 2 nd conductive layer 104 is formed on the insulating layer 110 so as to be partially connected to the 1 st conductive layer 102.
In the above embodiment, the 1 st substrate P1 is a copper (Cu) sheet-like foil, and the 1 st conductive layer 102 of the laminated structure 100 is formed on the surface thereof with the release layer 106 interposed therebetween, but the copper (Cu) sheet-like foil of the 1 st substrate P1 itself may be formed as the 1 st conductive layer 102 of the laminated structure 100. In this case, the 1 st substrate P1 may be a metal foil (copper foil) rolled to have a sufficiently small arithmetic average roughness Ra value of its surface, and the surface may be further polished as necessary.
In the case where the 1 st conductive layer 102 is the 1 st substrate P1, since the 1 st substrate P1 itself is the 1 st conductive layer 102 (electrode, wiring) transferred to the 2 nd substrate P2 side, it is preferable to perform polishing treatment for reducing the thickness of the 1 st substrate P1 (1 st conductive layer 102) immediately after the transfer step, for example. In this way, when the 1 st substrate P1 itself is the 1 st conductive layer 102, the entire laminated structure (conductive layer, insulating layer, semiconductor layer) including the 1 st substrate P1 is transferred to the 2 nd substrate P2 side, and as a result, the 1 st substrate P1 is also transferred to the 2 nd substrate P2 side.
In the present embodiment described above, the 1 st conductive layer 102 (or the 1 st substrate P1 itself) and the 2 nd conductive layer 104 are laminated with the insulating layer 110 and the semiconductor layer 108 interposed therebetween, but as shown in fig. 5B to 5F, the 1 st conductive layer 102 (or the 1 st substrate P1 itself) and the 2 nd conductive layer 104 may be laminated with only the insulating layer (or only the semiconductor layer) interposed therebetween.
In this way, when the 1 st substrate P1 itself is formed as a part of the laminated structure, the device manufacturing method for transferring the 1 st substrate on which at least a part of the laminated structure constituting the electronic device is formed onto the 2 nd substrate is to perform the 1 st step of preparing the 1 st substrate as the 1 st conductive layer made of the conductive material, forming the functional layer made of at least one of the insulating and semiconductor materials on the 1 st conductive layer, forming the 2 nd conductive layer made of the conductive material on the functional layer, thereby forming the laminated structure, and the 2 nd step of temporarily bringing the 1 st substrate and the 2 nd substrate close to or in close contact with each other so that the 2 nd conductive layer is located on the 2 nd substrate side, thereby transferring the laminated structure including the 1 st substrate onto the 2 nd substrate.
When the 1 st substrate P1 itself is formed as a part of the laminated structure, a transfer substrate for transferring at least a part of the laminated structure constituting an electronic component to a transfer substrate includes a conductive foil (for example, a metal foil) functioning as the 1 st conductive layer by a conductive material, a functional layer formed on the 1 st conductive layer by a material of at least one of insulation and a semiconductor, and a 2 nd conductive layer formed on the functional layer by a conductive material. In this case, the transfer substrate is entirely transferred (bonded) to the transferred substrate.
In the embodiment of fig. 34A to 34D, although a copper foil is laminated on the 1 st substrate P1 with the release layer 106 interposed therebetween as the 1 st conductive layer 102, a foil of aluminum (Al), zinc (Zn), molybdenum (Mo), nickel (Ni), tantalum (Ta), tin (Sn), stainless steel (SUS), or a foil made of such an alloy, or a foil of such a foil plated with gold (Au) may be laminated as the 1 st conductive layer 102. Although these metal foils are produced as rolled foils and electrolytic foils (plated foils), the back surface facing the 1 st substrate P1 must have a certain degree of roughness (for example, about 200nm in terms of the arithmetic average roughness Ra value) in order to improve adhesion during lamination. On the other hand, the surface of the metal foil on which the functional layer (insulating layer, semiconductor layer, etc.) is formed must be a smooth surface having a roughness Ra value of about several nm to several tens nm. In the case where the 1 st conductive layer 102 is a metal foil, the roughness Ra values of the front and rear surfaces of the metal foil may be intentionally different, and a surface having a large roughness Ra value may be referred to as a 1 st substrate P1 side and a surface having a small roughness Ra value may be referred to as a surface on which the laminated structure is formed.

Claims (14)

1. A method for manufacturing a device, which transfers a 1 st substrate on which at least a part of a laminated structure constituting an electronic device is formed to a 2 nd substrate, includes:
Step 1, preparing the 1 st substrate as a 1 st conductive layer formed of a conductive material, forming a functional layer formed of at least one of an insulating material and a semiconductor material on the 1 st conductive layer, and forming a 2 nd conductive layer formed of a conductive material on the functional layer to form the laminated structure;
a step 2 of temporarily bringing the 1 st substrate into close contact with or close contact with the 2 nd substrate so that the 2 nd conductive layer is located on the 2 nd substrate side, thereby transferring the laminated structure including the 1 st substrate to the 2 nd substrate; and
a step 3 of forming an alignment mark for detecting a position of the 2 nd substrate on the 2 nd conductive layer or the 1 st conductive layer between the 1 st step and the 2 nd step or after the 2 nd step; and is also provided with
The interface between the 1 st conductive layer and the functional layer formed on the 1 st substrate or the interface between the functional layer and the 2 nd conductive layer is planarized at a level of submicron or less.
2. The device manufacturing method according to claim 1, wherein,
the functional layer is constituted by a single insulating layer made of the insulating material, or by a laminate of an insulating layer made of the insulating material and a semiconductor layer made of the semiconductor material.
3. The device manufacturing method according to claim 2, comprising a 4 th step of applying an additional process to the laminated structure from the 1 st conductive layer side which is the surface of the laminated structure transferred to the 2 nd substrate.
4. The device manufacturing method according to claim 3, wherein the electronic device is a thin film transistor;
the 1 st step includes a step of forming a gate electrode by applying a process treatment using a photo patterning method to the 2 nd conductive layer;
the 4 th step includes a step of forming a source electrode and a drain electrode by applying a process treatment using a photo patterning method to the 1 st conductive layer of the laminated structure.
5. The device manufacturing method according to claim 3, wherein the electronic device is a bottom-contact thin film transistor;
the functional layer is an insulating layer made of insulating materials;
the 1 st step includes a step of forming a gate electrode of the thin film transistor by processing the 2 nd conductive layer;
the 4 th step includes a step of forming a semiconductor layer between a source electrode and a drain electrode of the thin film transistor by processing the 1 st conductive layer.
6. The device manufacturing method according to claim 3, wherein the electronic device is a top-contact thin film transistor;
the functional layer is composed of a semiconductor layer deposited on the 1 st conductive layer using the semiconductor material, and an insulating layer deposited on the semiconductor layer using the insulating material.
7. The device manufacturing method according to claim 1, wherein the electronic device is a top-contact thin film transistor;
the step 1 includes:
a step of forming a source electrode and a drain electrode of the thin film transistor by applying a process treatment using a photo patterning method to the 1 st conductive layer before forming the functional layer; forming a semiconductor layer formed of the semiconductor material between the source electrode and the drain electrode; forming the 2 nd conductive layer on the semiconductor layer after forming an insulating laminated layer made of the insulating material; and a step of forming a gate electrode by further performing a process treatment using a photo patterning method on the 2 nd conductive layer.
8. A transfer substrate for temporarily holding a laminate structure constituting an electronic component at a predetermined position on a substrate to be transferred on which the electronic component is formed, the transfer substrate comprising:
A conductive foil functioning as a 1 st conductive layer using a conductive material;
a functional layer formed on the surface of the conductive foil using at least one of an insulating material and a semiconductor material; and
a 2 nd conductive layer formed on the functional layer using a conductive material;
the interface between the conductive foil and the functional layer or the interface between the functional layer and the 2 nd conductive layer is planarized at a level of submicron or less, and an alignment mark for aligning with the position of the transferred substrate at the time of transfer of the laminate structure is formed on the conductive foil or the 2 nd conductive layer.
9. The transfer substrate according to claim 8, wherein the electronic element comprises a thin film transistor;
the functional layer is composed of a single insulating layer made of the insulating material, or a laminate of a semiconductor layer made of the semiconductor material and an insulating layer made of the insulating material.
10. The transfer substrate according to claim 9, wherein,
the functional layer and the 2 nd conductive layer are laminated on the surface of the conductive foil so as to cover the entire surface of the conductive foil.
11. The transfer substrate according to claim 10, wherein,
Any one or all of the functional layer and the 2 nd conductive layer are formed by vapor deposition, sputtering, or CVD.
12. The transfer substrate according to claim 9, wherein,
the conductive material to be the 2 nd conductive layer is a metal material or ITO.
13. The transfer substrate of claim 12, wherein,
the conductive foil is copper foil, and the conductive material to be the 2 nd conductive layer is copper.
14. The transfer substrate according to any one of claims 8 to 13, wherein,
the conductive foil is a flexible long substrate that can be conveyed in a roll-to-roll manner;
the functional layer and the 2 nd conductive layer are sequentially laminated by a roll-to-roll processing device on the conductive foil.
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